synplify.prj

#--  Synopsys, Inc.
#--  Version I-2013.09-SP1 
#--  Project file \\icnas4.cc.ic.ac.uk\mh1613\Git\VHDL_CWK\synplify.prj

#project files
add_file -vhdl -lib work "./hardware_files/config_pack.vhd"
add_file -vhdl -lib work "./hardware_files/db.vhd"
add_file -vhdl -lib work "./hardware_files/exercises.vhd"
add_file -vhdl -lib work "./hardware_files/project_pack.vhd"
add_file -vhdl -lib work "./hardware_files/rcb.vhd"
add_file -vhdl -lib work "./hardware_files/vdp.vhd"



#implementation: "rev_2"
impl -add rev_2 -type fpga

#
#implementation attributes

set_option -vlog_std sysv
set_option -project_relative_includes 1

#device options
set_option -technology CYCLONEII
set_option -part EP2C5
set_option -package QC208
set_option -speed_grade -6
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "vdp"

# altera_options
set_option -RWCheckOnRam 1

# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 1
set_option -srs_instrumentation 1

# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -quartus_version 13.1

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./rev_2/proj_1.vqm"

#design plan options
impl -active "rev_2"