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Fixes PathFInder
1 parent 9919c08 commit 6acc8fa

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3 files changed

+24
-10
lines changed

3 files changed

+24
-10
lines changed

README.md

+4-4
Original file line numberDiff line numberDiff line change
@@ -87,13 +87,13 @@ Streaming_matrix = [(1, 2, 3, 0)]
8787
| Source | destination | Muxex |
8888
|--------|-------------|-------|
8989
| 1 | 1 | 0 |
90-
| 1 | 3 | 14 |
91-
| 1 | 2 | 15 |
90+
| 1 | 3 | 3 |
91+
| 1 | 2 | 2 |
9292
| 1 | 1 | 0 |
93-
| 2 | 7 | 11 |
93+
| 2 | 7 | 0 |
9494
| -- | -- | -- |
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| -- | -- | -- |
96-
| 3 | 4 | 15 |
96+
| 3 | 4 | 1 |
9797
| 3 | 3 | 0 |
9898
9999
#### WaveForm

src/main/scala/components/Muxes.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,11 @@ class Muxes(implicit val config: MagmasiConfig) extends Module{
4545
when ((io.mat1(j)(i) =/= 0.U) && (io.mat2(i) =/= 0.U)) {
4646

4747
when(io.counterMatrix1(j)(i) < io.counterMatrix2(i)){
48-
mux(counter) := (io.mat2(i) - 1.U) - (io.mat1(j)(i) - 1.U)
48+
mux(counter) := (io.counterMatrix2(i) - 1.U) - (io.counterMatrix1(j)(i) - 1.U)
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src(counter) := io.mat2(i)
5050
dest(counter) := io.mat1(j)(i)
5151
}.otherwise{
52-
mux(counter) := (io.mat1(j)(i) - 1.U) - (io.mat2(i) - 1.U)
52+
mux(counter) := (io.counterMatrix1(j)(i) - 1.U) - (io.counterMatrix2(i) - 1.U)
5353
src(counter) := io.mat2(i)
5454
dest(counter) := io.mat1(j)(i)
5555
}

src/main/scala/components/SourceDestination.scala

+18-4
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ class SourceDestination(implicit val config: MagmasiConfig) extends Module {
3535
val valid1 = RegInit(false.B)
3636
val jValid = Reg(Bool())
3737
jValid := 0.B
38+
val kvalid = Reg(Bool())
3839
val k = RegInit(0.U(32.W))
3940

4041
val counter1 = RegInit(1.U(32.W))
@@ -56,15 +57,28 @@ class SourceDestination(implicit val config: MagmasiConfig) extends Module {
5657
}
5758

5859
when (io.Streaming_matrix(k) =/= 0.U) {
59-
counterRegs2(k) := counter2
60-
counter2 := counter2 + 1.U
60+
when (counter2 < (config.NUM_PES + 1).U) {
61+
counterRegs2(k) := counter1
62+
when (~((j === (config.MaxCols - 1).U) && (i === (config.MaxRows - 1).U))){
63+
counter2 := counter2 + 1.U
64+
}
6165
}
66+
}
6267
val reg_i = RegNext(((j === (config.MaxCols - 1).U) && (i === (config.MaxRows - 1).U)), 1.B)
6368
valid1 := Mux(((j === (config.MaxCols - 1).U) && (i === (config.MaxRows - 1).U)) === reg_i,1.B,0.B)
6469

65-
when (k >= 0.U){
66-
k := k + 1.U
70+
71+
// when ((k >= 0.U) && (kvalid === 0.B)){
72+
// k := k + 1.U
73+
// }
74+
75+
when(k === (config.MaxRows - 1).U){
76+
kvalid := 1.B
77+
}.elsewhen((k >= 0.U) && (kvalid === 0.B)){
78+
kvalid := 0.B
79+
k := k + 1.U
6780
}
81+
6882
when (jValid === 0.B){
6983
when(j < (config.MaxCols - 1).U) {
7084
j := j + 1.U

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