FlexDPUTester.cpp

#include <verilated.h>
#include <verilated_vcd_c.h>
#include "VFlexDPU.h"  // This header is generated by Chisel

int main(int argc, char** argv) {
    Verilated::commandArgs(argc, argv);
    
    // Initialize Verilator traces
    Verilated::traceEverOn(true);
    VerilatedVcdC* tfp = new VerilatedVcdC;

    // Create an instance of the generated Verilog module
    VFlexDPU* top = new VFlexDPU;

    // Trace the signals
    top->trace(tfp, 99);
    tfp->open("dump.vcd");

    // Initialize signals
    top->reset = 1;

    // for (int i = 0; i < 32; i++) {
    //     switch(i) {
               top->io_Stationary_matrix_0_0 = 1; 
               top->io_Stationary_matrix_0_1 = 2; 
               top->io_Stationary_matrix_1_0 = 3;  
               //top->io_Stationary_matrix_2_0 = 4; 
               top->io_Stationary_matrix_1_1 = 4; 
        
    
    // for (int i = 0; i < 32; i++) {
    //     switch(i) {
            top->io_Streaming_matrix_0_0 = 5;
            top->io_Streaming_matrix_0_1 = 6;
            // top->io_Streaming_matrix_0_3 = 0;
            top->io_Streaming_matrix_1_0 = 7;
            top->io_Streaming_matrix_1_1 = 8;
    
        
    //}
    // Simulation steps
    for (int cycle = 0; cycle < 2000; cycle++) {
        // Toggle clock
        top->clock = 1;
        top->eval();
        tfp->dump(cycle * 10 + 5);

        top->clock = 0;
        top->eval();
        tfp->dump(cycle * 10 + 10);

        if (cycle >= 2){
            top-> reset = 0;
        }
    }

    // ...


    // Close VCD
    tfp->close();
    delete top;
    return 0;
}