AcceleratoTop.anno.json

[
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|ReductionMux",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_0:EdgeAdderSwitch/reductionMux:ReductionMux",
    "index":0.3448275862068966
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|SimpleAdder",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_0:EdgeAdderSwitch/adder32:SimpleAdder",
    "index":0.3793103448275862
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|EdgeAdderSwitch",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_0:EdgeAdderSwitch",
    "index":0.41379310344827586
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|ReductionMux_1",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_1:EdgeAdderSwitch/reductionMux:ReductionMux",
    "index":0.4482758620689655
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|SimpleAdder_1",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_1:EdgeAdderSwitch/adder32:SimpleAdder",
    "index":0.4827586206896552
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|EdgeAdderSwitch_1",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_1:EdgeAdderSwitch",
    "index":0.5172413793103449
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|ReductionMux_2",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_2:EdgeAdderSwitch/reductionMux:ReductionMux",
    "index":0.5517241379310345
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|SimpleAdder_2",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_2:EdgeAdderSwitch/adder32:SimpleAdder",
    "index":0.5862068965517241
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|EdgeAdderSwitch_2",
    "duplicate":"~AcceleratoTop|AcceleratoTop/ACCL:Top/FDPU:FlexDPU/flexdpecom4:flexdpecom4/my_fan_network:Fan4/my_adder_2:EdgeAdderSwitch",
    "index":0.6206896551724138
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|gf180mcu_fd_ip_sram__sram512x8m8wm1",
    "duplicate":"~AcceleratoTop|AcceleratoTop/MMU:MMU/SRAM:SRAM/sram0:gf180mcu_fd_ip_sram__sram512x8m8wm1",
    "index":0.7931034482758621
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|gf180mcu_fd_ip_sram__sram512x8m8wm1_1",
    "duplicate":"~AcceleratoTop|AcceleratoTop/MMU:MMU/SRAM:SRAM/sram1:gf180mcu_fd_ip_sram__sram512x8m8wm1",
    "index":0.8275862068965517
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|gf180mcu_fd_ip_sram__sram512x8m8wm1_2",
    "duplicate":"~AcceleratoTop|AcceleratoTop/MMU:MMU/SRAM:SRAM/sram2:gf180mcu_fd_ip_sram__sram512x8m8wm1",
    "index":0.8620689655172413
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~AcceleratoTop|gf180mcu_fd_ip_sram__sram512x8m8wm1_3",
    "duplicate":"~AcceleratoTop|AcceleratoTop/MMU:MMU/SRAM:SRAM/sram3:gf180mcu_fd_ip_sram__sram512x8m8wm1",
    "index":0.896551724137931
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxInlineAnno",
    "target":"AcceleratoTop.gf180mcu_fd_ip_sram__sram512x8m8wm1",
    "name":"gf180mcu_fd_ip_sram__sram512x8m8wm1.v",
    "text":"/*\n * $Id: $\n * Copyright 2022 GlobalFoundries PDK Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * Project:             018 5VGREEN SRAM\n * Author:              GlobalFoundries PDK Authors\n * Data Created:        05-06-2014\n * Revision:\t\t0.0\n *\n * Description:         gf180mcu_fd_ip_sram__sram512x8m8wm1 Simulation Model\n */\n\n`timescale 1 ps / 1 ps\n\nmodule gf180mcu_fd_ip_sram__sram512x8m8wm1 (\n\tCLK,\n\tCEN,\n\tGWEN,\n\tWEN,\n\tA,\n\tD,\n\tQ,\n\tVDD,\n\tVSS\n);\n\ninput           CLK;\ninput           CEN;    //Chip Enable\ninput           GWEN;   //Global Write Enable\ninput   [7:0]  \tWEN;    //Write Enable\ninput   [8:0]   A;\ninput   [7:0]  \tD;\noutput\t[7:0]\tQ;\ninout\t\tVDD;\ninout\t\tVSS;\n\nreg\t[7:0]\tmem[511:0];\nreg\t[7:0]\tqo_reg;\n\nwire\t\tcen_flag;\nwire\t\twrite_flag;\nwire\t\tread_flag;\n\nreg             ntf_Tcyc;\t//notifier for clock period/low/high pulse\nreg             ntf_Tckh;\nreg             ntf_Tckl;\n\nreg\t\tntf_tcs;\t//notifier for setup time\nreg\t\tntf_tas;\nreg\t\tntf_tds;\nreg\t\tntf_tws;\nreg\t\tntf_twis;\n\nreg             ntf_tch;\t//notifier for hold time\nreg             ntf_tah;\nreg             ntf_tdh;\nreg             ntf_twh;\nreg             ntf_twih;\n\nwire\t\tno_st_viol;\t//no setup violation\nwire\t\tno_hd_viol;\t//no hold violation\nwire\t\tno_ck_viol;\t//no clock related violation\n\nreg             clk_dly;        //for read/write\nreg             write_flag_dly; //for write invalidation\nreg             read_flag_dly;  //for read invalidation\nreg             cen_dly;\nreg             cen_fell;       //detect CEN 1 -> 0 transition\nreg             cen_not_rst;    //detect CEN is not reset initially\n\nwire    [7:0]  we;       \t//inversion of WEN\nwire    [7:0]  cd2;\nwire    [7:0]  cd4;\nwire    [7:0]  cd5;\nreg    \t[7:0]  cdx;\n\nreg\t[8:0]\tmarked_a;\n\ninteger         i;\n\nassign Q = qo_reg;\n\n//---- for debugging\nwire    [7:0]  mem_0;\nwire\t[7:0]  mem_1;\nwire\t[7:0]  mem_2;\nwire\t[7:0]  mem_3;\nassign mem_0 = mem[0];\nassign mem_1 = mem[1];\nassign mem_2 = mem[2];\nassign mem_3 = mem[3];\n\nalways @(CEN) cen_dly = #100 CEN;\nalways @(CEN or cen_dly) begin\n  if (!CEN & cen_dly) cen_fell = 1'b1;\nend\n\nalways @(posedge CLK) begin\n  if (!CEN & !cen_fell & !cen_not_rst) cen_not_rst = 1;\nend\n\nalways @(posedge cen_not_rst) begin\n  $display(\"-------- WARNING: CEN is not reset, memory is not operational ---------\");\n  $display(\"-------- @Time %0t: scope = %m\", $realtime, \" ---------\");\nend\n\nalways @(posedge cen_fell) begin\n  $display(\"-------- MESSAGE: CEN is just reset, memory is operational ---------\");\n  $display(\"-------- @Time %0t: scope = %m\", $realtime, \" ---------\");\nend\n\nassign cen_flag   =  cen_fell & !CEN;\nassign write_flag =  cen_fell & !CEN & !GWEN & !(&WEN);\nassign read_flag  =  cen_fell & !CEN &  GWEN;\n\nreg cen_flag_dly;\nalways @(cen_flag) cen_flag_dly = #100 cen_flag;\n\nspecify\n  specparam Tcyc = 55600 : 55600 : 55600;\n  specparam Tckh = 25000 : 25000 : 25000;\n  specparam Tckl = 25000 : 25000 : 25000;\n\n  specparam tcs  = 5000 : 5000 : 5000;\n  specparam tas  = 5000 : 5000 : 5000;\n  specparam tds  = 5000 : 5000 : 5000;\n  specparam tws  = 5000 : 5000 : 5000;\n  specparam twis = 5000 : 5000 : 5000;\n\n  specparam tch  = 10000 : 10000 : 10000;\n  specparam tah  = 10000 : 10000 : 10000;\n  specparam tdh  = 10000 : 10000 : 10000;\n  specparam twh  = 10000 : 10000 : 10000;\n  specparam twih = 10000 : 10000 : 10000;\n\n  specparam ta   = 45000 : 45000 : 45000;\n\n  specparam Tdly  = 100 : 100: 100;\n\n//---- CLK period/pulse timing\n  $period (negedge CLK, Tcyc, ntf_Tcyc);\n  $width  (posedge CLK, Tckh, 0, ntf_Tckh);\n  $width  (negedge CLK, Tckl, 0, ntf_Tckl);\n\n//---- CEN setup/hold timing\n  $setup (negedge CEN, posedge CLK &&& cen_flag, tcs, ntf_tcs);\n  $setup (posedge CEN, posedge CLK &&& cen_flag, tcs, ntf_tcs);\n\n  $hold  (posedge CLK &&& cen_flag_dly, posedge CEN, tch, ntf_tch);\n  $hold  (posedge CLK &&& cen_flag,     negedge CEN, tch, ntf_tch);\n\n//---- GWEN setup/hold timing\n  $setup (negedge GWEN,  posedge CLK &&& cen_flag, tws, ntf_tws);\n  $setup (posedge GWEN,  posedge CLK &&& cen_flag, tws, ntf_tws);\n\n  $hold  (posedge CLK &&& cen_flag, posedge GWEN, twh, ntf_twh);\n  $hold  (posedge CLK &&& cen_flag, negedge GWEN, twh, ntf_twh);\n\n//---- WEN[7:0] setup/hold timing\n  $setup (negedge WEN[0],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (negedge WEN[1],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (negedge WEN[2],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (negedge WEN[3],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (negedge WEN[4],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (negedge WEN[5],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (negedge WEN[6],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (negedge WEN[7],  posedge CLK &&& write_flag, twis, ntf_twis);\n\n  $setup (posedge WEN[0],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (posedge WEN[1],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (posedge WEN[2],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (posedge WEN[3],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (posedge WEN[4],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (posedge WEN[5],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (posedge WEN[6],  posedge CLK &&& write_flag, twis, ntf_twis);\n  $setup (posedge WEN[7],  posedge CLK &&& write_flag, twis, ntf_twis);\n\n  $hold  (posedge CLK &&& write_flag, posedge WEN[0],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, posedge WEN[1],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, posedge WEN[2],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, posedge WEN[3],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, posedge WEN[4],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, posedge WEN[5],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, posedge WEN[6],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, posedge WEN[7],  twih, ntf_twih);\n\n  $hold  (posedge CLK &&& write_flag, negedge WEN[0],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, negedge WEN[1],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, negedge WEN[2],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, negedge WEN[3],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, negedge WEN[4],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, negedge WEN[5],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, negedge WEN[6],  twih, ntf_twih);\n  $hold  (posedge CLK &&& write_flag, negedge WEN[7],  twih, ntf_twih);\n\n//---- A[8:0] setup/hold timing\n  $setup (posedge A[0],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[1],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[2],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[3],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[4],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[5],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[6],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[7],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (posedge A[8],  posedge CLK &&& cen_flag, tas, ntf_tas);\n\n  $setup (negedge A[0],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[1],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[2],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[3],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[4],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[5],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[6],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[7],  posedge CLK &&& cen_flag, tas, ntf_tas);\n  $setup (negedge A[8],  posedge CLK &&& cen_flag, tas, ntf_tas);\n\n  $hold  (posedge CLK &&& cen_flag, negedge A[0],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[1],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[2],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[3],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[4],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[5],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[6],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[7],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, negedge A[8],  tah, ntf_tah);\n\n  $hold  (posedge CLK &&& cen_flag, posedge A[0],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[1],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[2],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[3],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[4],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[5],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[6],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[7],  tah, ntf_tah);\n  $hold  (posedge CLK &&& cen_flag, posedge A[8],  tah, ntf_tah);\n\n//---- D[7:0] setup/hold timing\n  $setup (posedge D[0],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (posedge D[1],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (posedge D[2],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (posedge D[3],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (posedge D[4],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (posedge D[5],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (posedge D[6],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (posedge D[7],  posedge CLK &&& write_flag, tds, ntf_tds);\n\n  $setup (negedge D[0],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (negedge D[1],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (negedge D[2],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (negedge D[3],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (negedge D[4],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (negedge D[5],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (negedge D[6],  posedge CLK &&& write_flag, tds, ntf_tds);\n  $setup (negedge D[7],  posedge CLK &&& write_flag, tds, ntf_tds);\n\n  $hold  (posedge CLK &&& write_flag, negedge D[0],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, negedge D[1],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, negedge D[2],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, negedge D[3],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, negedge D[4],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, negedge D[5],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, negedge D[6],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, negedge D[7],  tdh, ntf_tdh);\n\n  $hold  (posedge CLK &&& write_flag, posedge D[0],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, posedge D[1],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, posedge D[2],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, posedge D[3],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, posedge D[4],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, posedge D[5],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, posedge D[6],  tdh, ntf_tdh);\n  $hold  (posedge CLK &&& write_flag, posedge D[7],  tdh, ntf_tdh);\n\n//---- Output delay\n// rise transition:     0->1, z->1, Ta\n// fall transition:     1->0, 1->z, Ta\n// turn-off transition: 0->z, 1->z, Tcqx\n//if (!CEN & GWEN) (posedge CLK => (Q : 8'bx)) = (Ta, Ta, Tcqx);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[0]  : 1'bx)) = (ta, ta);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[1]  : 1'bx)) = (ta, ta);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[2]  : 1'bx)) = (ta, ta);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[3]  : 1'bx)) = (ta, ta);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[4]  : 1'bx)) = (ta, ta);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[5]  : 1'bx)) = (ta, ta);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[6]  : 1'bx)) = (ta, ta);\nif ((CEN == 1'b0) && (GWEN == 1'b1)) (posedge CLK => (Q[7]  : 1'bx)) = (ta, ta);\nendspecify\n\nassign no_st_viol = ~(|{ntf_tcs, ntf_tas, ntf_tds, ntf_tws, ntf_twis});\nassign no_hd_viol = ~(|{ntf_tch, ntf_tah, ntf_tdh, ntf_twh, ntf_twih});\nassign no_ck_viol = ~(|{ntf_Tcyc, ntf_Tckh, ntf_Tckl});\n\nalways @(CLK) clk_dly        = #Tdly CLK;\nalways @(CLK) write_flag_dly = #200 write_flag;\nalways @(CLK) read_flag_dly  = #200 read_flag;\n\nalways @(posedge CLK) marked_a = A;\n\nassign we  = ~WEN;\nassign cd2 = mem[A] & WEN;\t//set write bits to 0, others unchanged\nassign cd4 = D & we;\t\t//set write bits to 0/1, others = 0\nassign cd5 = cd2 | cd4;\t\t//memory content after write\n\nalways @(posedge CLK) cdx = {8{1'bx}} & we;    //latch cdx\n\nalways @(posedge clk_dly) begin\n  if (write_flag) begin \t//write\n    if (no_st_viol) begin \t//write, no viol\n      mem[A] = cd5;\n    end\n    else begin                 \t//write, with viol\n      mem[A] = mem[A] ^ cdx;    //1^x = x\n      qo_reg = qo_reg ^ cdx;\n    end\n  end //write\n  else if (read_flag) begin     //read\n    if (no_st_viol) begin \t//read, no viol\n      qo_reg = mem[marked_a];\n    end\n    else begin                  //read, with viol\n      qo_reg = 8'bx;\n    end\n  end //read\nend\n\nalways @(negedge clk_dly) begin         \t//invalidate write/read when hold/clk viol\n  if (no_hd_viol == 0 | no_ck_viol == 0) begin\n    if (write_flag_dly) begin\n      if (ntf_twh) begin\n        mem[marked_a] = mem[marked_a] ^ 8'bx; //GWEN can't be used to generate cdx\n        qo_reg        = qo_reg ^ 8'bx;\n      end\n      else begin\n        mem[marked_a] = mem[marked_a] ^ cdx;\n        qo_reg        = qo_reg ^ cdx;\n      end\n    end\n    else if (read_flag_dly) begin\n      qo_reg = 8'bx;\n    end\n\n    #100;\n    ntf_tch  = 0;\n    ntf_tah  = 0;\n    ntf_tdh  = 0;\n    ntf_twh  = 0;\n    ntf_twih = 0;\n\n    ntf_Tcyc  = 0;\n    ntf_Tckh  = 0;\n    ntf_Tckl  = 0;\n  end\n  else begin\n    #100;\n    ntf_tch  = 0;\n    ntf_tah  = 0;\n    ntf_tdh  = 0;\n    ntf_twh  = 0;\n    ntf_twih = 0;\n\n    ntf_Tcyc  = 0;\n    ntf_Tckh  = 0;\n    ntf_Tckl  = 0;\n  end\nend\n\nalways @(posedge ntf_tcs or posedge ntf_tas or posedge ntf_tds or\n         posedge ntf_tws or posedge ntf_twis or\n         posedge ntf_tch or posedge ntf_tah or posedge ntf_tdh or\n         posedge ntf_twh or posedge ntf_twih or\n         posedge ntf_Tcyc or posedge ntf_Tckh or posedge ntf_Tckl) begin\n  if (cen_fell) begin\n    #Tdly;\n    if (ntf_tcs)  $display(\"---- ERROR: CEN setup violation! ----\");\n    if (ntf_tas)  $display(\"---- ERROR: A setup violation! ----\");\n    if (ntf_tds)  $display(\"---- ERROR: D setup violation! ----\");\n    if (ntf_tws)  $display(\"---- ERROR: GWEN setup violation! ----\");\n    if (ntf_twis) $display(\"---- ERROR: WEN setup violation! ----\");\n\n    if (ntf_tch)  $display(\"---- ERROR: CEN hold violation! ----\");\n    if (ntf_tah)  $display(\"---- ERROR: A hold violation! ----\");\n    if (ntf_tdh)  $display(\"---- ERROR: D hold violation! ----\");\n    if (ntf_twh)  $display(\"---- ERROR: GWEN hold violation! ----\");\n    if (ntf_twih) $display(\"---- ERROR: WEN hold violation! ----\");\n\n    if (ntf_Tcyc) $display(\"---- ERROR: CLK period violation! ----\");\n    if (ntf_Tckh) $display(\"---- ERROR: CLK pulse width high violation! ----\");\n    if (ntf_Tckl) $display(\"---- ERROR: CLK pulse width low violation! ----\");\n  end\nend\n\nalways @(posedge cen_fell) begin\t//reset fasle notifiers\n  ntf_tcs  = 0;\t\t\t\t//after CEN reset (CEN from 1 to 0)\n  ntf_tas  = 0;\n  ntf_tds  = 0;\n  ntf_tws  = 0;\n  ntf_twis = 0;\n\n  ntf_tch  = 0;\n  ntf_tah  = 0;\n  ntf_tdh  = 0;\n  ntf_twh  = 0;\n  ntf_twih = 0;\nend\n\nalways @(negedge clk_dly) begin\t//reset setup/hold notifiers\n  #100;\n  ntf_tcs  = 0;\n  ntf_tas  = 0;\n  ntf_tds  = 0;\n  ntf_tws  = 0;\n  ntf_twis = 0;\n\n  ntf_tch  = 0;\n  ntf_tah  = 0;\n  ntf_tdh  = 0;\n  ntf_twh  = 0;\n  ntf_twih = 0;\nend\n\ninitial begin\t\t\t//initialization\n  ntf_Tcyc  = 0;\n  ntf_Tckh  = 0;\n  ntf_Tckl  = 0;\n\n  ntf_tcs  = 0;\n  ntf_tas  = 0;\n  ntf_tds  = 0;\n  ntf_tws  = 0;\n  ntf_twis = 0;\n\n  ntf_tch  = 0;\n  ntf_tah  = 0;\n  ntf_tdh  = 0;\n  ntf_twh  = 0;\n  ntf_twih = 0;\n\n  marked_a = 9'd0;\n\n  qo_reg         = 8'd0;\n  clk_dly        = 0;\n  write_flag_dly = 0;\n  read_flag_dly  = 0;\n  cen_dly        = 0;\n  cen_fell       = 0;\n  cen_not_rst    = 0;\n\n  for(i=0; i<512; i=i+1) begin\n    mem[i] = 8'd0;\n  end\nend\n\nendmodule\n"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|FlexDPU>FDPE_0_o_adder_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|FlexDPU>FDPE_0_o_adder_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|FlexDPU>FDPE_0_o_adder_2"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|flexdpecom4>counter"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|flexdpecom4>matrix_0_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|flexdpecom4>matrix_0_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|flexdpecom4>matrix_1_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|flexdpecom4>matrix_1_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>rowlength"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>valid"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>i"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>j"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>rowcount_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>rowcount_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>valid1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>matlength"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>count_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>count_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>mat_0_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>mat_0_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>mat_1_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|ivncontrol4>mat_1_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|flexdpecom4>io_i_data_valid"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|FlexDPU>check2"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|SourceDestination>counter2"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|SourceDestination>matricesAreEqual"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>counter"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>j"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>i"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>dest_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>dest_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>dest_2"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>dest_3"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>src_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>src_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>src_2"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>src_3"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>mux_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>mux_1"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>mux_2"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>mux_3"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Muxes>matricesAreEqual"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Regor>j"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Regor>i"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Regor>reg_0"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~AcceleratoTop|Regor>reg_1"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~AcceleratoTop|AcceleratoTop>io_wbs_dat_o",
    "sources":[
      "~AcceleratoTop|AcceleratoTop>io_wbs_we_i",
      "~AcceleratoTop|AcceleratoTop>io_wbs_adr_i"
    ]
  }
]