Re-applying simple fixes

Contains rust-embedded#422, rust-embedded#439, rust-embedded#493, rust-embedded#519, rust-embedded#539, rust-embedded#545, rust-embedded#546, rust-embedded#561, rust-embedded#563, rust-embedded#587 and rust-embedded#597

Author: mbrossard

cortex-m/Cargo.toml

@@ -13,19 +13,19 @@ readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-m"
 version = "0.7.7"
 edition = "2018"
-links = "cortex-m"  # prevent multiple versions of this crate to be linked together
+links = "cortex-m" # prevent multiple versions of this crate to be linked together
 rust-version = "1.61"
 
 [dependencies]
 bare-metal = { version = "0.2.4", features = ["const-fn"] }
 critical-section = { version = "1.0.0", optional = true }
-volatile-register = "0.2.0"
+volatile-register = "0.2.2"
 bitfield = "0.13.2"
 embedded-hal = "0.2.4"
 
 [dependencies.serde]
 version = "1"
-features = [ "derive" ]
+features = ["derive"]
 optional = true
 
 [dependencies.serde_json]
@@ -48,5 +48,5 @@ targets = [
     "thumbv7em-none-eabihf",
     "thumbv7m-none-eabi",
     "thumbv8m.base-none-eabi",
-    "thumbv8m.main-none-eabi"
+    "thumbv8m.main-none-eabi",
 ]

cortex-m/asm/inline.rs

@@ -60,6 +60,10 @@ pub unsafe fn __delay(cyc: u32) {
     // Add 1 to prevent an integer underflow which would cause a long freeze
     let real_cyc = 1 + cyc / 2;
     asm!(
+        // The `bne` on some cores (eg Cortex-M4) will take a different number of instructions
+        // depending on the alignment of the branch target.  Set the alignment of the top of the
+        // loop to prevent surprising timing changes when the alignment of the delay() changes.
+        ".p2align 3",
         // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m.
         "1:",
         "subs {}, #1",

cortex-m/src/asm.rs

@@ -17,13 +17,18 @@ pub fn bkpt() {
 
 /// Blocks the program for *at least* `cycles` CPU cycles.
 ///
-/// This is implemented in assembly so its execution time is independent of the optimization
-/// level, however it is dependent on the specific architecture and core configuration.
-///
-/// NOTE that the delay can take much longer if interrupts are serviced during its execution
-/// and the execution time may vary with other factors. This delay is mainly useful for simple
-/// timer-less initialization of peripherals if and only if accurate timing is not essential. In
-/// any other case please use a more accurate method to produce a delay.
+/// This is implemented in assembly as a fixed number of iterations of a loop, so that execution
+/// time is independent of the optimization level.
+///
+/// The loop code is the same for all architectures, however the number of CPU cycles required for
+/// one iteration varies substantially between architectures.  This means that with a 48MHz CPU
+/// clock, a call to `delay(48_000_000)` is guaranteed to take at least 1 second, but for example
+/// could take 2 seconds.
+///
+/// NOTE that the delay can take much longer if interrupts are serviced during its execution and the
+/// execution time may vary with other factors. This delay is mainly useful for simple timer-less
+/// initialization of peripherals if and only if accurate timing is not essential. In any other case
+/// please use a more accurate method to produce a delay.
 #[inline]
 pub fn delay(cycles: u32) {
     call_asm!(__delay(cycles: u32));

cortex-m/src/cmse.rs

@@ -174,9 +174,9 @@ impl TestTarget {
     ///   * the TT instruction was executed from an unprivileged mode and the A flag was not specified.
     #[inline]
     pub fn mpu_region(self) -> Option<u8> {
-        if self.tt_resp.srvalid() {
-            // Cast is safe as SREGION field is defined on 8 bits.
-            Some(self.tt_resp.sregion() as u8)
+        if self.tt_resp.mrvalid() {
+            // Cast is safe as MREGION field is defined on 8 bits.
+            Some(self.tt_resp.mregion() as u8)
         } else {
             None
         }

cortex-m/src/lib.rs

@@ -31,7 +31,7 @@
 //! implementation suitable for single-core targets, based on disabling interrupts globally.
 //!
 //! It is **unsound** to enable it on multi-core targets or for code running in unprivileged mode,
-//! and may cause functional problems in systems where some interrupts must be not be disabled
+//! and may cause functional problems in systems where some interrupts must not be disabled
 //! or critical sections are managed as part of an RTOS. In these cases, you should use
 //! a target-specific implementation instead, typically provided by a HAL or RTOS crate.
 //!

cortex-m/src/macros.rs

@@ -33,8 +33,8 @@ macro_rules! iprintln {
 /// # Notes
 /// This macro is unsound on multi core systems.
 ///
-/// For debuggability, you can set an explicit name for a singleton.  This name only shows up the
-/// the debugger and is not referencable from other code.  See example below.
+/// For debuggability, you can set an explicit name for a singleton. This name only shows up the
+/// debugger and is not referenceable from other code. See example below.
 ///
 /// # Example
 ///

cortex-m/src/peripheral/nvic.rs

@@ -36,7 +36,15 @@ pub struct RegisterBlock {
     #[cfg(armv6m)]
     _reserved4: [u32; 16],
 
-    _reserved5: [u32; 48],
+    _reserved5: [u32; 16],
+
+    #[cfg(armv8m)]
+    /// Interrupt Target Non-secure (only present on Arm v8-M)
+    pub itns: [RW<u32>; 16],
+    #[cfg(not(armv8m))]
+    _reserved6: [u32; 16],
+
+    _reserved7: [u32; 16],
 
     /// Interrupt Priority
     ///
@@ -67,7 +75,7 @@ pub struct RegisterBlock {
     pub ipr: [RW<u32>; 8],
 
     #[cfg(not(armv6m))]
-    _reserved6: [u32; 580],
+    _reserved8: [u32; 580],
 
     /// Software Trigger Interrupt
     #[cfg(not(armv6m))]

cortex-m/src/peripheral/scb.rs

@@ -820,6 +820,26 @@ impl SCB {
     }
 }
 
+const SCB_SCR_SEVONPEND: u32 = 0x1 << 4;
+
+impl SCB {
+    /// Set the SEVONPEND bit in the SCR register
+    #[inline]
+    pub fn set_sevonpend(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr | SCB_SCR_SEVONPEND);
+        }
+    }
+
+    /// Clear the SEVONPEND bit in the SCR register
+    #[inline]
+    pub fn clear_sevonpend(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr & !SCB_SCR_SEVONPEND);
+        }
+    }
+}
+
 const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16;
 const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x7 << 8;
 const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2;

cortex-m/src/peripheral/syst.rs

@@ -1,4 +1,18 @@
 //! SysTick: System Timer
+//!
+//! # Example
+//!
+//! ```no_run
+//! use cortex_m::peripheral::{Peripherals, SYST};
+//!
+//! let core_periph = cortex_m::peripheral::Peripherals::take().unwrap();
+//! let mut syst = core_periph.SYST;
+//! syst.set_reload(0xffffff);
+//! syst.clear_current();
+//! syst.enable_counter();
+//!
+//! let syst_value: u32 = SYST::get_current();
+//! ```
 
 use volatile_register::{RO, RW};
 
@@ -39,7 +53,7 @@ const SYST_CALIB_NOREF: u32 = 1 << 31;
 impl SYST {
     /// Clears current value to 0
     ///
-    /// After calling `clear_current()`, the next call to `has_wrapped()` will return `false`.
+    /// After calling `clear_current()`, the next call to `has_wrapped()`, unless called after the reload time (if the counter is enabled), will return `false`.
     #[inline]
     pub fn clear_current(&mut self) {
         unsafe { self.cvr.write(0) }