|
| 1 | + |
| 2 | +/dts-v1/; |
| 3 | + |
| 4 | +/ { |
| 5 | + #address-cells = <1>; |
| 6 | + #size-cells = <1>; |
| 7 | + |
| 8 | + |
| 9 | + chosen { |
| 10 | + bootargs = "console=liteuart earlycon=liteuart,0xf0001000 rootwait root=/dev/mmcblk0p2 fbcon=logo-pos:0"; |
| 11 | + }; |
| 12 | + |
| 13 | + sys_clk: pll { |
| 14 | + compatible = "fixed-clock"; |
| 15 | + #clock-cells = <0>; |
| 16 | + clock-frequency = <48000000>; |
| 17 | + }; |
| 18 | + |
| 19 | + cpus { |
| 20 | + #address-cells = <1>; |
| 21 | + #size-cells = <0>; |
| 22 | + timebase-frequency = <48000000>; |
| 23 | + |
| 24 | + CPU0: cpu@0 { |
| 25 | + device_type = "cpu"; |
| 26 | + compatible = "riscv"; |
| 27 | + riscv,isa = "rv32i2p0_ma"; |
| 28 | + riscv,isa-base = "rv32i"; |
| 29 | + riscv,isa-extensions = "i", "m", "a"; |
| 30 | + mmu-type = "riscv,sv32"; |
| 31 | + reg = <0>; |
| 32 | + clock-frequency = <48000000>; |
| 33 | + status = "okay"; |
| 34 | + |
| 35 | + d-cache-size = <64>; |
| 36 | + d-cache-sets = <1>; |
| 37 | + d-cache-block-size = <64>; |
| 38 | + |
| 39 | + i-cache-size = <64>; |
| 40 | + i-cache-sets = <1>; |
| 41 | + i-cache-block-size = <64>; |
| 42 | + |
| 43 | + |
| 44 | + d-tlb-size = <4>; |
| 45 | + d-tlb-sets = <4>; |
| 46 | + |
| 47 | + i-tlb-size = <4>; |
| 48 | + i-tlb-sets = <4>; |
| 49 | + |
| 50 | + |
| 51 | + L0: interrupt-controller { |
| 52 | + #address-cells = <0>; |
| 53 | + #interrupt-cells = <0x00000001>; |
| 54 | + interrupt-controller; |
| 55 | + compatible = "riscv,cpu-intc"; |
| 56 | + }; |
| 57 | + }; |
| 58 | + |
| 59 | + |
| 60 | + }; |
| 61 | + |
| 62 | + memory: memory@40000000 { |
| 63 | + device_type = "memory"; |
| 64 | + reg = <0x40000000 0x2000000>; |
| 65 | + }; |
| 66 | + |
| 67 | + reserved-memory { |
| 68 | + #address-cells = <1>; |
| 69 | + #size-cells = <1>; |
| 70 | + ranges; |
| 71 | + |
| 72 | + opensbi@40f00000 { |
| 73 | + reg = <0x40f00000 0x80000>; |
| 74 | + }; |
| 75 | + |
| 76 | + framebuffer@40c00000 { |
| 77 | + reg = <0x40c00000 0x96000>; |
| 78 | + }; |
| 79 | + |
| 80 | + }; |
| 81 | + |
| 82 | + soc { |
| 83 | + #address-cells = <1>; |
| 84 | + #size-cells = <1>; |
| 85 | + compatible = "simple-bus"; |
| 86 | + interrupt-parent = <&intc0>; |
| 87 | + ranges; |
| 88 | + |
| 89 | + soc_ctrl0: soc_controller@f0000000 { |
| 90 | + compatible = "litex,soc-controller"; |
| 91 | + reg = <0xf0000000 0xc>; |
| 92 | + status = "okay"; |
| 93 | + }; |
| 94 | + |
| 95 | + intc0: interrupt-controller@f0c00000 { |
| 96 | + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; |
| 97 | + reg = <0xf0c00000 0x400000>; |
| 98 | + #address-cells = <0>; |
| 99 | + #interrupt-cells = <1>; |
| 100 | + interrupt-controller; |
| 101 | + interrupts-extended = < |
| 102 | + &L0 11 &L0 9>; |
| 103 | + riscv,ndev = <32>; |
| 104 | + |
| 105 | + }; |
| 106 | + |
| 107 | + liteuart0: serial@f0001000 { |
| 108 | + compatible = "litex,liteuart"; |
| 109 | + reg = <0xf0001000 0x100>; |
| 110 | + interrupts = <1>; |
| 111 | + status = "okay"; |
| 112 | + }; |
| 113 | + |
| 114 | + usb0: mac@c0000000 { |
| 115 | + compatible = "generic-ohci"; |
| 116 | + reg = <0xc0000000 0x1000>; |
| 117 | + interrupts = <16>; |
| 118 | + status = "okay"; |
| 119 | + }; |
| 120 | + |
| 121 | + litespisdcard0: spi@f0002800 { |
| 122 | + compatible = "litex,litespi"; |
| 123 | + reg = <0xf0002800 0x100>; |
| 124 | + status = "okay"; |
| 125 | + |
| 126 | + litespi,max-bpw = <8>; |
| 127 | + litespi,sck-frequency = <1500000>; |
| 128 | + litespi,num-cs = <1>; |
| 129 | + |
| 130 | + #address-cells = <1>; |
| 131 | + #size-cells = <0>; |
| 132 | + |
| 133 | + mmc-slot@0 { |
| 134 | + compatible = "mmc-spi-slot"; |
| 135 | + reg = <0>; |
| 136 | + voltage-ranges = <3300 3300>; |
| 137 | + spi-max-frequency = <1500000>; |
| 138 | + status = "okay"; |
| 139 | + }; |
| 140 | + }; |
| 141 | + |
| 142 | + framebuffer0: framebuffer@40c00000 { |
| 143 | + compatible = "simple-framebuffer"; |
| 144 | + reg = <0x40c00000 0x96000>; |
| 145 | + width = <640>; |
| 146 | + height = <480>; |
| 147 | + stride = <1280>; |
| 148 | + format = "r5g6b5"; |
| 149 | + }; |
| 150 | + |
| 151 | + }; |
| 152 | + |
| 153 | + aliases { |
| 154 | + |
| 155 | + serial0 = &liteuart0; |
| 156 | + |
| 157 | + sdcard0 = &litespisdcard0; |
| 158 | + |
| 159 | + }; |
| 160 | + |
| 161 | +}; |
0 commit comments