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Issues list

redesign platform resource feature improvement
#82 opened Oct 28, 2017 by jordens updated Oct 30, 2017
3
document constraints API improvement
#76 opened Aug 23, 2017 by jordens updated Nov 9, 2017
document platform, toolchain API and build process hooks improvement
#77 opened Aug 23, 2017 by jordens updated Nov 9, 2017
mark proper CDCs as such, use to flag CDC errors and to emit timing exceptions automatically feature improvement
#103 opened Mar 7, 2018 by jordens updated Mar 7, 2018
make post-synthesis results compatible with Vivado GUI feature
#99 opened Jan 18, 2018 by sbourdeauducq updated May 13, 2018
1
tutorial out of date (was: Issue with importing Signal) bug
#80 opened Oct 10, 2017 by sheeets updated May 13, 2018
3
consider removing the depth parameter of ElasticBuffer question
#63 opened Jan 13, 2017 by sbourdeauducq updated May 13, 2018
@enjoy-digital
1
Missing documentation for migen.genlib modules improvement
#23 opened Jul 2, 2015 by mithro updated May 13, 2018
1 of 12 tasks
1
migen travis config should push development versions to PyPi improvement
#17 opened Apr 20, 2015 by mithro updated Jun 10, 2018
@fallen
1
review vivado cdc analysis (report_cdc) improvement
#117 opened Jun 26, 2018 by jordens updated Nov 10, 2018
Fix # TODO: instances via Iverilog/VPI feature
#125 opened Aug 28, 2018 by dvc94ch updated Nov 10, 2018
export as hierarchy (verilog modules) feature fixed-in-nmigen
#70 opened Jun 19, 2017 by jordens updated Jul 5, 2019
6
construct and use sensitivity graph to speed up sim and find comb loops fixed-in-nmigen improvement
#69 opened Jun 9, 2017 by jordens updated Jul 5, 2019
2
Cat(..)[slice] on LHS needs a proxy bug fixed-in-nmigen
#20 opened Jun 12, 2015 by cr1901 updated Jul 5, 2019
4
Records with 0 fields generate invalid verilog bug fixed-in-nmigen
#41 opened Mar 17, 2016 by nakengelhardt updated Jul 5, 2019
4
FullMemoryWE and SplitMemory break direct access to memory in simulation fixed-in-nmigen improvement
#53 opened Nov 15, 2016 by jordens updated Jul 5, 2019
1
AsyncFIFO reset fixed-in-nmigen improvement
#73 opened Jul 2, 2017 by jordens updated Jul 5, 2019
2
Should Migen generate explicit Verilog for mismatched bit vector lengths (rather then relying on implicit Verilog behaviour?) fixed-in-nmigen question
#102 opened Feb 14, 2018 by mithro updated Jul 5, 2019
23
chained comparisons are not implemented correctly bug fixed-in-nmigen
#108 opened May 13, 2018 by whitequark updated Jul 5, 2019
1
Empty FSM states do not produce expected behavior bug fixed-in-nmigen
#112 opened May 28, 2018 by whitequark updated Jul 5, 2019
1
review expression size and signedness fixed-in-nmigen improvement
#115 opened Jun 10, 2018 by jordens updated Jul 5, 2019
1
Migen outputs incorrect verilog in specific use-case bug fixed-in-nmigen
#119 opened Jul 4, 2018 by rohitk-singh updated Jul 5, 2019
6
Migen Namer __main__ Decoration fixed-in-nmigen improvement
#29 opened Aug 25, 2015 by cr1901 updated Jul 5, 2019
4
Negative initialization produces incorrect verilog bug fixed-in-nmigen
#142 opened Oct 9, 2018 by JohnSully updated Jul 5, 2019
8
Finalization is order-dependent, leading to footguns bug fixed-in-nmigen
#158 opened Nov 10, 2018 by whitequark updated Jul 5, 2019
1
ProTip! Updated in the last three days: updated:>2025-03-26.