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use eqLoc to replace reify
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src/Control/CSD/CSD.hs

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Original file line numberDiff line numberDiff line change
@@ -230,29 +230,29 @@ project1Distrib Out _ = \acbc -> return (either (\(a, c) -> (Left a, c)) (\(b, c
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project1 :: (forall x y. f x y -> x -> IO y) -> CSD f a b -> ProjectedF a b
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project1 hdl (Perf @l act) (_ :: Proxy t)
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| reify @l == reify @t = \x -> async (wait x >>= hdl act)
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| eqLoc @l @t = \x -> async (wait x >>= hdl act)
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| otherwise = \_ -> return absent
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project1 _ (Comm @s @r) (_ :: Proxy t)
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| reify @s == reify @r = return
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| reify @t == reify @s = \x -> do
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| eqLoc @s @r = return
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| eqLoc @t @s = \x -> do
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i <- inc
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lift $ send (reify @r) i x -- there's dangling Async there
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return absent
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| reify @t == reify @r = \_ -> do
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| eqLoc @t @r = \_ -> do
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i <- inc; lift $ recv i
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| otherwise = \_ -> inc >> return absent
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project1 hdl (Seq f g) t = \a -> project1 hdl f t a >>= project1 hdl g t
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project1 hdl (Par f g) t = \(a, b) -> (,) <$> project1 hdl f t a <*> project1 hdl g t b
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project1 _ (Fork @l) (_ :: Proxy t)
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| reify @l == reify @t = \xy -> (,) <$> async (fst <$> wait xy) <*> async (snd <$> wait xy)
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| eqLoc @l @t = \xy -> (,) <$> async (fst <$> wait xy) <*> async (snd <$> wait xy)
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| otherwise = \_ -> return (absent, absent)
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project1 _ (Join @l) (_ :: Proxy t)
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| reify @l == reify @t = \(x, y) -> async ((,) <$> wait x <*> wait y)
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| eqLoc @l @t = \(x, y) -> async ((,) <$> wait x <*> wait y)
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| otherwise = \_ -> return absent
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project1 _ (Perm p) t = project1Perm p t
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-- conditionals
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project1 _ (Split @s) (_ :: Proxy t)
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| reify @t == reify @s = \xy -> do
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| eqLoc @s @t = \xy -> do
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xy' <- wait xy
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i <- inc
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case xy' of
@@ -270,7 +270,7 @@ project1 _ (Split @s) (_ :: Proxy t)
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then return (Left absent)
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else return (Right absent)
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project1 _ (Merge @l) (_ :: Proxy t)
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| reify @t == reify @l = \case
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| eqLoc @l @t = \case
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(Left a) -> return (Left <$> a)
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(Right b) -> return (Right <$> b)
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| otherwise = \_ -> return absent

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