[sw/device] Fix strict prototype violations

I generated the changes in this commit by running this command:

    ./bazelisk.sh build -k \
        --config=riscv32 --config=clang_tidy //sw/device/...

Author: dmcardle

sw/device/examples/sram_program/sram_program.c

@@ -24,7 +24,7 @@ enum {
              TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES,
 };
 
-void sram_main() {
+void sram_main(void) {
   if (kDeviceType != kDeviceSimDV) {
     // Configure the pinmux.
     CHECK_DIF_OK(dif_pinmux_init(
@@ -62,4 +62,4 @@ void sram_main() {
 // Reference functions that the debugger may wish to call. This prevents the
 // compiler from dropping them as unused functions and has the side benefit of
 // preventing their includes from appearing unused.
-void debugger_support_functions() { (void)icache_invalidate; }
+void debugger_support_functions(void) { (void)icache_invalidate; }

sw/device/lib/testing/alert_handler_testutils.c

@@ -152,6 +152,6 @@ status_t alert_handler_testutils_get_cycles_from_us(uint64_t microseconds,
   return OK_STATUS();
 }
 
-uint32_t alert_handler_testutils_cycle_rescaling_factor() {
+uint32_t alert_handler_testutils_cycle_rescaling_factor(void) {
   return kDeviceType == kDeviceSimDV ? 1 : 10;
 }

sw/device/lib/testing/clkmgr_testutils.c

@@ -50,7 +50,7 @@ static uint32_t cast_safely(uint64_t val) {
   return (uint32_t)val;
 }
 
-void initialize_expected_counts() {
+void initialize_expected_counts(void) {
   // The expected counts depend on the device, per sw/device/lib/arch/device.h.
   // Notice the ratios are small enough to fit a uint32_t, even if the Hz number
   // is in uint64_t.

sw/device/lib/testing/profile.c

@@ -7,7 +7,7 @@
 #include "sw/device/lib/runtime/ibex.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 
-uint64_t profile_start() { return ibex_mcycle_read(); }
+uint64_t profile_start(void) { return ibex_mcycle_read(); }
 
 uint32_t profile_end(uint64_t t_start) {
   uint64_t t_end = ibex_mcycle_read();

sw/device/lib/testing/rstmgr_testutils.c

@@ -96,10 +96,10 @@ status_t rstmgr_testutils_post_reset(
   return OK_STATUS();
 }
 
-dif_rstmgr_reset_info_bitfield_t rstmgr_testutils_reason_get() {
+dif_rstmgr_reset_info_bitfield_t rstmgr_testutils_reason_get(void) {
   return retention_sram_get()->reset_reasons;
 }
 
-void rstmgr_testutils_reason_clear() {
+void rstmgr_testutils_reason_clear(void) {
   retention_sram_get()->reset_reasons = 0;
 }

sw/device/lib/testing/test_framework/ottf_console.c

@@ -51,7 +51,7 @@ static dif_uart_t ottf_console_uart;
 static volatile ottf_console_flow_control_t flow_control_state;
 static volatile uint32_t flow_control_irqs;
 
-void *ottf_console_get() {
+void *ottf_console_get(void) {
   switch (kOttfTestConfig.console.type) {
     case kOttfConsoleSpiDevice:
       return &ottf_console_spi_device;
@@ -123,7 +123,7 @@ void ottf_console_init(void) {
   }
 }
 
-static uint32_t get_flow_control_watermark_plic_id() {
+static uint32_t get_flow_control_watermark_plic_id(void) {
   switch (kOttfTestConfig.console.base_addr) {
 #if !OT_IS_ENGLISH_BREAKFAST
     case TOP_EARLGREY_UART1_BASE_ADDR:

sw/device/sca/ecc256_sign_serial.c

@@ -231,7 +231,7 @@ static void p256_ecdsa_sign(const uint32_t *msg, const uint32_t *private_key_d,
  * Triggers OTBN_P256_sign operation.
  *
  */
-static void ecc256_ecdsa() {
+static void ecc256_ecdsa(void) {
   LOG_INFO("SSECDSA starting...");
   SS_CHECK_STATUS_OK(otbn_load_app(kOtbnAppP256Ecdsa));
   LOG_INFO("otbn_status: 0x%08x", abs_mmio_read32(TOP_EARLGREY_OTBN_BASE_ADDR +

sw/device/sca/ecc384_serial.c

@@ -152,7 +152,7 @@ static void setup_data_pointer(const otbn_addr_t dptr,
  * This function makes the data pointers refer to the pre-allocated DMEM
  * regions to store the actual values.
  */
-static void setup_data_pointers() {
+static void setup_data_pointers(void) {
   setup_data_pointer(kOtbnVarDptrMsg, kOtbnVarMsg);
   setup_data_pointer(kOtbnVarDptrR, kOtbnVarR);
   setup_data_pointer(kOtbnVarDptrS, kOtbnVarS);

sw/device/silicon_creator/lib/sigverify/sphincsplus/test/fors_test.c

@@ -50,7 +50,7 @@ static rom_error_t pk_from_sig_test(void) {
   return kErrorOk;
 }
 
-bool test_main() {
+bool test_main(void) {
   status_t result = OK_STATUS();
   LOG_INFO("Starting FORS test...");
 

sw/device/silicon_creator/lib/sigverify/sphincsplus/test/verify_test.c

@@ -97,7 +97,7 @@ static rom_error_t spx_verify_negative_test(void) {
   return kErrorOk;
 }
 
-bool test_main() {
+bool test_main(void) {
   status_t result = OK_STATUS();
 
   CHECK(kNumNegativeTests <= kSpxVerifyNumTests,

sw/device/silicon_creator/lib/sigverify/sphincsplus/test/wots_test.c

@@ -64,7 +64,7 @@ static const uint32_t kExpectedPk[kSpxWotsPkWords] = {
     0x460bec28, 0x3724f477, 0x46f9003f, 0x6357d6ec, 0x7a39121d, 0x511b498f,
     0x2bca40d1, 0x24b829a1};
 
-static rom_error_t pk_from_sig_test() {
+static rom_error_t pk_from_sig_test(void) {
   // Initialize the KMAC block.
   RETURN_IF_ERROR(spx_hash_initialize(&kTestCtx));
 
@@ -79,7 +79,7 @@ static rom_error_t pk_from_sig_test() {
   return kErrorOk;
 }
 
-bool test_main() {
+bool test_main(void) {
   status_t result = OK_STATUS();
   LOG_INFO("Starting WOTS test...");
 

sw/device/silicon_creator/manuf/lib/sram_exec_test.c

@@ -27,7 +27,7 @@ static_assert(ARRAYSIZE(kTestDeviceID) % sizeof(uint32_t) == 0,
 static_assert(ARRAYSIZE(kTestDeviceID) <= 32,
               "kTestDeviceID must be less than 32 bytes");
 
-static status_t log_device_id() {
+static status_t log_device_id(void) {
   // Read the Device_ID from OTP (except all zeroes).
   uint32_t otp_device_id;
   for (int i = 0; i < kNumDeviceId; i++) {
@@ -39,7 +39,7 @@ static status_t log_device_id() {
   return OK_STATUS();
 }
 
-status_t write_otp() {
+status_t write_otp(void) {
   // Configure the pinmux.
   TRY(dif_pinmux_init(mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR),
                       &pinmux));
@@ -86,7 +86,7 @@ status_t write_otp() {
   return OK_STATUS();
 }
 
-void sram_main() {
+void sram_main(void) {
   status_t res = write_otp();
   LOG_INFO("result: %x", res);
   test_status_set(kTestStatusPassed);

sw/device/silicon_creator/rom/e2e/rom_e2e_c_init_test.c

@@ -77,7 +77,7 @@ static void fault(void) {
  * and then reading back, because the pad attribute registers have
  * write-any-read-legal behavior.
  */
-static uint32_t pad_attr_mask_get() {
+static uint32_t pad_attr_mask_get(void) {
   CHECK_EQ(kDeviceType, kDeviceFpgaCw310,
            "This test is only supported for CW310");
 

sw/device/tests/alert_handler_lpg_clkoff_test.c

@@ -382,7 +382,7 @@ void set_peripheral_clock(const test_t *peripheral,
  * A utility function to wait enough until the alert handler pings a peripheral
  * alert
  */
-void wait_enough_for_alert_ping() {
+void wait_enough_for_alert_ping(void) {
   // wait enough
   if (kDeviceType == kDeviceFpgaCw310) {
     // NUM_ALERTS*2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)

sw/device/tests/alert_handler_lpg_reset_toggle.c

@@ -293,7 +293,7 @@ static void alert_handler_config_peripherals(uint32_t num_peripherals,
  * A utility function to wait enough until the alert handler pings a peripheral
  * alert
  */
-void wait_enough_for_alert_ping() {
+void wait_enough_for_alert_ping(void) {
   // wait enough
   if (kDeviceType == kDeviceFpgaCw310) {
     // NUM_ALERTS*2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)

sw/device/tests/alert_handler_lpg_sleep_mode_alerts.c

@@ -266,7 +266,7 @@ static size_t test_step_cnt;
  * Helper function to keep the test body clean
  * Initializes the flash_ctrl and test counters.
  */
-void init_test_components() {
+void init_test_components(void) {
   // Enable global and external IRQ at Ibex.
   irq_global_ctrl(true);
   irq_external_ctrl(true);

sw/device/tests/alert_handler_lpg_sleep_mode_pings.c

@@ -79,7 +79,7 @@ static void init_peripherals(void) {
  * A utility function to wait enough until the alert handler pings a peripheral
  * alert
  */
-void wait_enough_for_alert_ping() {
+void wait_enough_for_alert_ping(void) {
   // wait enough
   if (kDeviceType == kDeviceFpgaCw310) {
     // 2*margin_of_safety*(2**DW)*(1/kClockFreqPeripheralHz)
@@ -295,7 +295,7 @@ static size_t test_step_cnt;
  * Helper function to keep the test body clean
  * Initializes the flash_ctrl and test counters.
  */
-void init_test_components() {
+void init_test_components(void) {
   // Enable global and external IRQ at Ibex.
   irq_global_ctrl(true);
   irq_external_ctrl(true);

sw/device/tests/clkmgr_off_kmac_trans_test.c

@@ -8,6 +8,6 @@
 
 #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
-bool test_main() {
+bool test_main(void) {
   return execute_off_trans_test(kTopEarlgreyHintableClocksMainKmac);
 }

sw/device/tests/clkmgr_off_peri_test.c

@@ -37,7 +37,7 @@
 OTTF_DEFINE_TEST_CONFIG();
 
 typedef struct peri_context {
-  void (*csr_access)();  // The function causing a timeout.
+  void (*csr_access)(void);  // The function causing a timeout.
   uint32_t address;      // The address causing a timeout.
 } peri_context_t;
 
@@ -62,7 +62,7 @@ static void set_hung_address(dif_clkmgr_gateable_clock_t clock,
            value, addr);
 }
 
-static void uart0_csr_access() {
+static void uart0_csr_access(void) {
   dif_toggle_t state;
   CHECK_DIF_OK(dif_uart_irq_set_enabled(&uart0, kDifUartIrqTxWatermark,
                                         kDifToggleEnabled));
@@ -71,7 +71,7 @@ static void uart0_csr_access() {
   CHECK(state == kDifToggleEnabled);
 }
 
-static void spi_host0_csr_access() {
+static void spi_host0_csr_access(void) {
   dif_toggle_t state;
   CHECK_DIF_OK(dif_spi_host_irq_set_enabled(&spi_host0, kDifSpiHostIrqSpiEvent,
                                             kDifToggleEnabled));
@@ -80,7 +80,7 @@ static void spi_host0_csr_access() {
   CHECK(state == kDifToggleEnabled);
 }
 
-static void spi_host1_csr_access() {
+static void spi_host1_csr_access(void) {
   dif_toggle_t state;
   CHECK_DIF_OK(dif_spi_host_irq_set_enabled(&spi_host1, kDifSpiHostIrqSpiEvent,
                                             kDifToggleEnabled));
@@ -89,7 +89,7 @@ static void spi_host1_csr_access() {
   CHECK(state == kDifToggleEnabled);
 }
 
-static void usbdev_csr_access() {
+static void usbdev_csr_access(void) {
   CHECK_DIF_OK(dif_usbdev_irq_set_enabled(&usbdev, kDifUsbdevIrqPowered,
                                           kDifToggleEnabled));
   dif_toggle_t state;

sw/device/tests/entropy_src_ast_rng_req_test.c

@@ -28,7 +28,7 @@ static uint32_t read_fifo_depth(dif_entropy_src_t *entropy) {
   return fifo_depth;
 }
 
-bool test_main() {
+bool test_main(void) {
   dif_entropy_src_t entropy_src;
   CHECK_DIF_OK(dif_entropy_src_init(
       mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR), &entropy_src));

sw/device/tests/entropy_src_edn_reqs_test.c

@@ -242,7 +242,7 @@ status_t execute_test(void) {
  * TODO: Run the test entropy src end reqs in continuous mode
  * (https://github.com/lowRISC/opentitan/issues/13393)
  */
-bool test_main() {
+bool test_main(void) {
   test_initialize();
 
   alert_handler_configure(&alert_handler);

sw/device/tests/hmac_enc_idle_test.c

@@ -67,7 +67,7 @@ static status_t handle_end_of_process(dif_clkmgr_hintable_clock_t clock) {
   return OK_STATUS();
 }
 
-static status_t execute_test() {
+static status_t execute_test(void) {
   // With the HMAC unit idle, write the HMAC clk hint to 0 within clkmgr to
   // indicate HMAC clk can be gated and verify that the HMAC clk hint status
   // within clkmgr reads 0 (HMAC is disabled).

sw/device/tests/otbn_randomness_test.c

@@ -131,7 +131,7 @@ status_t initialize_clkmgr(void) {
                                            kDifToggleEnabled);
 }
 
-status_t execute_test() {
+status_t execute_test(void) {
   // Write the OTBN clk hint to 0 within clkmgr to indicate OTBN clk can be
   // gated and verify that the OTBN clk hint status within clkmgr reads 0 (OTBN
   // is idle).

sw/device/tests/rstmgr_alert_info_test.c

@@ -666,7 +666,7 @@ static node_t test_node[kTopEarlgreyAlertPeripheralLast] = {
         },
 };
 
-static void init_expected_cause() {
+static void init_expected_cause(void) {
   kExpectedInfo[kRound1]
       .alert_info.alert_cause[kTopEarlgreyAlertIdI2c0FatalFault] = 1;
   kExpectedInfo[kRound1]

sw/device/tests/rv_core_ibex_rnd_test.c

@@ -20,8 +20,8 @@
 OTTF_DEFINE_TEST_CONFIG();
 
 // Declare two assembly functions defined in `rv_core_ibex_rnd_test.S`.
-extern uint32_t rv_core_ibex_rnd_read_and_immediately_check_status();
-extern uint32_t rv_core_ibex_check_rnd_read_possible_while_status_invalid();
+extern uint32_t rv_core_ibex_rnd_read_and_immediately_check_status(void);
+extern uint32_t rv_core_ibex_check_rnd_read_possible_while_status_invalid(void);
 
 enum {
   kRandomDataReads = 32,

sw/device/tests/sim_dv/all_escalation_resets_test.c

@@ -1091,7 +1091,7 @@ static void execute_test(const dif_aon_timer_t *aon_timer) {
   CHECK(false, "This should not be reached");
 }
 
-void check_alert_dump() {
+void check_alert_dump(void) {
   dif_rstmgr_alert_info_dump_segment_t dump[DIF_RSTMGR_ALERT_INFO_MAX_SIZE];
   size_t seg_size;
   alert_handler_testutils_info_t actual_info;

sw/device/tests/sim_dv/ast_clk_rst_inputs.c

@@ -165,7 +165,7 @@ static void test_event(uint32_t idx, dif_toggle_t fatal, bool set_event) {
   }
 };
 
-void init_units() {
+void init_units(void) {
   CHECK_DIF_OK(dif_pwrmgr_init(
       mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR), &pwrmgr));
   CHECK_DIF_OK(dif_rstmgr_init(
@@ -410,7 +410,7 @@ void ast_enter_sleep_states_and_check_functionality(
 /**
  *  set edn auto mode
  */
-void set_edn_auto_mode() {
+void set_edn_auto_mode(void) {
   const dif_edn_t edn0 = {
       .base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR)};
   const dif_edn_t edn1 = {
@@ -510,7 +510,7 @@ void ottf_external_isr(void) {
   interrupt_serviced = true;
 }
 
-bool test_main() {
+bool test_main(void) {
   dif_pwrmgr_domain_config_t pwrmgr_config;
 
   const dif_entropy_src_config_t entropy_src_config = {

sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c

@@ -493,7 +493,7 @@ static void alert_handler_config(void) {
       &alert_handler, kDifAlertHandlerIrqClassd, kDifToggleEnabled));
 }
 
-static void set_aon_timers() {
+static void set_aon_timers(void) {
   uint32_t bark_cycles = 0;
   CHECK_STATUS_OK(aon_timer_testutils_get_aon_cycles_from_us(kWdogBarkMicros,
                                                              &bark_cycles));
@@ -518,7 +518,7 @@ static void set_aon_timers() {
  * The aon timers should never trigger actions because escalation should take
  * precedence.
  */
-static void execute_test() {
+static void execute_test(void) {
   alert_handler_config();
 
   // Make sure we can receive both the watchdog and alert NMIs.

sw/device/tests/sim_dv/lc_walkthrough_test.c

@@ -106,7 +106,7 @@ static void lock_otp_secret0_partition(void) {
   CHECK_STATUS_OK(otp_ctrl_testutils_wait_for_dai(&otp));
 }
 
-static void lock_otp_secret2_partition() {
+static void lock_otp_secret2_partition(void) {
   // Write LC RMA tokens to OTP secret2 partition.
   uint64_t otp_rma_token_0 = 0;
   uint64_t otp_rma_token_1 = 0;

sw/device/tests/sim_dv/pwrmgr_b2b_sleep_reset_test.c

@@ -47,7 +47,7 @@ static dif_pinmux_t pinmux;
  * . set sysrst_ctrl.KEY_INTR_CTL.pwrb_in_H2L to 1
  * . use IOR13 as pwrb_in
  */
-static void prgm_push_button_wakeup() {
+static void prgm_push_button_wakeup(void) {
   dif_sysrst_ctrl_input_change_config_t config = {
       .input_changes = kDifSysrstCtrlInputPowerButtonH2L,
       .debounce_time_threshold = 1,  // 5us

sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c

@@ -173,7 +173,7 @@ const test_wakeup_sources_t kTestWakeupSources[PWRMGR_PARAM_NUM_WKUPS] = {
     },
 };
 
-void init_units() {
+void init_units(void) {
   CHECK_DIF_OK(dif_adc_ctrl_init(
       mmio_region_from_addr(TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR), &adc_ctrl));
   CHECK_DIF_OK(dif_aon_timer_init(