From f283b93fb5a0d4f59ad5c4be969eb3d96adea19a Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Tue, 16 Apr 2024 19:10:16 +0000 Subject: [PATCH 1/3] [llvm-exegesis] Add support for alder lake This patch adds the PFM counter definitions for Intel alder lake CPUs. --- llvm/lib/Target/X86/X86PfmCounters.td | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index d87a559aa353b..11846477e64ae 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -204,6 +204,27 @@ def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>; def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>; def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>; +def AlderLakePfmCounters : ProcPfmCounters { + let CycleCounter = UnhaltedCoreCyclesPfmCounter; + let UopsCounter = UopsIssuedPfmCounter; + let IssueCounters = [ + PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">, + PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">, + PfmIssueCounter<"ADLPPort02", "uops_dispatched_port:port_2_3_10">, + PfmIssueCounter<"ADLPPort03", "uops_dispatched_port:port_2_3_10">, + PfmIssueCounter<"ADLPPort04", "uops_dispatched_port:port_4_9">, + PfmIssueCounter<"ADLPPort05", "uops_dispatched_port:port_5_11">, + PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">, + PfmIssueCounter<"ADLPPort07", "uops_dispatched_port:port_7_8">, + PfmIssueCounter<"ADLPPort08", "uops_dispatched_port:port_7_8">, + PfmIssueCounter<"ADLPPort09", "uops_dispatched_port:port_4_9">, + PfmIssueCounter<"ADLPPort10", "uops_dispatched_port:port_2_3_10">, + PfmIssueCounter<"ADLPPort11", "uops_dispatched_port:port_5_11">, + ]; + let ValidationCounters = DefaultIntelPfmValidationCounters; +} +def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>; + // AMD X86 Counters. defvar DefaultAMDPfmValidationCounters = [ PfmValidationCounter, From 829205a893e42ead4d2c3a912bd844feed0f1732 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Sat, 20 Apr 2024 10:22:57 +0000 Subject: [PATCH 2/3] Address reviewer feedback --- llvm/lib/Target/X86/X86PfmCounters.td | 10 +++------- llvm/lib/Target/X86/X86SchedAlderlakeP.td | 6 ++++++ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index 11846477e64ae..c08e3e738e3fe 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -210,15 +210,11 @@ def AlderLakePfmCounters : ProcPfmCounters { let IssueCounters = [ PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">, PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">, - PfmIssueCounter<"ADLPPort02", "uops_dispatched_port:port_2_3_10">, - PfmIssueCounter<"ADLPPort03", "uops_dispatched_port:port_2_3_10">, - PfmIssueCounter<"ADLPPort04", "uops_dispatched_port:port_4_9">, + PfmIssueCounter<"ADLPPort02_03_10", "uops_dispatched_port:port_2_3_10">, + PfmIssueCounter<"ADLPPort04_09", "uops_dispatched_port:port_4_9">, PfmIssueCounter<"ADLPPort05", "uops_dispatched_port:port_5_11">, PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">, - PfmIssueCounter<"ADLPPort07", "uops_dispatched_port:port_7_8">, - PfmIssueCounter<"ADLPPort08", "uops_dispatched_port:port_7_8">, - PfmIssueCounter<"ADLPPort09", "uops_dispatched_port:port_4_9">, - PfmIssueCounter<"ADLPPort10", "uops_dispatched_port:port_2_3_10">, + PfmIssueCounter<"ADLPPort07_08", "uops_dispatched_port:port_7_8">, PfmIssueCounter<"ADLPPort11", "uops_dispatched_port:port_5_11">, ]; let ValidationCounters = DefaultIntelPfmValidationCounters; diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td index 6f9d2cf7ffdf4..7756cd57cf7f8 100644 --- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td +++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td @@ -60,6 +60,8 @@ def ADLPPort01_05_10 : ProcResGroup<[ADLPPort01, ADLPPort05, ADLPPort10]>; def ADLPPort02_03 : ProcResGroup<[ADLPPort02, ADLPPort03]>; def ADLPPort02_03_07 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07]>; def ADLPPort02_03_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort11]>; +def ADLPPort02_03_10 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort10]>; +def ADLPPort05_11 : ProcResGroup<[ADLPPort05, ADLPPort11]>; def ADLPPort07_08 : ProcResGroup<[ADLPPort07, ADLPPort08]>; // EU has 112 reservation stations. @@ -79,6 +81,10 @@ def ADLPPort02_03_07_08_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07, let BufferSize = 72; } +def ADLPPortAny : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort02, ADLPPort03, + ADLPPort04, ADLPPort05, ADLPPort06, ADLPPort07, + ADLPPort08, ADLPPort09, ADLPPort10, ADLPPort11]>; + // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available // until 5 cycles after the memory operand. def : ReadAdvance; From 856a4d9f97d8de7d12d3f641496e3d103decb362 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Sat, 20 Apr 2024 10:29:22 +0000 Subject: [PATCH 3/3] Push unsaved changes --- llvm/lib/Target/X86/X86PfmCounters.td | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index c08e3e738e3fe..2b1dac411c992 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -212,10 +212,9 @@ def AlderLakePfmCounters : ProcPfmCounters { PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">, PfmIssueCounter<"ADLPPort02_03_10", "uops_dispatched_port:port_2_3_10">, PfmIssueCounter<"ADLPPort04_09", "uops_dispatched_port:port_4_9">, - PfmIssueCounter<"ADLPPort05", "uops_dispatched_port:port_5_11">, + PfmIssueCounter<"ADLPPort05_11", "uops_dispatched_port:port_5_11">, PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">, - PfmIssueCounter<"ADLPPort07_08", "uops_dispatched_port:port_7_8">, - PfmIssueCounter<"ADLPPort11", "uops_dispatched_port:port_5_11">, + PfmIssueCounter<"ADLPPort07_08", "uops_dispatched_port:port_7_8"> ]; let ValidationCounters = DefaultIntelPfmValidationCounters; }