diff --git a/llvm/test/CodeGen/AVR/powi.ll b/llvm/test/CodeGen/AVR/powi.ll new file mode 100644 index 0000000000000..35c6f8c9b883e --- /dev/null +++ b/llvm/test/CodeGen/AVR/powi.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=avr < %s | FileCheck %s + +declare float @llvm.powi.f32.i16(float, i16) +declare double @llvm.powi.f64.i16(double, i16) + +define float @powi_f32(float %a, i16 %b) { +; CHECK-LABEL: powi_f32: +; CHECK: ; %bb.0: +; CHECK-NEXT: rcall __powisf2 +; CHECK-NEXT: ret + %r = call float @llvm.powi.f32.i16(float %a, i16 %b) + ret float %r +} + +define double @powi_f64(double %a, i16 %b) { +; CHECK-LABEL: powi_f64: +; CHECK: ; %bb.0: +; CHECK-NEXT: rcall __powidf2 +; CHECK-NEXT: ret + %r = call double @llvm.powi.f64.i16(double %a, i16 %b) + ret double %r +} diff --git a/llvm/test/CodeGen/AVR/sqrt.ll b/llvm/test/CodeGen/AVR/sqrt.ll new file mode 100644 index 0000000000000..086c51ff03033 --- /dev/null +++ b/llvm/test/CodeGen/AVR/sqrt.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=avr < %s | FileCheck %s + +declare float @llvm.sqrt.f32(float) +declare double @llvm.sqrt.f64(double) + +define float @sqrt_f32(float %a) { +; CHECK-LABEL: sqrt_f32: +; CHECK: ; %bb.0: +; CHECK-NEXT: rcall sqrtf +; CHECK-NEXT: ret + %r = call float @llvm.sqrt.f32(float %a) + ret float %r +} + +define double @sqrt_f64(double %a) { +; CHECK-LABEL: sqrt_f64: +; CHECK: ; %bb.0: +; CHECK-NEXT: rcall sqrt +; CHECK-NEXT: ret + %r = call double @llvm.sqrt.f64(double %a) + ret double %r +} diff --git a/llvm/test/CodeGen/CSKY/powi.ll b/llvm/test/CodeGen/CSKY/powi.ll new file mode 100644 index 0000000000000..714de819bbb79 --- /dev/null +++ b/llvm/test/CodeGen/CSKY/powi.ll @@ -0,0 +1,53 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=csky < %s | FileCheck %s + +declare float @llvm.powi.f32.i32(float, i32) +declare double @llvm.powi.f64.i32(double, i32) + +define float @powi_f32(float %a, i32 %b) { +; CHECK-LABEL: powi_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 4 +; CHECK-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset lr, -4 +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: lrw a2, [.LCPI0_0] +; CHECK-NEXT: jsr16 a2 +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: rts16 +; CHECK-NEXT: .p2align 1 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: .LCPI0_0: +; CHECK-NEXT: .long __powisf2 + %r = call float @llvm.powi.f32.i32(float %a, i32 %b) + ret float %r +} + +define double @powi_f64(double %a, i32 %b) { +; CHECK-LABEL: powi_f64: +; CHECK: # %bb.0: +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 4 +; CHECK-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset lr, -4 +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: lrw a3, [.LCPI1_0] +; CHECK-NEXT: jsr16 a3 +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: rts16 +; CHECK-NEXT: .p2align 1 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: .LCPI1_0: +; CHECK-NEXT: .long __powidf2 + %r = call double @llvm.powi.f64.i32(double %a, i32 %b) + ret double %r +} diff --git a/llvm/test/CodeGen/CSKY/sqrt.ll b/llvm/test/CodeGen/CSKY/sqrt.ll new file mode 100644 index 0000000000000..aeea9ccb80b8d --- /dev/null +++ b/llvm/test/CodeGen/CSKY/sqrt.ll @@ -0,0 +1,53 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=csky < %s | FileCheck %s + +declare float @llvm.sqrt.f32(float) +declare double @llvm.sqrt.f64(double) + +define float @sqrt_f32(float %a) { +; CHECK-LABEL: sqrt_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 4 +; CHECK-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset lr, -4 +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: lrw a1, [.LCPI0_0] +; CHECK-NEXT: jsr16 a1 +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: rts16 +; CHECK-NEXT: .p2align 1 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: .LCPI0_0: +; CHECK-NEXT: .long sqrtf + %r = call float @llvm.sqrt.f32(float %a) + ret float %r +} + +define double @sqrt_f64(double %a) { +; CHECK-LABEL: sqrt_f64: +; CHECK: # %bb.0: +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 4 +; CHECK-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset lr, -4 +; CHECK-NEXT: subi16 sp, sp, 4 +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: lrw a2, [.LCPI1_0] +; CHECK-NEXT: jsr16 a2 +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload +; CHECK-NEXT: addi16 sp, sp, 4 +; CHECK-NEXT: rts16 +; CHECK-NEXT: .p2align 1 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: .LCPI1_0: +; CHECK-NEXT: .long sqrt + %r = call double @llvm.sqrt.f64(double %a) + ret double %r +} diff --git a/llvm/test/CodeGen/Generic/fpowi-promote.ll b/llvm/test/CodeGen/Generic/fpowi-promote.ll deleted file mode 100644 index cb7dfc7036ba5..0000000000000 --- a/llvm/test/CodeGen/Generic/fpowi-promote.ll +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: llc < %s - -; PR1239 - -; Undefined external symbol "__powisf2" -; XFAIL: target=nvptx{{.*}} - -define float @test(float %tmp23302331, i32 %tmp23282329 ) { - -%tmp2339 = call float @llvm.powi.f32.i32( float %tmp23302331, i32 %tmp23282329 ) - ret float %tmp2339 -} - -declare float @llvm.powi.f32.i32(float,i32) diff --git a/llvm/test/CodeGen/Generic/intrinsics.ll b/llvm/test/CodeGen/Generic/intrinsics.ll index 82e2b3ec7dee5..d2b62f77b5d37 100644 --- a/llvm/test/CodeGen/Generic/intrinsics.ll +++ b/llvm/test/CodeGen/Generic/intrinsics.ll @@ -1,10 +1,6 @@ ; RUN: llc < %s ; RUN: llc -O0 < %s -; NVPTX can't select sinf(float)/sin(double) -; XFAIL: target=nvptx{{.*}} - -;; SQRT declare float @llvm.sqrt.f32(float) declare double @llvm.sqrt.f64(double) @@ -16,32 +12,6 @@ define double @test_sqrt(float %F) { ret double %I } - -; SIN -declare float @sinf(float) readonly - -declare double @sin(double) readonly - -define double @test_sin(float %F) { - %G = call float @sinf( float %F ) ; [#uses=1] - %H = fpext float %G to double ; [#uses=1] - %I = call double @sin( double %H ) ; [#uses=1] - ret double %I -} - - -; COS -declare float @cosf(float) readonly - -declare double @cos(double) readonly - -define double @test_cos(float %F) { - %G = call float @cosf( float %F ) ; [#uses=1] - %H = fpext float %G to double ; [#uses=1] - %I = call double @cos( double %H ) ; [#uses=1] - ret double %I -} - declare ptr @llvm.launder.invariant.group(ptr) define ptr @launder(ptr %p) { @@ -56,9 +26,6 @@ define ptr @strip(ptr %p) { ret ptr %q } - -; sideeffect - declare void @llvm.sideeffect() define void @test_sideeffect() { diff --git a/llvm/test/CodeGen/Generic/print-arith-fp.ll b/llvm/test/CodeGen/Generic/print-arith-fp.ll index 87a2e2ee3d35d..f8dab0566cc18 100644 --- a/llvm/test/CodeGen/Generic/print-arith-fp.ll +++ b/llvm/test/CodeGen/Generic/print-arith-fp.ll @@ -5,7 +5,6 @@ @sub_str = internal constant [12 x i8] c"a - b = %f\0A\00" ; [#uses=1] @mul_str = internal constant [12 x i8] c"a * b = %f\0A\00" ; [#uses=1] @div_str = internal constant [12 x i8] c"b / a = %f\0A\00" ; [#uses=1] -@rem_str = internal constant [13 x i8] c"b %% a = %f\0A\00" ; [#uses=1] @lt_str = internal constant [12 x i8] c"a < b = %d\0A\00" ; [#uses=1] @le_str = internal constant [13 x i8] c"a <= b = %d\0A\00" ; [#uses=1] @gt_str = internal constant [12 x i8] c"a > b = %d\0A\00" ; [#uses=1] @@ -28,17 +27,14 @@ define i32 @main() { %sub_r = fsub double %a, %b ; [#uses=1] %mul_r = fmul double %a, %b ; [#uses=1] %div_r = fdiv double %b, %a ; [#uses=1] - %rem_r = frem double %b, %a ; [#uses=1] %add_s = getelementptr [12 x i8], ptr @add_str, i64 0, i64 0 ; [#uses=1] %sub_s = getelementptr [12 x i8], ptr @sub_str, i64 0, i64 0 ; [#uses=1] %mul_s = getelementptr [12 x i8], ptr @mul_str, i64 0, i64 0 ; [#uses=1] %div_s = getelementptr [12 x i8], ptr @div_str, i64 0, i64 0 ; [#uses=1] - %rem_s = getelementptr [13 x i8], ptr @rem_str, i64 0, i64 0 ; [#uses=1] call i32 (ptr, ...) @printf( ptr %add_s, double %add_r ) ; :3 [#uses=0] call i32 (ptr, ...) @printf( ptr %sub_s, double %sub_r ) ; :4 [#uses=0] call i32 (ptr, ...) @printf( ptr %mul_s, double %mul_r ) ; :5 [#uses=0] call i32 (ptr, ...) @printf( ptr %div_s, double %div_r ) ; :6 [#uses=0] - call i32 (ptr, ...) @printf( ptr %rem_s, double %rem_r ) ; :7 [#uses=0] %lt_r = fcmp olt double %a, %b ; [#uses=1] %le_r = fcmp ole double %a, %b ; [#uses=1] %gt_r = fcmp ogt double %a, %b ; [#uses=1] diff --git a/llvm/test/CodeGen/Hexagon/powi.ll b/llvm/test/CodeGen/Hexagon/powi.ll new file mode 100644 index 0000000000000..c06de8c8f8710 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/powi.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=hexagon < %s | FileCheck %s + +declare float @llvm.powi.f32.i32(float, i32) +declare double @llvm.powi.f64.i32(double, i32) + +define float @powi_f32(float %a, i32 %b) { +; CHECK-LABEL: powi_f32: +; CHECK: .cfi_startproc +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: { +; CHECK-NEXT: jump __powisf2 +; CHECK-NEXT: } + %r = call float @llvm.powi.f32.i32(float %a, i32 %b) + ret float %r +} + +define double @powi_f64(double %a, i32 %b) { +; CHECK-LABEL: powi_f64: +; CHECK: .cfi_startproc +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: { +; CHECK-NEXT: jump __powidf2 +; CHECK-NEXT: } + %r = call double @llvm.powi.f64.i32(double %a, i32 %b) + ret double %r +} diff --git a/llvm/test/CodeGen/MSP430/sqrt.ll b/llvm/test/CodeGen/MSP430/sqrt.ll new file mode 100644 index 0000000000000..67410da8ad96d --- /dev/null +++ b/llvm/test/CodeGen/MSP430/sqrt.ll @@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=msp430 < %s | FileCheck %s + +declare float @llvm.sqrt.f32(float) +declare double @llvm.sqrt.f64(double) + +define float @sqrt_f32(float %a) { +; CHECK-LABEL: sqrt_f32: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: call #sqrtf +; CHECK-NEXT: ret + %r = call float @llvm.sqrt.f32(float %a) + ret float %r +} + +define double @sqrt_f64(double %a) { +; CHECK-LABEL: sqrt_f64: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: call #sqrt +; CHECK-NEXT: ret + %r = call double @llvm.sqrt.f64(double %a) + ret double %r +} diff --git a/llvm/test/CodeGen/NVPTX/powi.ll b/llvm/test/CodeGen/NVPTX/powi.ll new file mode 100644 index 0000000000000..8daebe9204734 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/powi.ll @@ -0,0 +1,10 @@ +; RUN: not --crash llc < %s -mtriple=nvptx64 2>&1 | FileCheck %s + +declare float @llvm.powi.f32.i32(float, i32) + +; CHECK: LLVM ERROR: Cannot select: {{.*}}: f32 = fpow +; CHECK: In function: test_powi +define float @test_powi(float %a, i32 %b) { + %r = call float @llvm.powi.f32.i32(float %a, i32 %b) + ret float %r +} diff --git a/llvm/test/CodeGen/SPARC/powi.ll b/llvm/test/CodeGen/SPARC/powi.ll new file mode 100644 index 0000000000000..604bf6d700fab --- /dev/null +++ b/llvm/test/CodeGen/SPARC/powi.ll @@ -0,0 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=sparc < %s | FileCheck %s + +declare float @llvm.powi.f32.i32(float, i32) +declare double @llvm.powi.f64.i32(double, i32) + +define float @powi_f32(float %a, i32 %b) nounwind { +; CHECK-LABEL: powi_f32: +; CHECK: ! %bb.0: +; CHECK-NEXT: save %sp, -96, %sp +; CHECK-NEXT: mov %i1, %o1 +; CHECK-NEXT: call __powisf2 +; CHECK-NEXT: mov %i0, %o0 +; CHECK-NEXT: ret +; CHECK-NEXT: restore + %r = call float @llvm.powi.f32.i32(float %a, i32 %b) + ret float %r +} + +define double @powi_f64(double %a, i32 %b) nounwind { +; CHECK-LABEL: powi_f64: +; CHECK: ! %bb.0: +; CHECK-NEXT: save %sp, -112, %sp +; CHECK-NEXT: ! kill: def $i1 killed $i1 killed $i0_i1 def $i0_i1 +; CHECK-NEXT: ! kill: def $i0 killed $i0 killed $i0_i1 def $i0_i1 +; CHECK-NEXT: std %i0, [%fp+-8] +; CHECK-NEXT: ldd [%fp+-8], %f0 +; CHECK-NEXT: mov %i2, %o2 +; CHECK-NEXT: std %f0, [%fp+-16] +; CHECK-NEXT: call __powidf2 +; CHECK-NEXT: ldd [%fp+-16], %o0 +; CHECK-NEXT: ret +; CHECK-NEXT: restore + %r = call double @llvm.powi.f64.i32(double %a, i32 %b) + ret double %r +}