diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp
index 07f656fc5ccfd..b95196c081a4a 100644
--- a/llvm/lib/Target/X86/X86FixupLEAs.cpp
+++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp
@@ -343,9 +343,9 @@ static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
          Index.getReg().isValid();
 }
 
-static inline bool hasLEAOffset(const MachineOperand &Offset) {
-  return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal() ||
-         Offset.isBlockAddress();
+// Returns true if this operand may have a non-zero offset.
+static inline bool mayHaveOffset(const MachineOperand &Offset) {
+  return !(Offset.isImm() && Offset.getImm() == 0);
 }
 
 static inline unsigned getADDrrFromLEA(unsigned LEAOpcode) {
@@ -790,7 +790,7 @@ void FixupLEAsImpl::processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
   // Only do this if the LEA would otherwise be split into 2-instruction
   // (either it has a an Offset or neither base nor index are dst)
   if (IsScale1 && BaseReg == IndexReg &&
-      (hasLEAOffset(Offset) || (IsInefficientBase && !BaseOrIndexIsDst))) {
+      (mayHaveOffset(Offset) || (IsInefficientBase && !BaseOrIndexIsDst))) {
     NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
                 .add(Dest)
                 .addReg(0)
@@ -845,7 +845,7 @@ void FixupLEAsImpl::processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
   // replace the instruction.
   if (NewMI) {
     // Create ADD instruction for the Offset in case of 3-Ops LEA.
-    if (hasLEAOffset(Offset)) {
+    if (mayHaveOffset(Offset)) {
       if (OptIncDec && Offset.isImm() &&
           (Offset.getImm() == 1 || Offset.getImm() == -1)) {
         unsigned NewOpc =
@@ -877,7 +877,7 @@ void FixupLEAsImpl::processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
     return;
 
   // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
-  if (IsScale1 && !hasLEAOffset(Offset)) {
+  if (IsScale1 && !mayHaveOffset(Offset)) {
     bool BIK = Base.isKill() && BaseReg != IndexReg;
     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);
     LLVM_DEBUG(MI.getPrevNode()->dump(););
diff --git a/llvm/test/CodeGen/X86/lea-fixup-mcsymbol.mir b/llvm/test/CodeGen/X86/lea-fixup-mcsymbol.mir
new file mode 100644
index 0000000000000..373f8b0fc57e0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/lea-fixup-mcsymbol.mir
@@ -0,0 +1,20 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=slow-3ops-lea -run-pass x86-fixup-leas -o -  %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=slow-3ops-lea -passes="require<profile-summary>,function(machine-function(x86-fixup-leas))" -o -  %s | FileCheck %s
+
+--- |
+  define void @test() nounwind {
+    ret void
+  }
+
+---
+name:            test
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test
+    ; CHECK: renamable $rax = LEA64r renamable $rbx, 1, renamable $rbp, 0, $noreg
+    ; CHECK-NEXT: $rax = ADD64ri32 $rax, target-flags(x86-gotoff) <mcsymbol foo>, implicit-def $eflags
+    ; CHECK-NEXT: JMP64r renamable $rax
+    renamable $rax = LEA64r renamable $rbp, 1, renamable $rbx, target-flags(x86-gotoff) <mcsymbol foo>, $noreg
+    JMP64r renamable $rax
+...