From 6567a9e4ed24895c65b3e4c7c9ca7c7c50421fba Mon Sep 17 00:00:00 2001 From: idubinov Date: Fri, 27 Feb 2026 04:51:40 -0600 Subject: [PATCH 1/2] Fix compile warning --- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 8c3dd6f9ca8009..541be635100293 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2877,7 +2877,7 @@ bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg, [&](Register InputRegister, bool IsUnsigned) { const bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); - const unsigned IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMax + const auto IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMax : SPIRV::OpGroupNonUniformSMax; return IsFloatTy ? SPIRV::OpGroupNonUniformFMax : IntOp; }); @@ -2892,7 +2892,7 @@ bool SPIRVInstructionSelector::selectWaveReduceMin(Register ResVReg, [&](Register InputRegister, bool IsUnsigned) { const bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); - const unsigned IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMin + const auto IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMin : SPIRV::OpGroupNonUniformSMin; return IsFloatTy ? SPIRV::OpGroupNonUniformFMin : IntOp; }); From bc5b1f633c3a84143b0de727cce608c803ca69b7 Mon Sep 17 00:00:00 2001 From: idubinov Date: Fri, 27 Feb 2026 04:57:59 -0600 Subject: [PATCH 2/2] code format --- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 541be635100293..344628f2582293 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2878,7 +2878,7 @@ bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg, const bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); const auto IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMax - : SPIRV::OpGroupNonUniformSMax; + : SPIRV::OpGroupNonUniformSMax; return IsFloatTy ? SPIRV::OpGroupNonUniformFMax : IntOp; }); } @@ -2893,7 +2893,7 @@ bool SPIRVInstructionSelector::selectWaveReduceMin(Register ResVReg, const bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); const auto IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMin - : SPIRV::OpGroupNonUniformSMin; + : SPIRV::OpGroupNonUniformSMin; return IsFloatTy ? SPIRV::OpGroupNonUniformFMin : IntOp; }); }