From 0f38c43b51074b9a8ed7783853dc2d7fc58ea2d0 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Thu, 12 Feb 2026 16:19:49 +0000 Subject: [PATCH 1/5] [BOLT][AArch64] Add a unittest for compare-and-branch inversion. Checks that isReversibleBranch() returns false - when the immediate value is 63 and needs +1 adjustment - when the immediate value is 0 and needs -1 adjustment Checks that reverseBranchCondition() adjusts - the opcode - the immediate operand if necessary (+/-1) - the register operands if necessary (swap) --- bolt/unittests/Core/MCPlusBuilder.cpp | 57 +++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp index a8d25f3323b38e..e11347a8c4c941 100644 --- a/bolt/unittests/Core/MCPlusBuilder.cpp +++ b/bolt/unittests/Core/MCPlusBuilder.cpp @@ -119,6 +119,63 @@ TEST_P(MCPlusBuilderTester, AliasSmallerX0) { /*OnlySmaller=*/true); } +TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { + if (GetParam() != Triple::aarch64) + GTEST_SKIP(); + + BinaryFunction *BF = BC->createInjectedBinaryFunction("BF", true); + std::unique_ptr BB = BF->createBasicBlock(); + std::unique_ptr TargetBB = BF->createBasicBlock(); + BB->addSuccessor(TargetBB.get()); + + // cbgt x0, #0, target + MCInst NeedsImmInc = MCInstBuilder(AArch64::CBGTXri) + .addReg(AArch64::X0) + .addImm(0) + .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + BB->addInstruction(NeedsImmInc); + // cblo x0, #1, target + MCInst NeedsImmDec = MCInstBuilder(AArch64::CBLOXri) + .addReg(AArch64::X0) + .addImm(1) + .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + BB->addInstruction(NeedsImmDec); + // cbge x0, x1, target + MCInst NeedsRegSwap = MCInstBuilder(AArch64::CBGEXrr) + .addReg(AArch64::X0) + .addReg(AArch64::X1) + .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + BB->addInstruction(NeedsRegSwap); + // cbgt x0, #63, target + MCInst Irreversible = MCInstBuilder(AArch64::CBGTXri) + .addReg(AArch64::X0) + .addImm(63) + .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + BB->addInstruction(Irreversible); + + auto II = BB->begin(); + ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); + BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); + // cblt x0, #1, target + ASSERT_EQ(II->getOpcode(), AArch64::CBLTXri); + ASSERT_EQ(II->getOperand(1).getImm(), 1); + II++; + ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); + BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); + // cbhi x0, #0, target + ASSERT_EQ(II->getOpcode(), AArch64::CBHIXri); + ASSERT_EQ(II->getOperand(1).getImm(), 0); + II++; + ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); + BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); + // cbgt x1, x0, target + ASSERT_EQ(II->getOpcode(), AArch64::CBGTXrr); + ASSERT_EQ(II->getOperand(0).getReg(), AArch64::X1); + ASSERT_EQ(II->getOperand(1).getReg(), AArch64::X0); + II++; + ASSERT_FALSE(BC->MIB->isReversibleBranch(*II)); +} + TEST_P(MCPlusBuilderTester, AArch64_CmpJE) { if (GetParam() != Triple::aarch64) GTEST_SKIP(); From 67480ddd147178661dd37c948b38d44d79a78205 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Thu, 12 Feb 2026 16:39:45 +0000 Subject: [PATCH 2/5] clang-format --- bolt/unittests/Core/MCPlusBuilder.cpp | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp index e11347a8c4c941..a0fcfd798ff503 100644 --- a/bolt/unittests/Core/MCPlusBuilder.cpp +++ b/bolt/unittests/Core/MCPlusBuilder.cpp @@ -130,27 +130,31 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { // cbgt x0, #0, target MCInst NeedsImmInc = MCInstBuilder(AArch64::CBGTXri) - .addReg(AArch64::X0) - .addImm(0) - .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + .addReg(AArch64::X0) + .addImm(0) + .addExpr(MCSymbolRefExpr::create( + TargetBB->getLabel(), *BC->Ctx.get())); BB->addInstruction(NeedsImmInc); // cblo x0, #1, target MCInst NeedsImmDec = MCInstBuilder(AArch64::CBLOXri) - .addReg(AArch64::X0) - .addImm(1) - .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + .addReg(AArch64::X0) + .addImm(1) + .addExpr(MCSymbolRefExpr::create( + TargetBB->getLabel(), *BC->Ctx.get())); BB->addInstruction(NeedsImmDec); // cbge x0, x1, target MCInst NeedsRegSwap = MCInstBuilder(AArch64::CBGEXrr) - .addReg(AArch64::X0) - .addReg(AArch64::X1) - .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + .addReg(AArch64::X0) + .addReg(AArch64::X1) + .addExpr(MCSymbolRefExpr::create( + TargetBB->getLabel(), *BC->Ctx.get())); BB->addInstruction(NeedsRegSwap); // cbgt x0, #63, target MCInst Irreversible = MCInstBuilder(AArch64::CBGTXri) - .addReg(AArch64::X0) - .addImm(63) - .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); + .addReg(AArch64::X0) + .addImm(63) + .addExpr(MCSymbolRefExpr::create( + TargetBB->getLabel(), *BC->Ctx.get())); BB->addInstruction(Irreversible); auto II = BB->begin(); From 4d420fa5f2f10b7620c723fd2c73e4f594850145 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Mon, 16 Feb 2026 15:51:59 +0000 Subject: [PATCH 3/5] Added more cases to cover bytes/halfwords and under/overflow. --- bolt/unittests/Core/MCPlusBuilder.cpp | 63 +++++++++++++++++++++------ 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp index a0fcfd798ff503..0425f3672b3cbc 100644 --- a/bolt/unittests/Core/MCPlusBuilder.cpp +++ b/bolt/unittests/Core/MCPlusBuilder.cpp @@ -143,19 +143,40 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { TargetBB->getLabel(), *BC->Ctx.get())); BB->addInstruction(NeedsImmDec); // cbge x0, x1, target - MCInst NeedsRegSwap = MCInstBuilder(AArch64::CBGEXrr) - .addReg(AArch64::X0) - .addReg(AArch64::X1) - .addExpr(MCSymbolRefExpr::create( - TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(NeedsRegSwap); - // cbgt x0, #63, target - MCInst Irreversible = MCInstBuilder(AArch64::CBGTXri) - .addReg(AArch64::X0) - .addImm(63) - .addExpr(MCSymbolRefExpr::create( - TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(Irreversible); + MCInst CompRegNeedsRegSwap = MCInstBuilder(AArch64::CBGEXrr) + .addReg(AArch64::X0) + .addReg(AArch64::X1) + .addExpr(MCSymbolRefExpr::create( + TargetBB->getLabel(), *BC->Ctx.get())); + BB->addInstruction(CompRegNeedsRegSwap); + // cbbhi w0, w1, target + MCInst CompByteNeedsRegSwap = MCInstBuilder(AArch64::CBBHIWrr) + .addReg(AArch64::W0) + .addReg(AArch64::W1) + .addExpr(MCSymbolRefExpr::create( + TargetBB->getLabel(), *BC->Ctx.get())); + BB->addInstruction(CompByteNeedsRegSwap); + // cbhhs w0, w1, target + MCInst CompHalfNeedsRegSwap = MCInstBuilder(AArch64::CBHHSWrr) + .addReg(AArch64::W0) + .addReg(AArch64::W1) + .addExpr(MCSymbolRefExpr::create( + TargetBB->getLabel(), *BC->Ctx.get())); + BB->addInstruction(CompHalfNeedsRegSwap); + // cblt x0, #0, target + MCInst Underflows = MCInstBuilder(AArch64::CBLTXri) + .addReg(AArch64::X0) + .addImm(0) + .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), + *BC->Ctx.get())); + BB->addInstruction(Underflows); + // cbhi x0, #63, target + MCInst Overflows = MCInstBuilder(AArch64::CBHIXri) + .addReg(AArch64::X0) + .addImm(63) + .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), + *BC->Ctx.get())); + BB->addInstruction(Overflows); auto II = BB->begin(); ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); @@ -177,6 +198,22 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { ASSERT_EQ(II->getOperand(0).getReg(), AArch64::X1); ASSERT_EQ(II->getOperand(1).getReg(), AArch64::X0); II++; + ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); + BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); + // cbbhs w1, w0, target + ASSERT_EQ(II->getOpcode(), AArch64::CBBHSWrr); + ASSERT_EQ(II->getOperand(0).getReg(), AArch64::W1); + ASSERT_EQ(II->getOperand(1).getReg(), AArch64::W0); + II++; + ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); + BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); + // cbhhi w1, w0, target + ASSERT_EQ(II->getOpcode(), AArch64::CBHHIWrr); + ASSERT_EQ(II->getOperand(0).getReg(), AArch64::W1); + ASSERT_EQ(II->getOperand(1).getReg(), AArch64::W0); + II++; + ASSERT_FALSE(BC->MIB->isReversibleBranch(*II)); + II++; ASSERT_FALSE(BC->MIB->isReversibleBranch(*II)); } From bf29962b4ce2f588b5ffe0f5ff4577c8e4387443 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Tue, 24 Feb 2026 12:01:49 +0000 Subject: [PATCH 4/5] removed addition of instructions to basic block reordered assertions added comments --- bolt/unittests/Core/MCPlusBuilder.cpp | 102 +++++++++++++------------- 1 file changed, 50 insertions(+), 52 deletions(-) diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp index 0425f3672b3cbc..0e51bfac3bc9e6 100644 --- a/bolt/unittests/Core/MCPlusBuilder.cpp +++ b/bolt/unittests/Core/MCPlusBuilder.cpp @@ -124,97 +124,95 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { GTEST_SKIP(); BinaryFunction *BF = BC->createInjectedBinaryFunction("BF", true); - std::unique_ptr BB = BF->createBasicBlock(); std::unique_ptr TargetBB = BF->createBasicBlock(); - BB->addSuccessor(TargetBB.get()); - // cbgt x0, #0, target + // Compare register with immediate and branch. + // Inversion requires incrementing the immediate value. + // cbgt x0, #0, target ~> cblt x0, #1, target MCInst NeedsImmInc = MCInstBuilder(AArch64::CBGTXri) .addReg(AArch64::X0) .addImm(0) .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(NeedsImmInc); - // cblo x0, #1, target + ASSERT_TRUE(BC->MIB->isReversibleBranch(NeedsImmInc)); + BC->MIB->reverseBranchCondition(NeedsImmInc, TargetBB->getLabel(), BC->Ctx.get()); + ASSERT_EQ(NeedsImmInc.getOpcode(), AArch64::CBLTXri); + ASSERT_EQ(NeedsImmInc.getOperand(1).getImm(), 1); + + // Compare register with immediate and branch. + // Inversion requires decrementing the immediate value. + // cblo x0, #1, target ~> cbhi x0, #0, target MCInst NeedsImmDec = MCInstBuilder(AArch64::CBLOXri) .addReg(AArch64::X0) .addImm(1) .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(NeedsImmDec); - // cbge x0, x1, target + ASSERT_TRUE(BC->MIB->isReversibleBranch(NeedsImmDec)); + BC->MIB->reverseBranchCondition(NeedsImmDec, TargetBB->getLabel(), BC->Ctx.get()); + ASSERT_EQ(NeedsImmDec.getOpcode(), AArch64::CBHIXri); + ASSERT_EQ(NeedsImmDec.getOperand(1).getImm(), 0); + + // Compare registers and branch. + // Inversion requires swapping registers. + // cbge x0, x1, target ~> cbgt x1, x0, target MCInst CompRegNeedsRegSwap = MCInstBuilder(AArch64::CBGEXrr) .addReg(AArch64::X0) .addReg(AArch64::X1) .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(CompRegNeedsRegSwap); - // cbbhi w0, w1, target + ASSERT_TRUE(BC->MIB->isReversibleBranch(CompRegNeedsRegSwap)); + BC->MIB->reverseBranchCondition(CompRegNeedsRegSwap, TargetBB->getLabel(), BC->Ctx.get()); + ASSERT_EQ(CompRegNeedsRegSwap.getOpcode(), AArch64::CBGTXrr); + ASSERT_EQ(CompRegNeedsRegSwap.getOperand(0).getReg(), AArch64::X1); + ASSERT_EQ(CompRegNeedsRegSwap.getOperand(1).getReg(), AArch64::X0); + + // Compare bytes and branch. + // Inversion requires swapping registers. + // cbbhi w0, w1, target ~> cbbhs w1, w0, target MCInst CompByteNeedsRegSwap = MCInstBuilder(AArch64::CBBHIWrr) .addReg(AArch64::W0) .addReg(AArch64::W1) .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(CompByteNeedsRegSwap); - // cbhhs w0, w1, target + ASSERT_TRUE(BC->MIB->isReversibleBranch(CompByteNeedsRegSwap)); + BC->MIB->reverseBranchCondition(CompByteNeedsRegSwap, TargetBB->getLabel(), BC->Ctx.get()); + ASSERT_EQ(CompByteNeedsRegSwap.getOpcode(), AArch64::CBBHSWrr); + ASSERT_EQ(CompByteNeedsRegSwap.getOperand(0).getReg(), AArch64::W1); + ASSERT_EQ(CompByteNeedsRegSwap.getOperand(1).getReg(), AArch64::W0); + + // Compare halfwords and branch. + // Inversion requires swapping registers. + // cbhhs w0, w1, target ~> cbhhi w1, w0, target MCInst CompHalfNeedsRegSwap = MCInstBuilder(AArch64::CBHHSWrr) .addReg(AArch64::W0) .addReg(AArch64::W1) .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(CompHalfNeedsRegSwap); + ASSERT_TRUE(BC->MIB->isReversibleBranch(CompHalfNeedsRegSwap)); + BC->MIB->reverseBranchCondition(CompHalfNeedsRegSwap, TargetBB->getLabel(), BC->Ctx.get()); + ASSERT_EQ(CompHalfNeedsRegSwap.getOpcode(), AArch64::CBHHIWrr); + ASSERT_EQ(CompHalfNeedsRegSwap.getOperand(0).getReg(), AArch64::W1); + ASSERT_EQ(CompHalfNeedsRegSwap.getOperand(1).getReg(), AArch64::W0); + + // Compare register with immediate and branch. + // Inversion not possible, immediate value underflows. // cblt x0, #0, target MCInst Underflows = MCInstBuilder(AArch64::CBLTXri) .addReg(AArch64::X0) .addImm(0) .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(Underflows); + ASSERT_FALSE(BC->MIB->isReversibleBranch(Underflows)); + + // Compare register with immediate and branch. + // Inversion not possible, immediate value overflows. // cbhi x0, #63, target MCInst Overflows = MCInstBuilder(AArch64::CBHIXri) .addReg(AArch64::X0) .addImm(63) .addExpr(MCSymbolRefExpr::create(TargetBB->getLabel(), *BC->Ctx.get())); - BB->addInstruction(Overflows); - - auto II = BB->begin(); - ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); - BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); - // cblt x0, #1, target - ASSERT_EQ(II->getOpcode(), AArch64::CBLTXri); - ASSERT_EQ(II->getOperand(1).getImm(), 1); - II++; - ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); - BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); - // cbhi x0, #0, target - ASSERT_EQ(II->getOpcode(), AArch64::CBHIXri); - ASSERT_EQ(II->getOperand(1).getImm(), 0); - II++; - ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); - BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); - // cbgt x1, x0, target - ASSERT_EQ(II->getOpcode(), AArch64::CBGTXrr); - ASSERT_EQ(II->getOperand(0).getReg(), AArch64::X1); - ASSERT_EQ(II->getOperand(1).getReg(), AArch64::X0); - II++; - ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); - BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); - // cbbhs w1, w0, target - ASSERT_EQ(II->getOpcode(), AArch64::CBBHSWrr); - ASSERT_EQ(II->getOperand(0).getReg(), AArch64::W1); - ASSERT_EQ(II->getOperand(1).getReg(), AArch64::W0); - II++; - ASSERT_TRUE(BC->MIB->isReversibleBranch(*II)); - BC->MIB->reverseBranchCondition(*II, TargetBB->getLabel(), BC->Ctx.get()); - // cbhhi w1, w0, target - ASSERT_EQ(II->getOpcode(), AArch64::CBHHIWrr); - ASSERT_EQ(II->getOperand(0).getReg(), AArch64::W1); - ASSERT_EQ(II->getOperand(1).getReg(), AArch64::W0); - II++; - ASSERT_FALSE(BC->MIB->isReversibleBranch(*II)); - II++; - ASSERT_FALSE(BC->MIB->isReversibleBranch(*II)); + ASSERT_FALSE(BC->MIB->isReversibleBranch(Overflows)); } TEST_P(MCPlusBuilderTester, AArch64_CmpJE) { From 4017f513f89f9681210fb0ad3949009ca3f20cc8 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Tue, 24 Feb 2026 12:04:14 +0000 Subject: [PATCH 5/5] clang format --- bolt/unittests/Core/MCPlusBuilder.cpp | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp index 0e51bfac3bc9e6..d76dac04c5bb14 100644 --- a/bolt/unittests/Core/MCPlusBuilder.cpp +++ b/bolt/unittests/Core/MCPlusBuilder.cpp @@ -135,7 +135,8 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); ASSERT_TRUE(BC->MIB->isReversibleBranch(NeedsImmInc)); - BC->MIB->reverseBranchCondition(NeedsImmInc, TargetBB->getLabel(), BC->Ctx.get()); + BC->MIB->reverseBranchCondition(NeedsImmInc, TargetBB->getLabel(), + BC->Ctx.get()); ASSERT_EQ(NeedsImmInc.getOpcode(), AArch64::CBLTXri); ASSERT_EQ(NeedsImmInc.getOperand(1).getImm(), 1); @@ -148,7 +149,8 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); ASSERT_TRUE(BC->MIB->isReversibleBranch(NeedsImmDec)); - BC->MIB->reverseBranchCondition(NeedsImmDec, TargetBB->getLabel(), BC->Ctx.get()); + BC->MIB->reverseBranchCondition(NeedsImmDec, TargetBB->getLabel(), + BC->Ctx.get()); ASSERT_EQ(NeedsImmDec.getOpcode(), AArch64::CBHIXri); ASSERT_EQ(NeedsImmDec.getOperand(1).getImm(), 0); @@ -161,7 +163,8 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); ASSERT_TRUE(BC->MIB->isReversibleBranch(CompRegNeedsRegSwap)); - BC->MIB->reverseBranchCondition(CompRegNeedsRegSwap, TargetBB->getLabel(), BC->Ctx.get()); + BC->MIB->reverseBranchCondition(CompRegNeedsRegSwap, TargetBB->getLabel(), + BC->Ctx.get()); ASSERT_EQ(CompRegNeedsRegSwap.getOpcode(), AArch64::CBGTXrr); ASSERT_EQ(CompRegNeedsRegSwap.getOperand(0).getReg(), AArch64::X1); ASSERT_EQ(CompRegNeedsRegSwap.getOperand(1).getReg(), AArch64::X0); @@ -175,7 +178,8 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); ASSERT_TRUE(BC->MIB->isReversibleBranch(CompByteNeedsRegSwap)); - BC->MIB->reverseBranchCondition(CompByteNeedsRegSwap, TargetBB->getLabel(), BC->Ctx.get()); + BC->MIB->reverseBranchCondition(CompByteNeedsRegSwap, TargetBB->getLabel(), + BC->Ctx.get()); ASSERT_EQ(CompByteNeedsRegSwap.getOpcode(), AArch64::CBBHSWrr); ASSERT_EQ(CompByteNeedsRegSwap.getOperand(0).getReg(), AArch64::W1); ASSERT_EQ(CompByteNeedsRegSwap.getOperand(1).getReg(), AArch64::W0); @@ -189,7 +193,8 @@ TEST_P(MCPlusBuilderTester, AArch64_ReverseCompAndBranch) { .addExpr(MCSymbolRefExpr::create( TargetBB->getLabel(), *BC->Ctx.get())); ASSERT_TRUE(BC->MIB->isReversibleBranch(CompHalfNeedsRegSwap)); - BC->MIB->reverseBranchCondition(CompHalfNeedsRegSwap, TargetBB->getLabel(), BC->Ctx.get()); + BC->MIB->reverseBranchCondition(CompHalfNeedsRegSwap, TargetBB->getLabel(), + BC->Ctx.get()); ASSERT_EQ(CompHalfNeedsRegSwap.getOpcode(), AArch64::CBHHIWrr); ASSERT_EQ(CompHalfNeedsRegSwap.getOperand(0).getReg(), AArch64::W1); ASSERT_EQ(CompHalfNeedsRegSwap.getOperand(1).getReg(), AArch64::W0);