From b1bc9cb5d51076b504ed629477f99ada22eb64bd Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Fri, 6 Feb 2026 16:49:18 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?= =?UTF-8?q?anges=20to=20main=20this=20commit=20is=20based=20on?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.6-beta.1 [skip ci] --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 9 + llvm/docs/RISCVUsage.rst | 3 + llvm/docs/ReleaseNotes.md | 2 + llvm/lib/Target/RISCV/RISCVFeatures.td | 6 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + .../Target/RISCV/RISCVInstrInfoVPseudos.td | 19 +- .../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 29 +- .../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 32 +- llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td | 51 ++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 + llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/CodeGen/RISCV/rvv/abd.ll | 140 +++++++++ .../CodeGen/RISCV/rvv/fixed-vectors-abd.ll | 284 ++++++++++++++++++ .../CodeGen/RISCV/rvv/fixed-vectors-sad.ll | 83 +++++ llvm/test/MC/RISCV/rvv/zvabd-invalid.s | 10 + llvm/test/MC/RISCV/rvv/zvabd.s | 63 ++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 19 files changed, 720 insertions(+), 29 deletions(-) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td create mode 100644 llvm/test/MC/RISCV/rvv/zvabd-invalid.s create mode 100644 llvm/test/MC/RISCV/rvv/zvabd.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 8337d9f12fabd..3abafb6deafb2 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -245,6 +245,7 @@ // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) +// CHECK-NEXT: zvabd 0.7 'Zvabd' (Vector Absolute Difference) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) // CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index e315f75b15614..833a64d23c4e0 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -140,6 +140,7 @@ // CHECK-NOT: __riscv_zkt {{.*$}} // CHECK-NOT: __riscv_zmmul {{.*$}} // CHECK-NOT: __riscv_ztso {{.*$}} +// CHECK-NOT: __riscv_zvabd {{.*$}} // CHECK-NOT: __riscv_zvbb {{.*$}} // CHECK-NOT: __riscv_zvbc {{.*$}} // CHECK-NOT: __riscv_zve32f {{.*$}} @@ -1382,6 +1383,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvabd0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvabd0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// CHECK-ZVABD-EXT: __riscv_zvabd 7000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_zve64x_zvbb1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index b58ecc105620a..6fd52df010991 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -356,6 +356,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smpmpmt`` LLVM implements the `0.6 draft specification `__. +``experimental-zvabd`` + LLVM implements the `0.7 draft specification `__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 2a535dc0530a0..f9be659ed9bd4 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -129,6 +129,8 @@ Changes to the RISC-V Backend `sspush`, `sspopchk`, `ssrdp`, `c.sspush`, `c.sspopchk`) are now always available in the assembler and disassembler without requiring their respective extensions. +* Adds experimental assembler support for the 'Zvabd` (RISC-V Integer Vector + Absolute Difference) extension. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e8c8543992865..de7f14802002e 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -688,6 +688,12 @@ def FeatureStdExtV [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, RISCVExtensionBitmask<0, 21>; +def FeatureStdExtZvabd + : RISCVExperimentalExtension<0, 7, "Vector Absolute Difference">; +def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">, + AssemblerPredicate<(all_of FeatureStdExtZvabd), + "'Zvabd' (Vector Absolute Difference)">; + def FeatureStdExtZvfbfa : RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support", [FeatureStdExtZve32f, FeatureStdExtZfbfmin]>; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index b9d8ffc19e51a..6e236fcdae82d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -995,7 +995,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, Legal); - setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); + if (Subtarget.hasStdExtZvabd()) + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal); + else + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); // Custom-lower extensions and truncations from/to mask types. setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, @@ -7526,6 +7529,8 @@ static unsigned getRISCVVLOp(SDValue Op) { OP_CASE(SMAX) OP_CASE(UMIN) OP_CASE(UMAX) + OP_CASE(ABDS) + OP_CASE(ABDU) OP_CASE(STRICT_FADD) OP_CASE(STRICT_FSUB) OP_CASE(STRICT_FMUL) @@ -8814,6 +8819,9 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, return lowerToScalableOp(Op, DAG); case ISD::ABDS: case ISD::ABDU: { + if (Subtarget.hasStdExtZvabd()) + return lowerToScalableOp(Op, DAG); + SDLoc dl(Op); EVT VT = Op->getValueType(0); SDValue LHS = DAG.getFreeze(Op->getOperand(0)); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 156e41ede2d1e..699a1b0bf3cd3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2353,6 +2353,7 @@ include "RISCVInstrInfoZk.td" // Vector include "RISCVInstrInfoV.td" +include "RISCVInstrInfoZvabd.td" include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoZvqdotq.td" include "RISCVInstrInfoZvfofp8min.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 4e2b162507f52..fe7dc2a21bd7f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2817,14 +2817,19 @@ multiclass VPseudoVFRDIV_VF_RM { } } -multiclass VPseudoVALU_VV_VX { - foreach m = MxList in { - defm "" : VPseudoBinaryV_VV, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, - forcePassthruRead=true>; +multiclass VPseudoVALU_VV { + foreach m = MxList in { + defm "" : VPseudoBinaryV_VV, + SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, + forcePassthruRead=true>; + } +} + +multiclass VPseudoVALU_VV_VX : VPseudoVALU_VV { + foreach m = MxList in { defm "" : VPseudoBinaryV_VX, - SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX, - forcePassthruRead=true>; + SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX, + forcePassthruRead=true>; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 38d0cf16a2da0..a469d7a04ec36 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -123,20 +123,29 @@ class VPatBinarySDNode_XI; +multiclass VPatBinarySDNode_VV vtilist = AllIntegerVectors, + bit isSEWAware = 0, + list ExtraPreds = []> { + foreach vti = vtilist in { + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in + def : VPatBinarySDNode_VV; + } +} + multiclass VPatBinarySDNode_VV_VX vtilist = AllIntegerVectors, bit isSEWAware = 0, - list ExtraPreds = []> { + list ExtraPreds = []> + : VPatBinarySDNode_VV { foreach vti = vtilist in { - let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in { - def : VPatBinarySDNode_VV; - def : VPatBinarySDNode_XI; - } + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in + def : VPatBinarySDNode_XI; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 51c7175a07474..46b1cefcf6dc0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -910,21 +910,31 @@ class VPatBinaryVL_XI; +multiclass VPatBinaryVL_VV vtilist = AllIntegerVectors, + bit isSEWAware = 0, + list ExtraPreds = []> { + foreach vti = vtilist in { + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in { + def : VPatBinaryVL_V; + } + } +} + multiclass VPatBinaryVL_VV_VX vtilist = AllIntegerVectors, bit isSEWAware = 0, - list ExtraPreds = []> { + list ExtraPreds = []> + : VPatBinaryVL_VV{ foreach vti = vtilist in { - let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in { - def : VPatBinaryVL_V; - def : VPatBinaryVL_XI; - } + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in + def : VPatBinaryVL_XI; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td new file mode 100644 index 0000000000000..c73d0f20a7e8b --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td @@ -0,0 +1,51 @@ +//===-- RISCVInstrInfoZvabd.td - 'Zvabd' instructions ------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions for 'Zvabd' (Vector Absolute +/// Difference). +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Definitions +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvabd] in { + defm VABS_V : VALU_MV_VS2<"vabs.v", 0b010010, 0b10000>; + + def VABD_VV : VALUVV<0b010001, OPMVV, "vabd.vv">; + def VABDU_VV : VALUVV<0b010011, OPMVV, "vabdu.vv">; + + let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { + def VWABDA_VV : VALUVV<0b010101, OPMVV, "vwabda.vv">; + def VWABDAU_VV : VALUVV<0b010110, OPMVV, "vwabdau.vv">; + } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV +} // Predicates = [HasStdExtZvabd] + +//===----------------------------------------------------------------------===// +// Pseudos +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvabd] in { + defm PseudoVABD : VPseudoVALU_VV; + defm PseudoVABDU : VPseudoVALU_VV; +} // Predicates = [HasStdExtZvabd] + +//===----------------------------------------------------------------------===// +// CodeGen Patterns +//===----------------------------------------------------------------------===// +let HasPassthruOp = true, HasMaskOp = true in { +def riscv_abds_vl : RVSDNode<"ABDS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; +def riscv_abdu_vl : RVSDNode<"ABDU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; +} // let HasPassthruOp = true, HasMaskOp = true + +let Predicates = [HasStdExtZvabd] in { +defm : VPatBinarySDNode_VV; +defm : VPatBinarySDNode_VV; + +defm : VPatBinaryVL_VV; +defm : VPatBinaryVL_VV; +} // Predicates = [HasStdExtZvabd] diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 522dc3579deb1..a17e199eed994 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -111,6 +111,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV32ZVQDOTQ %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV32ZVABD %s ; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s ; RUN: llc -mtriple=riscv32 -mattr=+zilsd %s -o - | FileCheck --check-prefix=RV32ZILSD %s ; RUN: llc -mtriple=riscv32 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s @@ -265,6 +266,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV64ZVQDOTQ %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s ; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s @@ -430,6 +432,7 @@ ; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV32ZVQDOTQ: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0" ; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV32ZVABD: .attribute 5, "rv32i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" ; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0" ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0" @@ -582,6 +585,7 @@ ; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV64ZVQDOTQ: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0" ; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0" ; RV64ZCMOP: .attribute 5, "rv64i2p1_c2p0_zca1p0_zcmop1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 5eadff68895de..c2e56061bf579 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -39,6 +39,7 @@ ; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate). ; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). +; CHECK-NEXT: experimental-zvabd - 'Zvabd' (Vector Absolute Difference). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). ; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts). diff --git a/llvm/test/CodeGen/RISCV/rvv/abd.ll b/llvm/test/CodeGen/RISCV/rvv/abd.ll index 949a9a3dfc470..837e53af5578e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abd.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV64 ; ; SABD @@ -14,6 +16,12 @@ define @sabd_b( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -30,6 +38,14 @@ define @sabd_b_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -45,6 +61,12 @@ define @sabd_h( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -63,6 +85,14 @@ define @sabd_h_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -78,6 +108,12 @@ define @sabd_s( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -96,6 +132,14 @@ define @sabd_s_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -111,6 +155,12 @@ define @sabd_d( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -129,6 +179,14 @@ define @sabd_d_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -148,6 +206,12 @@ define @uabd_b( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -164,6 +228,14 @@ define @uabd_b_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -179,6 +251,12 @@ define @uabd_h( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -197,6 +275,14 @@ define @uabd_h_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -212,6 +298,12 @@ define @uabd_s( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -230,6 +322,14 @@ define @uabd_s_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -245,6 +345,12 @@ define @uabd_d( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -263,6 +369,14 @@ define @uabd_d_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -281,6 +395,13 @@ define @uabd_non_matching_extension( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -302,6 +423,15 @@ define @uabd_non_matching_promoted_ops( %a, ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_non_matching_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v10, v8 +; ZVABD-NEXT: vabdu.vv v10, v10, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -321,6 +451,14 @@ define @uabd_non_matching_promotion( %a, %a to %b.zext = sext %b to %sub = sub %a.zext, %b.zext @@ -331,3 +469,5 @@ define @uabd_non_matching_promotion( %a, @sabd_8b_as_16b(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8b_as_16b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i8> %a to <8 x i16> %b.sext = sext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.sext, %b.sext @@ -31,6 +39,12 @@ define <8 x i8> @sabd_8b_as_32b(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8b_as_32b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i8> %a to <8 x i32> %b.sext = sext <8 x i8> %b to <8 x i32> %sub = sub <8 x i32> %a.sext, %b.sext @@ -48,6 +62,12 @@ define <16 x i8> @sabd_16b(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_16b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <16 x i8> %a to <16 x i16> %b.sext = sext <16 x i8> %b to <16 x i16> %sub = sub <16 x i16> %a.sext, %b.sext @@ -65,6 +85,12 @@ define <4 x i16> @sabd_4h(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <4 x i16> %a to <4 x i32> %b.sext = sext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.sext, %b.sext @@ -84,6 +110,14 @@ define <4 x i16> @sabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <4 x i8> %a to <4 x i16> %b.sext = sext <4 x i8> %b to <4 x i16> %sub = sub <4 x i16> %a.sext, %b.sext @@ -100,6 +134,12 @@ define <8 x i16> @sabd_8h(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i16> %a to <8 x i32> %b.sext = sext <8 x i16> %b to <8 x i32> %sub = sub <8 x i32> %a.sext, %b.sext @@ -119,6 +159,14 @@ define <8 x i16> @sabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i8> %a to <8 x i16> %b.sext = sext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.sext, %b.sext @@ -135,6 +183,12 @@ define <2 x i32> @sabd_2s(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <2 x i32> %a to <2 x i64> %b.sext = sext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.sext, %b.sext @@ -154,6 +208,14 @@ define <2 x i32> @sabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <2 x i16> %a to <2 x i32> %b.sext = sext <2 x i16> %b to <2 x i32> %sub = sub <2 x i32> %a.sext, %b.sext @@ -170,6 +232,12 @@ define <4 x i32> @sabd_4s(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <4 x i32> %a to <4 x i64> %b.sext = sext <4 x i32> %b to <4 x i64> %sub = sub <4 x i64> %a.sext, %b.sext @@ -189,6 +257,14 @@ define <4 x i32> @sabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <4 x i16> %a to <4 x i32> %b.sext = sext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.sext, %b.sext @@ -204,6 +280,12 @@ define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <2 x i64> %a to <2 x i128> %b.sext = sext <2 x i64> %b to <2 x i128> %sub = sub <2 x i128> %a.sext, %b.sext @@ -223,6 +305,14 @@ define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2d_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e64, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <2 x i32> %a to <2 x i64> %b.sext = sext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.sext, %b.sext @@ -243,6 +333,12 @@ define <8 x i8> @uabd_8b(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_8b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <8 x i8> %a to <8 x i16> %b.zext = zext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.zext, %b.zext @@ -260,6 +356,12 @@ define <16 x i8> @uabd_16b(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_16b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <16 x i8> %a to <16 x i16> %b.zext = zext <16 x i8> %b to <16 x i16> %sub = sub <16 x i16> %a.zext, %b.zext @@ -277,6 +379,12 @@ define <4 x i16> @uabd_4h(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <4 x i16> %a to <4 x i32> %b.zext = zext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.zext, %b.zext @@ -296,6 +404,14 @@ define <4 x i16> @uabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <4 x i8> %a to <4 x i16> %b.zext = zext <4 x i8> %b to <4 x i16> %sub = sub <4 x i16> %a.zext, %b.zext @@ -312,6 +428,12 @@ define <8 x i16> @uabd_8h(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_8h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <8 x i16> %a to <8 x i32> %b.zext = zext <8 x i16> %b to <8 x i32> %sub = sub <8 x i32> %a.zext, %b.zext @@ -331,6 +453,14 @@ define <8 x i16> @uabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_8h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <8 x i8> %a to <8 x i16> %b.zext = zext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.zext, %b.zext @@ -347,6 +477,12 @@ define <2 x i32> @uabd_2s(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <2 x i32> %a to <2 x i64> %b.zext = zext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.zext, %b.zext @@ -366,6 +502,14 @@ define <2 x i32> @uabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <2 x i16> %a to <2 x i32> %b.zext = zext <2 x i16> %b to <2 x i32> %sub = sub <2 x i32> %a.zext, %b.zext @@ -382,6 +526,12 @@ define <4 x i32> @uabd_4s(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <4 x i32> %a to <4 x i64> %b.zext = zext <4 x i32> %b to <4 x i64> %sub = sub <4 x i64> %a.zext, %b.zext @@ -401,6 +551,14 @@ define <4 x i32> @uabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <4 x i16> %a to <4 x i32> %b.zext = zext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.zext, %b.zext @@ -416,6 +574,12 @@ define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <2 x i64> %a to <2 x i128> %b.zext = zext <2 x i64> %b to <2 x i128> %sub = sub <2 x i128> %a.zext, %b.zext @@ -435,6 +599,14 @@ define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2d_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e64, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <2 x i32> %a to <2 x i64> %b.zext = zext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.zext, %b.zext @@ -451,6 +623,14 @@ define <16 x i8> @uabd_v16i8_nuw(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v16i8_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vrsub.vi v9, v8, 0 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nuw <16 x i8> %a, %b %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true) ret <16 x i8> %abs @@ -465,6 +645,14 @@ define <8 x i16> @uabd_v8i16_nuw(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v8i16_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vrsub.vi v9, v8, 0 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nuw <8 x i16> %a, %b %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) ret <8 x i16> %abs @@ -479,6 +667,14 @@ define <4 x i32> @uabd_v4i32_nuw(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v4i32_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vrsub.vi v9, v8, 0 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nuw <4 x i32> %a, %b %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) ret <4 x i32> %abs @@ -493,6 +689,14 @@ define <2 x i64> @uabd_v2i64_nuw(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v2i64_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vrsub.vi v9, v8, 0 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nuw <2 x i64> %a, %b %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) ret <2 x i64> %abs @@ -507,6 +711,12 @@ define <16 x i8> @sabd_v16i8_nsw(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v16i8_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nsw <16 x i8> %a, %b %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true) ret <16 x i8> %abs @@ -521,6 +731,12 @@ define <8 x i16> @sabd_v8i16_nsw(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v8i16_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nsw <8 x i16> %a, %b %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) ret <8 x i16> %abs @@ -535,6 +751,12 @@ define <4 x i32> @sabd_v4i32_nsw(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v4i32_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nsw <4 x i32> %a, %b %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) ret <4 x i32> %abs @@ -549,6 +771,12 @@ define <2 x i64> @sabd_v2i64_nsw(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v2i64_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nsw <2 x i64> %a, %b %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) ret <2 x i64> %abs @@ -563,6 +791,12 @@ define <16 x i8> @smaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v16i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <16 x i8> @llvm.smax.v16i8(<16 x i8> %0, <16 x i8> %1) %b = tail call <16 x i8> @llvm.smin.v16i8(<16 x i8> %0, <16 x i8> %1) %sub = sub <16 x i8> %a, %b @@ -578,6 +812,12 @@ define <8 x i16> @smaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v8i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <8 x i16> @llvm.smax.v8i16(<8 x i16> %0, <8 x i16> %1) %b = tail call <8 x i16> @llvm.smin.v8i16(<8 x i16> %0, <8 x i16> %1) %sub = sub <8 x i16> %a, %b @@ -593,6 +833,12 @@ define <4 x i32> @smaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %0, <4 x i32> %1) %b = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %0, <4 x i32> %1) %sub = sub <4 x i32> %a, %b @@ -608,6 +854,12 @@ define <2 x i64> @smaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v2i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <2 x i64> @llvm.smax.v2i64(<2 x i64> %0, <2 x i64> %1) %b = tail call <2 x i64> @llvm.smin.v2i64(<2 x i64> %0, <2 x i64> %1) %sub = sub <2 x i64> %a, %b @@ -623,6 +875,12 @@ define <16 x i8> @umaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v16i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1) %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %0, <16 x i8> %1) %sub = sub <16 x i8> %a, %b @@ -638,6 +896,12 @@ define <8 x i16> @umaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v8i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <8 x i16> @llvm.umax.v8i16(<8 x i16> %0, <8 x i16> %1) %b = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> %0, <8 x i16> %1) %sub = sub <8 x i16> %a, %b @@ -653,6 +917,12 @@ define <4 x i32> @umaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %0, <4 x i32> %1) %b = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %0, <4 x i32> %1) %sub = sub <4 x i32> %a, %b @@ -668,6 +938,12 @@ define <2 x i64> @umaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v2i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <2 x i64> @llvm.umax.v2i64(<2 x i64> %0, <2 x i64> %1) %b = tail call <2 x i64> @llvm.umin.v2i64(<2 x i64> %0, <2 x i64> %1) %sub = sub <2 x i64> %a, %b @@ -683,6 +959,12 @@ define <16 x i8> @umaxmin_v16i8_com1(<16 x i8> %0, <16 x i8> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v16i8_com1: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1) %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %1, <16 x i8> %0) %sub = sub <16 x i8> %a, %b @@ -692,3 +974,5 @@ define <16 x i8> @umaxmin_v16i8_com1(<16 x i8> %0, <16 x i8> %1) { ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; RV32: {{.*}} ; RV64: {{.*}} +; ZVABD-RV32: {{.*}} +; ZVABD-RV64: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll index 71c32f1473b7f..65010fdbdc2bb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefix=ZVABD +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefix=ZVABD define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) { ; CHECK-LABEL: sad_4x8_as_i16: @@ -16,6 +18,18 @@ define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_4x8_as_i16: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vmv.s.x v9, zero +; ZVABD-NEXT: vsetvli zero, zero, e8, mf4, ta, ma +; ZVABD-NEXT: vwredsumu.vs v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <4 x i8> %a to <4 x i16> %3 = zext <4 x i8> %b to <4 x i16> @@ -38,6 +52,17 @@ define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vredsum.vs v8, v9, v8 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_4x8_as_i32: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; ZVABD-NEXT: vzext.vf4 v9, v8 +; ZVABD-NEXT: vmv.s.x v8, zero +; ZVABD-NEXT: vredsum.vs v8, v9, v8 +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <4 x i8> %a to <4 x i32> %3 = zext <4 x i8> %b to <4 x i32> @@ -61,6 +86,18 @@ define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_16x8_as_i16: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vmv.s.x v9, zero +; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; ZVABD-NEXT: vwredsumu.vs v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <16 x i8> %a to <16 x i16> %3 = zext <16 x i8> %b to <16 x i16> @@ -83,6 +120,17 @@ define signext i32 @sad_16x8_as_i32(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vredsum.vs v8, v8, v12 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_16x8_as_i32: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v12, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; ZVABD-NEXT: vzext.vf4 v8, v12 +; ZVABD-NEXT: vmv.s.x v12, zero +; ZVABD-NEXT: vredsum.vs v8, v8, v12 +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <16 x i8> %a to <16 x i32> %3 = zext <16 x i8> %b to <16 x i32> @@ -135,6 +183,41 @@ define signext i32 @sad_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea ; CHECK-NEXT: vredsum.vs v8, v8, v12 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_2block_16xi8_as_i32: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vle8.v v8, (a0) +; ZVABD-NEXT: vle8.v v9, (a1) +; ZVABD-NEXT: add a0, a0, a2 +; ZVABD-NEXT: add a1, a1, a3 +; ZVABD-NEXT: vle8.v v10, (a0) +; ZVABD-NEXT: vle8.v v11, (a1) +; ZVABD-NEXT: add a0, a0, a2 +; ZVABD-NEXT: add a1, a1, a3 +; ZVABD-NEXT: vle8.v v14, (a0) +; ZVABD-NEXT: vle8.v v15, (a1) +; ZVABD-NEXT: add a0, a0, a2 +; ZVABD-NEXT: add a1, a1, a3 +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vle8.v v9, (a0) +; ZVABD-NEXT: vabdu.vv v10, v10, v11 +; ZVABD-NEXT: vle8.v v11, (a1) +; ZVABD-NEXT: vwaddu.vv v12, v10, v8 +; ZVABD-NEXT: vabdu.vv v8, v14, v15 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v14, v8 +; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v16, v9, v11 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vwaddu.vv v8, v14, v12 +; ZVABD-NEXT: vzext.vf2 v12, v16 +; ZVABD-NEXT: vwaddu.wv v8, v8, v12 +; ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; ZVABD-NEXT: vmv.s.x v12, zero +; ZVABD-NEXT: vredsum.vs v8, v8, v12 +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %idx.ext8 = sext i32 %strideb to i64 %idx.ext = sext i32 %stridea to i64 diff --git a/llvm/test/MC/RISCV/rvv/zvabd-invalid.s b/llvm/test/MC/RISCV/rvv/zvabd-invalid.s new file mode 100644 index 0000000000000..ec4529b9289cb --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvabd-invalid.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+experimental-zvabd %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vwabda.vv v9, v9, v8 +# CHECK-ERROR: [[@LINE-1]]:11: error: the destination vector register group cannot overlap the source vector register group +# CHECK-ERROR-LABEL: vwabda.vv v9, v9, v8 + +vwabdau.vv v9, v9, v8 +# CHECK-ERROR: [[@LINE-1]]:12: error: the destination vector register group cannot overlap the source vector register group +# CHECK-ERROR-LABEL: vwabdau.vv v9, v9, v8 diff --git a/llvm/test/MC/RISCV/rvv/zvabd.s b/llvm/test/MC/RISCV/rvv/zvabd.s new file mode 100644 index 0000000000000..2b994ebf94ba6 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvabd.s @@ -0,0 +1,63 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvabd --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vabs.v v9, v8 +# CHECK-INST: vabs.v v9, v8 +# CHECK-ENCODING: [0xd7,0x24,0x88,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4a8824d7 + +vabd.vv v10, v9, v8 +# CHECK-INST: vabd.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x46] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 46942557 + +vabd.vv v10, v9, v8, v0.t +# CHECK-INST: vabd.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x44] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 44942557 + +vabdu.vv v10, v9, v8 +# CHECK-INST: vabdu.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x4e] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4e942557 + +vabdu.vv v10, v9, v8, v0.t +# CHECK-INST: vabdu.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x4c] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4c942557 + +vwabda.vv v10, v9, v8 +# CHECK-INST: vwabda.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x56] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 56942557 + +vwabda.vv v10, v9, v8, v0.t +# CHECK-INST: vwabda.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 54942557 + +vwabdau.vv v10, v9, v8 +# CHECK-INST: vwabdau.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x5a] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 5a942557 + +vwabdau.vv v10, v9, v8, v0.t +# CHECK-INST: vwabdau.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x58] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 58942557 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index c07551e6cff00..fa09135136889 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1397,6 +1397,7 @@ Experimental extensions zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 + zvabd 0.7 zvbc32e 0.7 zvfbfa 0.1 zvfofp8min 0.2 From 15d8489aaab95fb41b08387076c6c0b7cce9bc42 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Fri, 6 Feb 2026 18:10:44 +0800 Subject: [PATCH 2/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?= =?UTF-8?q?anges=20introduced=20through=20rebase?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.6-beta.1 [skip ci] --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 18 ++++-- llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td | 13 +++-- llvm/test/CodeGen/RISCV/rvv/abd.ll | 32 ++++++++--- .../CodeGen/RISCV/rvv/fixed-vectors-abd.ll | 56 ++++++++++++++----- 4 files changed, 88 insertions(+), 31 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 6e236fcdae82d..387dc2ba5f388 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -995,9 +995,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, Legal); - if (Subtarget.hasStdExtZvabd()) - setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal); - else + if (Subtarget.hasStdExtZvabd()) { + // Only SEW=8/16 are supported in Zvabd. + if (VT.getVectorElementType() == MVT::i8 || + VT.getVectorElementType() == MVT::i16) + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal); + else + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); + } else setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); // Custom-lower extensions and truncations from/to mask types. @@ -8819,11 +8824,14 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, return lowerToScalableOp(Op, DAG); case ISD::ABDS: case ISD::ABDU: { - if (Subtarget.hasStdExtZvabd()) + EVT VT = Op->getValueType(0); + // Only SEW=8/16 are supported in Zvabd. + if (Subtarget.hasStdExtZvabd() && VT.isVector() && + (VT.getVectorElementType() == MVT::i8 || + VT.getVectorElementType() == MVT::i16)) return lowerToScalableOp(Op, DAG); SDLoc dl(Op); - EVT VT = Op->getValueType(0); SDValue LHS = DAG.getFreeze(Op->getOperand(0)); SDValue RHS = DAG.getFreeze(Op->getOperand(1)); bool IsSigned = Op->getOpcode() == ISD::ABDS; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td index c73d0f20a7e8b..fa7b188fc7325 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td @@ -42,10 +42,15 @@ def riscv_abds_vl : RVSDNode<"ABDS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]> def riscv_abdu_vl : RVSDNode<"ABDU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; } // let HasPassthruOp = true, HasMaskOp = true +// These instructions are defined for SEW=8 and SEW=16, otherwise the instruction +// encoding is reserved. +defvar ABDIntVectors = !filter(vti, AllIntegerVectors, !or(!eq(vti.SEW, 8), + !eq(vti.SEW, 16))); + let Predicates = [HasStdExtZvabd] in { -defm : VPatBinarySDNode_VV; -defm : VPatBinarySDNode_VV; +defm : VPatBinarySDNode_VV; +defm : VPatBinarySDNode_VV; -defm : VPatBinaryVL_VV; -defm : VPatBinaryVL_VV; +defm : VPatBinaryVL_VV; +defm : VPatBinaryVL_VV; } // Predicates = [HasStdExtZvabd] diff --git a/llvm/test/CodeGen/RISCV/rvv/abd.ll b/llvm/test/CodeGen/RISCV/rvv/abd.ll index 837e53af5578e..c451559a29a69 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abd.ll @@ -112,7 +112,9 @@ define @sabd_s( %a, %b) ; ZVABD-LABEL: sabd_s: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: vmin.vv v12, v8, v10 +; ZVABD-NEXT: vmax.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 ; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to @@ -159,7 +161,9 @@ define @sabd_d( %a, %b) ; ZVABD-LABEL: sabd_d: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: vmin.vv v12, v8, v10 +; ZVABD-NEXT: vmax.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 ; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to @@ -183,7 +187,9 @@ define @sabd_d_promoted_ops( %a, @uabd_s( %a, %b) ; ZVABD-LABEL: uabd_s: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: vminu.vv v12, v8, v10 +; ZVABD-NEXT: vmaxu.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 ; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to @@ -349,7 +357,9 @@ define @uabd_d( %a, %b) ; ZVABD-LABEL: uabd_d: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma -; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: vminu.vv v12, v8, v10 +; ZVABD-NEXT: vmaxu.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 ; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to @@ -373,7 +383,9 @@ define @uabd_d_promoted_ops( %a, @uabd_non_matching_extension( %a, %a to %b.zext = zext %b to @@ -457,7 +471,9 @@ define @uabd_non_matching_promotion( %a, %a to %b.zext = sext %b to diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll index ce4d3f9392697..998668dc26bb8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll @@ -187,7 +187,9 @@ define <2 x i32> @sabd_2s(<2 x i32> %a, <2 x i32> %b) { ; ZVABD-LABEL: sabd_2s: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a.sext = sext <2 x i32> %a to <2 x i64> %b.sext = sext <2 x i32> %b to <2 x i64> @@ -236,7 +238,9 @@ define <4 x i32> @sabd_4s(<4 x i32> %a, <4 x i32> %b) { ; ZVABD-LABEL: sabd_4s: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a.sext = sext <4 x i32> %a to <4 x i64> %b.sext = sext <4 x i32> %b to <4 x i64> @@ -284,7 +288,9 @@ define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) { ; ZVABD-LABEL: sabd_2d: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a.sext = sext <2 x i64> %a to <2 x i128> %b.sext = sext <2 x i64> %b to <2 x i128> @@ -309,7 +315,9 @@ define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) { ; ZVABD-LABEL: sabd_2d_promoted_ops: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v9, v8, v10 ; ZVABD-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; ZVABD-NEXT: vzext.vf2 v8, v9 ; ZVABD-NEXT: ret @@ -481,7 +489,9 @@ define <2 x i32> @uabd_2s(<2 x i32> %a, <2 x i32> %b) { ; ZVABD-LABEL: uabd_2s: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a.zext = zext <2 x i32> %a to <2 x i64> %b.zext = zext <2 x i32> %b to <2 x i64> @@ -530,7 +540,9 @@ define <4 x i32> @uabd_4s(<4 x i32> %a, <4 x i32> %b) { ; ZVABD-LABEL: uabd_4s: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a.zext = zext <4 x i32> %a to <4 x i64> %b.zext = zext <4 x i32> %b to <4 x i64> @@ -578,7 +590,9 @@ define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) { ; ZVABD-LABEL: uabd_2d: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a.zext = zext <2 x i64> %a to <2 x i128> %b.zext = zext <2 x i64> %b to <2 x i128> @@ -603,7 +617,9 @@ define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) { ; ZVABD-LABEL: uabd_2d_promoted_ops: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v9, v8, v10 ; ZVABD-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; ZVABD-NEXT: vzext.vf2 v8, v9 ; ZVABD-NEXT: ret @@ -755,7 +771,9 @@ define <4 x i32> @sabd_v4i32_nsw(<4 x i32> %a, <4 x i32> %b) { ; ZVABD-LABEL: sabd_v4i32_nsw: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %sub = sub nsw <4 x i32> %a, %b %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) @@ -775,7 +793,9 @@ define <2 x i64> @sabd_v2i64_nsw(<2 x i64> %a, <2 x i64> %b) { ; ZVABD-LABEL: sabd_v2i64_nsw: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %sub = sub nsw <2 x i64> %a, %b %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) @@ -837,7 +857,9 @@ define <4 x i32> @smaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) { ; ZVABD-LABEL: smaxmin_v4i32: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %0, <4 x i32> %1) %b = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %0, <4 x i32> %1) @@ -858,7 +880,9 @@ define <2 x i64> @smaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) { ; ZVABD-LABEL: smaxmin_v2i64: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a = tail call <2 x i64> @llvm.smax.v2i64(<2 x i64> %0, <2 x i64> %1) %b = tail call <2 x i64> @llvm.smin.v2i64(<2 x i64> %0, <2 x i64> %1) @@ -921,7 +945,9 @@ define <4 x i32> @umaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) { ; ZVABD-LABEL: umaxmin_v4i32: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %0, <4 x i32> %1) %b = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %0, <4 x i32> %1) @@ -942,7 +968,9 @@ define <2 x i64> @umaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) { ; ZVABD-LABEL: umaxmin_v2i64: ; ZVABD: # %bb.0: ; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 ; ZVABD-NEXT: ret %a = tail call <2 x i64> @llvm.umax.v2i64(<2 x i64> %0, <2 x i64> %1) %b = tail call <2 x i64> @llvm.umin.v2i64(<2 x i64> %0, <2 x i64> %1)