From cb2cc626e77dba6d5c4b35e1770b3b33b55181e3 Mon Sep 17 00:00:00 2001 From: Ricardo Jesus Date: Mon, 4 Aug 2025 02:14:54 -0700 Subject: [PATCH 1/2] [AArch64] Drop poison flags when lowering absolute difference patterns. When lowering SELECT_CC nodes of absolute difference patterns, drop poison generating flags from the negated operand to avoid inadvertently propagating poison. --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 4f6e3ddd18def..c1cff5b8431a8 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -11398,13 +11398,18 @@ SDValue AArch64TargetLowering::LowerSELECT_CC( // select_cc lhs, rhs, sub(rhs, lhs), sub(lhs, rhs), cc -> // select_cc lhs, rhs, neg(sub(lhs, rhs)), sub(lhs, rhs), cc // The second forms can be matched into subs+cneg. + // NOTE: Drop poison generating flags from the negated operand to avoid + // inadvertently propagating poison after the canonicalisation. if (TVal.getOpcode() == ISD::SUB && FVal.getOpcode() == ISD::SUB) { if (TVal.getOperand(0) == LHS && TVal.getOperand(1) == RHS && - FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS) + FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS) { FVal = DAG.getNegative(TVal, DL, TVal.getValueType()); - else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS && - FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS) + TVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags); + } else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS && + FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS) { TVal = DAG.getNegative(FVal, DL, FVal.getValueType()); + FVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags); + } } unsigned Opcode = AArch64ISD::CSEL; From 08ec67a8b3fe57bc2381c322efa897c687464756 Mon Sep 17 00:00:00 2001 From: Ricardo Jesus Date: Tue, 5 Aug 2025 05:20:52 -0700 Subject: [PATCH 2/2] Drop flags first. --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index c1cff5b8431a8..e6c128e18d15c 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -11403,12 +11403,12 @@ SDValue AArch64TargetLowering::LowerSELECT_CC( if (TVal.getOpcode() == ISD::SUB && FVal.getOpcode() == ISD::SUB) { if (TVal.getOperand(0) == LHS && TVal.getOperand(1) == RHS && FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS) { - FVal = DAG.getNegative(TVal, DL, TVal.getValueType()); TVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags); + FVal = DAG.getNegative(TVal, DL, TVal.getValueType()); } else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS && FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS) { - TVal = DAG.getNegative(FVal, DL, FVal.getValueType()); FVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags); + TVal = DAG.getNegative(FVal, DL, FVal.getValueType()); } }