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[llvm-objcopy][libObject] Add RISC-V big-endian support #146913

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Merged
merged 7 commits into from
Jul 17, 2025
Merged

[llvm-objcopy][libObject] Add RISC-V big-endian support #146913

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a3b50d1
[llvm-objcopy][libObject] Add RISC-V big-endian support
djtodoro Jul 3, 2025
9f95a0c
Fixup: Remove Triple::riscv32/64be from isLittleEndian predicates
djtodoro Jul 4, 2025
5db9463
Apply clang-format
djtodoro Jul 4, 2025
688f560
Satisfy clang-format
djtodoro Jul 4, 2025
2f68ae4
Additional request from clang-format
djtodoro Jul 4, 2025
158b232
Follow existing format
djtodoro Jul 9, 2025
f988ae8
Revert "Follow existing format"
djtodoro Jul 15, 2025
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2 changes: 1 addition & 1 deletion clang/test/Driver/frame-pointer-elim.c
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Expand Up @@ -160,7 +160,7 @@
// RUN: FileCheck --check-prefix=KEEP-ALL %s
// RUN: %clang -### --target=riscv64-linux-android -O1 -S %s 2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s 2>&1 | \
// RUN: %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s 2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s

// On ARM backend bare metal targets, frame pointer is omitted
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8 changes: 4 additions & 4 deletions llvm/include/llvm/Object/ELFObjectFile.h
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Expand Up @@ -1312,7 +1312,7 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
case ELF::EM_PPC:
return (IsLittleEndian ? "elf32-powerpcle" : "elf32-powerpc");
case ELF::EM_RISCV:
return "elf32-littleriscv";
return (IsLittleEndian ? "elf32-littleriscv" : "elf32-bigriscv");
case ELF::EM_CSKY:
return "elf32-csky";
case ELF::EM_SPARC:
Expand All @@ -1338,7 +1338,7 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
case ELF::EM_PPC64:
return (IsLittleEndian ? "elf64-powerpcle" : "elf64-powerpc");
case ELF::EM_RISCV:
return "elf64-littleriscv";
return (IsLittleEndian ? "elf64-littleriscv" : "elf64-bigriscv");
case ELF::EM_S390:
return "elf64-s390";
case ELF::EM_SPARCV9:
Expand Down Expand Up @@ -1400,9 +1400,9 @@ template <class ELFT> Triple::ArchType ELFObjectFile<ELFT>::getArch() const {
case ELF::EM_RISCV:
switch (EF.getHeader().e_ident[ELF::EI_CLASS]) {
case ELF::ELFCLASS32:
return Triple::riscv32;
return IsLittleEndian ? Triple::riscv32 : Triple::riscv32be;
case ELF::ELFCLASS64:
return Triple::riscv64;
return IsLittleEndian ? Triple::riscv64 : Triple::riscv64be;
default:
report_fatal_error("Invalid ELFCLASS!");
}
Expand Down
122 changes: 64 additions & 58 deletions llvm/include/llvm/TargetParser/Triple.h
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Expand Up @@ -48,62 +48,64 @@ class Triple {
enum ArchType {
UnknownArch,

arm, // ARM (little endian): arm, armv.*, xscale
armeb, // ARM (big endian): armeb
aarch64, // AArch64 (little endian): aarch64
aarch64_be, // AArch64 (big endian): aarch64_be
aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
arc, // ARC: Synopsys ARC
avr, // AVR: Atmel AVR microcontroller
bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
csky, // CSKY: csky
dxil, // DXIL 32-bit DirectX bytecode
hexagon, // Hexagon: hexagon
loongarch32, // LoongArch (32-bit): loongarch32
loongarch64, // LoongArch (64-bit): loongarch64
m68k, // M68k: Motorola 680x0 family
mips, // MIPS: mips, mipsallegrex, mipsr6
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
msp430, // MSP430: msp430
ppc, // PPC: powerpc
ppcle, // PPCLE: powerpc (little endian)
ppc64, // PPC64: powerpc64, ppu
ppc64le, // PPC64LE: powerpc64le
r600, // R600: AMD GPUs HD2XXX - HD6XXX
amdgcn, // AMDGCN: AMD GCN GPUs
riscv32, // RISC-V (32-bit): riscv32
riscv64, // RISC-V (64-bit): riscv64
sparc, // Sparc: sparc
sparcv9, // Sparcv9: Sparcv9
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
systemz, // SystemZ: s390x
tce, // TCE (http://tce.cs.tut.fi/): tce
tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
thumb, // Thumb (little endian): thumb, thumbv.*
thumbeb, // Thumb (big endian): thumbeb
x86, // X86: i[3-9]86
x86_64, // X86-64: amd64, x86_64
xcore, // XCore: xcore
xtensa, // Tensilica: Xtensa
nvptx, // NVPTX: 32-bit
nvptx64, // NVPTX: 64-bit
amdil, // AMDIL
amdil64, // AMDIL with 64-bit pointers
hsail, // AMD HSAIL
hsail64, // AMD HSAIL with 64-bit pointers
spir, // SPIR: standard portable IR for OpenCL 32-bit version
spir64, // SPIR: standard portable IR for OpenCL 64-bit version
spirv, // SPIR-V with logical memory layout.
spirv32, // SPIR-V with 32-bit pointers
spirv64, // SPIR-V with 64-bit pointers
kalimba, // Kalimba: generic kalimba
shave, // SHAVE: Movidius vector VLIW processors
lanai, // Lanai: Lanai 32-bit
wasm32, // WebAssembly with 32-bit pointers
wasm64, // WebAssembly with 64-bit pointers
arm, // ARM (little endian): arm, armv.*, xscale
armeb, // ARM (big endian): armeb
aarch64, // AArch64 (little endian): aarch64
aarch64_be, // AArch64 (big endian): aarch64_be
aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
arc, // ARC: Synopsys ARC
avr, // AVR: Atmel AVR microcontroller
bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
csky, // CSKY: csky
dxil, // DXIL 32-bit DirectX bytecode
hexagon, // Hexagon: hexagon
loongarch32, // LoongArch (32-bit): loongarch32
loongarch64, // LoongArch (64-bit): loongarch64
m68k, // M68k: Motorola 680x0 family
mips, // MIPS: mips, mipsallegrex, mipsr6
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
msp430, // MSP430: msp430
ppc, // PPC: powerpc
ppcle, // PPCLE: powerpc (little endian)
ppc64, // PPC64: powerpc64, ppu
ppc64le, // PPC64LE: powerpc64le
r600, // R600: AMD GPUs HD2XXX - HD6XXX
amdgcn, // AMDGCN: AMD GCN GPUs
riscv32, // RISC-V (32-bit, little endian): riscv32
riscv64, // RISC-V (64-bit, little endian): riscv64
riscv32be, // RISC-V (32-bit, big endian): riscv32be
riscv64be, // RISC-V (64-bit, big endian): riscv64be
sparc, // Sparc: sparc
sparcv9, // Sparcv9: Sparcv9
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
systemz, // SystemZ: s390x
tce, // TCE (http://tce.cs.tut.fi/): tce
tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
thumb, // Thumb (little endian): thumb, thumbv.*
thumbeb, // Thumb (big endian): thumbeb
x86, // X86: i[3-9]86
x86_64, // X86-64: amd64, x86_64
xcore, // XCore: xcore
xtensa, // Tensilica: Xtensa
nvptx, // NVPTX: 32-bit
nvptx64, // NVPTX: 64-bit
amdil, // AMDIL
amdil64, // AMDIL with 64-bit pointers
hsail, // AMD HSAIL
hsail64, // AMD HSAIL with 64-bit pointers
spir, // SPIR: standard portable IR for OpenCL 32-bit version
spir64, // SPIR: standard portable IR for OpenCL 64-bit version
spirv, // SPIR-V with logical memory layout.
spirv32, // SPIR-V with 32-bit pointers
spirv64, // SPIR-V with 64-bit pointers
kalimba, // Kalimba: generic kalimba
shave, // SHAVE: Movidius vector VLIW processors
lanai, // Lanai: Lanai 32-bit
wasm32, // WebAssembly with 32-bit pointers
wasm64, // WebAssembly with 64-bit pointers
renderscript32, // 32-bit RenderScript
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Did clang-format do this? It's weird that the last 3 values in the enum have a different comment placement.

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Yes.. Without it, clang-format step fails.

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I am not sure what is the next step with this... (cc @topperc)

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I think, match what clang-format is doing, but also raise an issue or make an appropriate Discourse post to raise with the clang-format people.

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@jh7370 I agree.

renderscript64, // 64-bit RenderScript
ve, // NEC SX-Aurora Vector Engine
Expand Down Expand Up @@ -1069,10 +1071,14 @@ class Triple {
}

/// Tests whether the target is 32-bit RISC-V.
bool isRISCV32() const { return getArch() == Triple::riscv32; }
bool isRISCV32() const {
return getArch() == Triple::riscv32 || getArch() == Triple::riscv32be;
}

/// Tests whether the target is 64-bit RISC-V.
bool isRISCV64() const { return getArch() == Triple::riscv64; }
bool isRISCV64() const {
return getArch() == Triple::riscv64 || getArch() == Triple::riscv64be;
}

/// Tests whether the target is RISC-V (32- and 64-bit).
bool isRISCV() const { return isRISCV32() || isRISCV64(); }
Expand Down
6 changes: 5 additions & 1 deletion llvm/lib/Object/RelocationResolver.cpp
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Expand Up @@ -812,6 +812,7 @@ getRelocationResolver(const ObjectFile &Obj) {
case Triple::amdgcn:
return {supportsAmdgpu, resolveAmdgpu};
case Triple::riscv64:
case Triple::riscv64be:
return {supportsRISCV, resolveRISCV};
default:
if (isAMDGPU(Obj))
Expand Down Expand Up @@ -851,6 +852,7 @@ getRelocationResolver(const ObjectFile &Obj) {
case Triple::r600:
return {supportsAmdgpu, resolveAmdgpu};
case Triple::riscv32:
case Triple::riscv32be:
return {supportsRISCV, resolveRISCV};
case Triple::csky:
return {supportsCSKY, resolveCSKY};
Expand Down Expand Up @@ -897,7 +899,9 @@ uint64_t resolveRelocation(RelocationResolver Resolver, const RelocationRef &R,
if (Obj->getArch() != Triple::loongarch32 &&
Obj->getArch() != Triple::loongarch64 &&
Obj->getArch() != Triple::riscv32 &&
Obj->getArch() != Triple::riscv64)
Obj->getArch() != Triple::riscv64 &&
Obj->getArch() != Triple::riscv32be &&
Obj->getArch() != Triple::riscv64be)
LocData = 0;
}
}
Expand Down
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