diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 3751aac4df8ea..73686e176750c 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4781,7 +4781,7 @@ class TargetLowering : public TargetLoweringBase {
   virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
                               MachineFunction &/*MF*/, bool /*isVarArg*/,
                const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
-               LLVMContext &/*Context*/) const
+               LLVMContext &/*Context*/, const Type *RetTy) const
   {
     // Return true by default to get preexisting behavior.
     return true;
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index ec5b058da2971..5a314570c776a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1001,7 +1001,7 @@ bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
   GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
 
   bool CanLowerReturn = TLI.CanLowerReturn(
-      CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
+      CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext(), CLI.RetTy);
 
   // FIXME: sret demotion isn't supported yet - bail out.
   if (!CanLowerReturn)
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 1de336429fe10..3e89b18585f15 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -99,7 +99,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
   GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
                 mf.getDataLayout());
   CanLowerReturn =
-      TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
+      TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext(), Fn->getReturnType());
 
   // If this personality uses funclets, we need to do a bit more work.
   DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index f8d7c3ef7bbe7..ae3e2020cca34 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -11008,7 +11008,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
 
   bool CanLowerReturn =
       this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
-                           CLI.IsVarArg, Outs, CLI.RetTy->getContext());
+                           CLI.IsVarArg, Outs, CLI.RetTy->getContext(), CLI.RetTy);
 
   SDValue DemoteStackSlot;
   int DemoteStackIdx = -100;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a6f8f47f31fa5..22b446ee1d30a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9632,7 +9632,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
 
 bool AArch64TargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   CCAssignFn *RetCC = CCAssignFnForReturn(CallConv);
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 1b7f328fa729a..3c6cca24bbb68 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1102,7 +1102,7 @@ class AArch64TargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 58b061f5c1af0..82cbabce8925a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3146,7 +3146,8 @@ SDValue SITargetLowering::LowerFormalArguments(
 // possible in registers before passing on stack.
 bool SITargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   // Replacing returns with sret/stack usage doesn't make sense for shaders.
   // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
   // for shaders. Vector types should be explicitly handled by CC.
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 631f26542bbe6..5a4ac26197f7e 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -388,7 +388,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv,
                       MachineFunction &MF, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp
index 5ab27681361db..b133e4e5299a5 100644
--- a/llvm/lib/Target/ARC/ARCISelLowering.cpp
+++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp
@@ -630,7 +630,8 @@ SDValue ARCTargetLowering::LowerCallArguments(
 
 bool ARCTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
   if (!CCInfo.CheckReturn(Outs, RetCC_ARC))
diff --git a/llvm/lib/Target/ARC/ARCISelLowering.h b/llvm/lib/Target/ARC/ARCISelLowering.h
index e070ed8752cce..716a72455e827 100644
--- a/llvm/lib/Target/ARC/ARCISelLowering.h
+++ b/llvm/lib/Target/ARC/ARCISelLowering.h
@@ -112,7 +112,7 @@ class ARCTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 };
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 5ec2d8389c18e..4970946d03961 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -3239,7 +3239,7 @@ bool
 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
                                   MachineFunction &MF, bool isVarArg,
                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
-                                  LLVMContext &Context) const {
+                                  LLVMContext &Context, const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 3c1a414af8597..9fad056edd3f1 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -965,7 +965,7 @@ class VectorType;
     bool CanLowerReturn(CallingConv::ID CallConv,
                         MachineFunction &MF, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
-                        LLVMContext &Context) const override;
+                        LLVMContext &Context, const Type *RetTy) const override;
 
     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 07c79f6f227b0..c73ff83d29789 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1670,7 +1670,8 @@ SDValue AVRTargetLowering::LowerCallResult(
 
 bool AVRTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   if (CallConv == CallingConv::AVR_BUILTIN) {
     SmallVector<CCValAssign, 16> RVLocs;
     CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h
index f605795934532..cd45444e2bc3a 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -172,7 +172,7 @@ class AVRTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index c3fc9f9ead5eb..4cea262d40a37 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -426,7 +426,8 @@ SDValue CSKYTargetLowering::LowerFormalArguments(
 
 bool CSKYTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> CSKYLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context);
   return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.h b/llvm/lib/Target/CSKY/CSKYISelLowering.h
index d59481af3c5ba..0accfcad1879f 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.h
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.h
@@ -61,7 +61,7 @@ class CSKYTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 900a9054fc2c3..654298e082df1 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -182,7 +182,7 @@ bool
 HexagonTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
     const SmallVectorImpl<ISD::OutputArg> &Outs,
-    LLVMContext &Context) const {
+    LLVMContext &Context, const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 3fd961f5a7462..aaa9c65c1e07e 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -249,7 +249,7 @@ class HexagonTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv,
                       MachineFunction &MF, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index da55b7b8c6d68..e0792b36ce4d8 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -527,7 +527,8 @@ SDValue LanaiTargetLowering::LowerCCCArguments(
 
 bool LanaiTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.h b/llvm/lib/Target/Lanai/LanaiISelLowering.h
index 5fa5444b51618..ebec2525b93cd 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.h
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.h
@@ -93,7 +93,7 @@ class LanaiTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   Register getRegisterByName(const char *RegName, LLT VT,
                              const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 7f67def73ca2b..d9ae3a632d29e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -5668,7 +5668,8 @@ LoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,
 
 bool LoongArchTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index e619cb69f3332..e1bab9ebdd3f0 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -183,7 +183,7 @@ class LoongArchTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 4297325cf0e64..39b307b28889c 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -1060,7 +1060,8 @@ SDValue M68kTargetLowering::LowerFormalArguments(
 
 bool M68kTargetLowering::CanLowerReturn(
     CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, RetCC_M68k);
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h
index d00907775f928..e01f333316db6 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.h
+++ b/llvm/lib/Target/M68k/M68kISelLowering.h
@@ -271,7 +271,7 @@ class M68kTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   /// Lower the result values of a call into the
   /// appropriate copies out of appropriate physical registers.
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 31b793e9c0f2f..28d782543b330 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -723,7 +723,8 @@ MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
                                      MachineFunction &MF,
                                      bool IsVarArg,
                                      const SmallVectorImpl<ISD::OutputArg> &Outs,
-                                     LLVMContext &Context) const {
+                                     LLVMContext &Context,
+                                     const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, RetCC_MSP430);
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.h b/llvm/lib/Target/MSP430/MSP430ISelLowering.h
index 667ad60338619..d1263e453dda1 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.h
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.h
@@ -171,7 +171,7 @@ namespace llvm {
                         MachineFunction &MF,
                         bool IsVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
-                        LLVMContext &Context) const override;
+                        LLVMContext &Context, const Type *RetTy) const override;
 
     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/Mips/MipsCCState.cpp b/llvm/lib/Target/Mips/MipsCCState.cpp
index 76acfa97c3b41..781bb7c8c7e6d 100644
--- a/llvm/lib/Target/Mips/MipsCCState.cpp
+++ b/llvm/lib/Target/Mips/MipsCCState.cpp
@@ -95,14 +95,13 @@ void MipsCCState::PreAnalyzeCallResultForF128(
 
 /// Identify lowered values that originated from f128 or float arguments and
 /// record this for use by RetCC_MipsN.
-void MipsCCState::PreAnalyzeReturnForF128(
-    const SmallVectorImpl<ISD::OutputArg> &Outs) {
-  const MachineFunction &MF = getMachineFunction();
+void MipsCCState::PreAnalyzeCallReturnForF128(
+    const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy) {
   for (unsigned i = 0; i < Outs.size(); ++i) {
     OriginalArgWasF128.push_back(
-        originalTypeIsF128(MF.getFunction().getReturnType(), nullptr));
+        originalTypeIsF128(RetTy, nullptr));
     OriginalArgWasFloat.push_back(
-        MF.getFunction().getReturnType()->isFloatingPointTy());
+        RetTy->isFloatingPointTy());
   }
 }
 
diff --git a/llvm/lib/Target/Mips/MipsCCState.h b/llvm/lib/Target/Mips/MipsCCState.h
index bbb5225d5f678..4229da564630d 100644
--- a/llvm/lib/Target/Mips/MipsCCState.h
+++ b/llvm/lib/Target/Mips/MipsCCState.h
@@ -49,7 +49,7 @@ class MipsCCState : public CCState {
 
   /// Identify lowered values that originated from f128 arguments and record
   /// this for use by RetCC_MipsN.
-  void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
+  void PreAnalyzeCallReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy);
 
   /// Identify lowered values that originated from f128 arguments and record
   /// this.
@@ -167,10 +167,11 @@ class MipsCCState : public CCState {
 
   void PreAnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
                         CCAssignFn Fn) {
+    const MachineFunction &MF = getMachineFunction();
     OriginalArgWasFloat.clear();
     OriginalArgWasF128.clear();
     OriginalArgWasFloatVector.clear();
-    PreAnalyzeReturnForF128(Outs);
+    PreAnalyzeCallReturnForF128(Outs, MF.getFunction().getReturnType());
     PreAnalyzeReturnForVectorFloat(Outs);
   }
 
@@ -182,7 +183,8 @@ class MipsCCState : public CCState {
 
   bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
                    CCAssignFn Fn) {
-    PreAnalyzeReturnForF128(ArgsFlags);
+    const MachineFunction &MF = getMachineFunction();
+    PreAnalyzeCallReturnForF128(ArgsFlags, MF.getFunction().getReturnType());
     PreAnalyzeReturnForVectorFloat(ArgsFlags);
     bool Return = CCState::CheckReturn(ArgsFlags, Fn);
     OriginalArgWasFloat.clear();
@@ -191,6 +193,16 @@ class MipsCCState : public CCState {
     return Return;
   }
 
+  bool CheckCallReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
+                   CCAssignFn Fn, const Type *RetTy) {
+    PreAnalyzeCallReturnForF128(ArgsFlags, RetTy);
+    PreAnalyzeReturnForVectorFloat(ArgsFlags);
+    bool Return = CCState::CheckReturn(ArgsFlags, Fn);
+    OriginalArgWasFloat.clear();
+    OriginalArgWasF128.clear();
+    OriginalArgWasFloatVector.clear();
+    return Return;
+  }
   bool WasOriginalArgF128(unsigned ValNo) { return OriginalArgWasF128[ValNo]; }
   bool WasOriginalArgFloat(unsigned ValNo) {
       return OriginalArgWasFloat[ValNo];
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d5f38c414e703..30b2ea1f4798d 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3864,10 +3864,10 @@ bool
 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
                                    MachineFunction &MF, bool IsVarArg,
                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
-                                   LLVMContext &Context) const {
+                                   LLVMContext &Context, const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
-  return CCInfo.CheckReturn(Outs, RetCC_Mips);
+  return CCInfo.CheckCallReturn(Outs, RetCC_Mips, RetTy);
 }
 
 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(Type *Ty,
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 655a347679ad7..ff4d089d6a49a 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -615,7 +615,7 @@ class TargetRegisterClass;
     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
-                        LLVMContext &Context) const override;
+                        LLVMContext &Context, const Type *RetTy) const override;
 
     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 691107abf3e89..4ca328bd9a9ba 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -7868,7 +7868,8 @@ bool
 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
                                   MachineFunction &MF, bool isVarArg,
                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
-                                  LLVMContext &Context) const {
+                                  LLVMContext &Context,
+                                  const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 5d692e3fcae92..cc01cab7a2089 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1373,7 +1373,7 @@ namespace llvm {
     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
-                        LLVMContext &Context) const override;
+                        LLVMContext &Context, const Type *RetTy) const override;
 
     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cda64ae5f498d..8f544049ae4a1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20361,7 +20361,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
 
 bool RISCVTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index ea077c7d2d23a..74f9bea3fd754 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -762,7 +762,7 @@ class RISCVTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 03a74b6254300..d0cd38cf72363 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -234,7 +234,8 @@ static unsigned toCallerWindow(unsigned Reg) {
 
 bool SparcTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h
index cc672074a4be8..1bee5f4cfe84d 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.h
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.h
@@ -153,7 +153,7 @@ namespace llvm {
     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
-                        LLVMContext &Context) const override;
+                        LLVMContext &Context, const Type *RetTy) const override;
 
     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index d664b4a41fce7..e3dfab962f55f 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2412,7 +2412,8 @@ bool SystemZTargetLowering::
 CanLowerReturn(CallingConv::ID CallConv,
                MachineFunction &MF, bool isVarArg,
                const SmallVectorImpl<ISD::OutputArg> &Outs,
-               LLVMContext &Context) const {
+               LLVMContext &Context,
+               const Type *RetTy) const {
   // Special case that we cannot easily detect in RetCC_SystemZ since
   // i128 may not be a legal type.
   for (auto &Out : Outs)
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index d663e4abfb4e3..afd3d0d989a22 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -620,7 +620,8 @@ class SystemZTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context,
+                      const Type *RetTy) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 87c1625c11454..aff058868f306 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -65,7 +65,8 @@ CCAssignFn *getParamCC(CallingConv::ID CallConv, bool IsVarArg) {
 
 bool VETargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   CCAssignFn *RetCC = getReturnCC(CallConv);
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h
index 8b9412d786625..04274b14baa1f 100644
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -191,7 +191,8 @@ class VETargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context,
+                      const Type *RetTy) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 084aed6eed46d..02db1b142a22b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1429,7 +1429,8 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
 bool WebAssemblyTargetLowering::CanLowerReturn(
     CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
     const SmallVectorImpl<ISD::OutputArg> &Outs,
-    LLVMContext & /*Context*/) const {
+    LLVMContext & /*Context*/,
+    const Type *RetTy) const {
   // WebAssembly can only handle returning tuples with multivalue enabled
   return WebAssembly::canLowerReturn(Outs.size(), Subtarget);
 }
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
index 454432728ca87..d9ced1a1a5279 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
@@ -87,7 +87,8 @@ class WebAssemblyTargetLowering final : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context,
+                      const Type *RetTy) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 2b7a8eaf249d8..7a48c778820f1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1799,7 +1799,8 @@ namespace llvm {
     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
-                        LLVMContext &Context) const override;
+                        LLVMContext &Context,
+                        const Type *RetTy) const override;
 
     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
     ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index b1c1ab4aa855d..10aa2a5e5dac8 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -659,7 +659,8 @@ X86TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
 
 bool X86TargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, RetCC_X86);
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 9a9acaca3188e..ac199230b2c07 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -1325,7 +1325,7 @@ bool XCoreTargetLowering::
 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                bool isVarArg,
                const SmallVectorImpl<ISD::OutputArg> &Outs,
-               LLVMContext &Context) const {
+               LLVMContext &Context, const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
   if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h
index eaa36d40cba92..1e036ea316978 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.h
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.h
@@ -217,7 +217,7 @@ namespace llvm {
     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
-                        LLVMContext &Context) const override;
+                        LLVMContext &Context, const Type *RetTy) const override;
   };
 }
 
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index e8ede330bbac5..cdf38a0669479 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -621,7 +621,8 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI,
 
 bool XtensaTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
-    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
+    const Type *RetTy) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, RetCC_Xtensa);
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index cebd7d2016c8e..a959299d8ca6a 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -105,7 +105,7 @@ class XtensaTargetLowering : public TargetLowering {
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
+                      LLVMContext &Context, const Type *RetTy) const override;
 
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index ac29154579c50..04bed7d42bf96 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -2903,6 +2903,242 @@ entry:
   %cond = select i1 %cmp, fp128 %c, fp128 %d
   ret fp128 %cond
 }
+
+define { i8, i128 } @bar_structure_without_fp128() nounwind {
+; C_CC_FMT-LABEL: bar_structure_without_fp128:
+; C_CC_FMT:       # %bb.0: # %entry
+; C_CC_FMT-NEXT:    sd $zero, 24($4)
+; C_CC_FMT-NEXT:    sd $zero, 16($4)
+; C_CC_FMT-NEXT:    sb $zero, 0($4)
+; C_CC_FMT-NEXT:    jr $ra
+; C_CC_FMT-NEXT:    nop
+;
+; CMP_CC_FMT-LABEL: bar_structure_without_fp128:
+; CMP_CC_FMT:       # %bb.0: # %entry
+; CMP_CC_FMT-NEXT:    sd $zero, 24($4)
+; CMP_CC_FMT-NEXT:    sd $zero, 16($4)
+; CMP_CC_FMT-NEXT:    sb $zero, 0($4)
+; CMP_CC_FMT-NEXT:    jrc $ra
+entry:
+  ret { i8, i128 } zeroinitializer
+}
+
+define fp128 @call_structure_without_fp128() nounwind {
+; C_CC_FMT-LABEL: call_structure_without_fp128:
+; C_CC_FMT:       # %bb.0: # %entry
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, -48
+; C_CC_FMT-NEXT:    sd $ra, 40($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    sd $gp, 32($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(call_structure_without_fp128)))
+; C_CC_FMT-NEXT:    daddu $1, $1, $25
+; C_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_structure_without_fp128)))
+; C_CC_FMT-NEXT:    daddiu $4, $sp, 0
+; C_CC_FMT-NEXT:    ld $25, %call16(bar_structure_without_fp128)($gp)
+; C_CC_FMT-NEXT:    .reloc .Ltmp51, R_MIPS_JALR, bar_structure_without_fp128
+; C_CC_FMT-NEXT:  .Ltmp51:
+; C_CC_FMT-NEXT:    jalr $25
+; C_CC_FMT-NEXT:    nop
+; C_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; C_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; C_CC_FMT-NEXT:    ld $gp, 32($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    ld $ra, 40($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, 48
+; C_CC_FMT-NEXT:    jr $ra
+; C_CC_FMT-NEXT:    nop
+;
+; CMP_CC_FMT-LABEL: call_structure_without_fp128:
+; CMP_CC_FMT:       # %bb.0: # %entry
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, -48
+; CMP_CC_FMT-NEXT:    sd $ra, 40($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    sd $gp, 32($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(call_structure_without_fp128)))
+; CMP_CC_FMT-NEXT:    daddu $1, $1, $25
+; CMP_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_structure_without_fp128)))
+; CMP_CC_FMT-NEXT:    daddiu $4, $sp, 0
+; CMP_CC_FMT-NEXT:    ld $25, %call16(bar_structure_without_fp128)($gp)
+; CMP_CC_FMT-NEXT:    .reloc .Ltmp51, R_MIPS_JALR, bar_structure_without_fp128
+; CMP_CC_FMT-NEXT:  .Ltmp51:
+; CMP_CC_FMT-NEXT:    jalrc $25
+; CMP_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; CMP_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT:    ld $gp, 32($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    ld $ra, 40($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, 48
+; CMP_CC_FMT-NEXT:    jrc $ra
+entry:
+  call { i8, i128 } @bar_structure_without_fp128()
+  ret fp128 0xL00000000000000000000000000000000
+}
+
+define { fp128 } @bar_structure_fp128() nounwind {
+; C_CC_FMT-LABEL: bar_structure_fp128:
+; C_CC_FMT:       # %bb.0: # %entry
+; C_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; C_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; C_CC_FMT-NEXT:    jr $ra
+; C_CC_FMT-NEXT:    nop
+;
+; CMP_CC_FMT-LABEL: bar_structure_fp128:
+; CMP_CC_FMT:       # %bb.0: # %entry
+; CMP_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; CMP_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT:    jrc $ra
+entry:
+  ret { fp128 } zeroinitializer
+}
+
+define fp128 @tail_call_structure_fp128() nounwind {
+; C_CC_FMT-LABEL: tail_call_structure_fp128:
+; C_CC_FMT:       # %bb.0: # %entry
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, -16
+; C_CC_FMT-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(tail_call_structure_fp128)))
+; C_CC_FMT-NEXT:    daddu $1, $1, $25
+; C_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(tail_call_structure_fp128)))
+; C_CC_FMT-NEXT:    ld $25, %call16(bar_structure_fp128)($gp)
+; C_CC_FMT-NEXT:    .reloc .Ltmp52, R_MIPS_JALR, bar_structure_fp128
+; C_CC_FMT-NEXT:  .Ltmp52:
+; C_CC_FMT-NEXT:    jalr $25
+; C_CC_FMT-NEXT:    nop
+; C_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; C_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; C_CC_FMT-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, 16
+; C_CC_FMT-NEXT:    jr $ra
+; C_CC_FMT-NEXT:    nop
+;
+; CMP_CC_FMT-LABEL: tail_call_structure_fp128:
+; CMP_CC_FMT:       # %bb.0: # %entry
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, -16
+; CMP_CC_FMT-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(tail_call_structure_fp128)))
+; CMP_CC_FMT-NEXT:    daddu $1, $1, $25
+; CMP_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(tail_call_structure_fp128)))
+; CMP_CC_FMT-NEXT:    ld $25, %call16(bar_structure_fp128)($gp)
+; CMP_CC_FMT-NEXT:    .reloc .Ltmp52, R_MIPS_JALR, bar_structure_fp128
+; CMP_CC_FMT-NEXT:  .Ltmp52:
+; CMP_CC_FMT-NEXT:    jalrc $25
+; CMP_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; CMP_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, 16
+; CMP_CC_FMT-NEXT:    jrc $ra
+entry:
+  %call = tail call fp128 @bar_structure_fp128()
+  ret fp128 0xL00000000000000000000000000000000
+}
+
+define fp128 @bar_fp128() nounwind {
+; C_CC_FMT-LABEL: bar_fp128:
+; C_CC_FMT:       # %bb.0: # %entry
+; C_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; C_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; C_CC_FMT-NEXT:    jr $ra
+; C_CC_FMT-NEXT:    nop
+;
+; CMP_CC_FMT-LABEL: bar_fp128:
+; CMP_CC_FMT:       # %bb.0: # %entry
+; CMP_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; CMP_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT:    jrc $ra
+entry:
+  ret fp128 zeroinitializer
+}
+
+define fp128 @call_fp128() nounwind {
+; C_CC_FMT-LABEL: call_fp128:
+; C_CC_FMT:       # %bb.0: # %entry
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, -16
+; C_CC_FMT-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(call_fp128)))
+; C_CC_FMT-NEXT:    daddu $1, $1, $25
+; C_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_fp128)))
+; C_CC_FMT-NEXT:    ld $25, %call16(bar_fp128)($gp)
+; C_CC_FMT-NEXT:    .reloc .Ltmp53, R_MIPS_JALR, bar_fp128
+; C_CC_FMT-NEXT:  .Ltmp53:
+; C_CC_FMT-NEXT:    jalr $25
+; C_CC_FMT-NEXT:    nop
+; C_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; C_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; C_CC_FMT-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, 16
+; C_CC_FMT-NEXT:    jr $ra
+; C_CC_FMT-NEXT:    nop
+;
+; CMP_CC_FMT-LABEL: call_fp128:
+; CMP_CC_FMT:       # %bb.0: # %entry
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, -16
+; CMP_CC_FMT-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(call_fp128)))
+; CMP_CC_FMT-NEXT:    daddu $1, $1, $25
+; CMP_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_fp128)))
+; CMP_CC_FMT-NEXT:    ld $25, %call16(bar_fp128)($gp)
+; CMP_CC_FMT-NEXT:    .reloc .Ltmp53, R_MIPS_JALR, bar_fp128
+; CMP_CC_FMT-NEXT:  .Ltmp53:
+; CMP_CC_FMT-NEXT:    jalrc $25
+; CMP_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; CMP_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, 16
+; CMP_CC_FMT-NEXT:    jrc $ra
+entry:
+  call fp128 @bar_fp128()
+  ret fp128 0xL00000000000000000000000000000000
+}
+
+define fp128 @call_structure_fp128() nounwind {
+; C_CC_FMT-LABEL: call_structure_fp128:
+; C_CC_FMT:       # %bb.0: # %entry
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, -16
+; C_CC_FMT-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
+; C_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(call_structure_fp128)))
+; C_CC_FMT-NEXT:    daddu $1, $1, $25
+; C_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_structure_fp128)))
+; C_CC_FMT-NEXT:    ld $25, %call16(bar_structure_fp128)($gp)
+; C_CC_FMT-NEXT:    .reloc .Ltmp54, R_MIPS_JALR, bar_structure_fp128
+; C_CC_FMT-NEXT:  .Ltmp54:
+; C_CC_FMT-NEXT:    jalr $25
+; C_CC_FMT-NEXT:    nop
+; C_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; C_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; C_CC_FMT-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; C_CC_FMT-NEXT:    daddiu $sp, $sp, 16
+; C_CC_FMT-NEXT:    jr $ra
+; C_CC_FMT-NEXT:    nop
+;
+; CMP_CC_FMT-LABEL: call_structure_fp128:
+; CMP_CC_FMT:       # %bb.0: # %entry
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, -16
+; CMP_CC_FMT-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
+; CMP_CC_FMT-NEXT:    lui $1, %hi(%neg(%gp_rel(call_structure_fp128)))
+; CMP_CC_FMT-NEXT:    daddu $1, $1, $25
+; CMP_CC_FMT-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_structure_fp128)))
+; CMP_CC_FMT-NEXT:    ld $25, %call16(bar_structure_fp128)($gp)
+; CMP_CC_FMT-NEXT:    .reloc .Ltmp54, R_MIPS_JALR, bar_structure_fp128
+; CMP_CC_FMT-NEXT:  .Ltmp54:
+; CMP_CC_FMT-NEXT:    jalrc $25
+; CMP_CC_FMT-NEXT:    daddiu $2, $zero, 0
+; CMP_CC_FMT-NEXT:    daddiu $4, $zero, 0
+; CMP_CC_FMT-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; CMP_CC_FMT-NEXT:    daddiu $sp, $sp, 16
+; CMP_CC_FMT-NEXT:    jrc $ra
+entry:
+  call { fp128 } @bar_structure_fp128()
+  ret fp128 0xL00000000000000000000000000000000
+}
+
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; ALL: {{.*}}
 ; PRER6: {{.*}}