[AMDGPU] Assertion `(!LeaveBefore || Idx <= LeaveBefore) && "Interference"' failed

[jayfoad]

With this test case I get:

llc -x mir zz.txt -start-after unreachable-mbb-elimination
llc: /home/jayfoad2/git/llvm-project/llvm/lib/CodeGen/SplitKit.cpp:1661: void llvm::SplitEditor::splitLiveThroughBlock(unsigned int, unsigned int, llvm::SlotIndex, unsigned int, llvm::SlotIndex): Assertion `(!LeaveBefore || Idx <= LeaveBefore) && "Interference"' failed.

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

Author: Jay Foad (jayfoad)

With [this test case](https://github.com/user-attachments/files/17061455/zz.txt) I get: ``` llc -x mir zz.txt -start-after unreachable-mbb-elimination llc: /home/jayfoad2/git/llvm-project/llvm/lib/CodeGen/SplitKit.cpp:1661: void llvm::SplitEditor::splitLiveThroughBlock(unsigned int, unsigned int, llvm::SlotIndex, unsigned int, llvm::SlotIndex): Assertion `(!LeaveBefore || Idx <= LeaveBefore) && "Interference"' failed. ```

[jayfoad]

The same assertion failed in #87721.

[jayfoad]

I tried reducing the MIR with llvm-reduce without success.

I tried running with -verify-regalloc but it failed like this, which I suspect is unrelated:

*** Bad machine code: Operand has incorrect register class. ***
- function:    test
- basic block: %bb.146  (0x60b5c40) [29456B;29808B)
- instruction: 29640B	SI_SPILL_V128_SAVE %8155:vreg_128, %stack.0, $sp_reg, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5)

*** Bad machine code: Illegal physical register for instruction ***
- function:    test
- basic block: %bb.146  (0x60b5c40) [29456B;29808B)
- instruction: 29640B	SI_SPILL_V128_SAVE %8155:vreg_128, %stack.0, $sp_reg, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5)
- operand 2:   $sp_reg
$sp_reg is not a SReg_32 register.

[arsenm]

I tried reducing the MIR with llvm-reduce without success.

I tried running with -verify-regalloc but it failed like this, which I suspect is unrelated:

*** Bad machine code: Operand has incorrect register class. ***
- function:    test
- basic block: %bb.146  (0x60b5c40) [29456B;29808B)
- instruction: 29640B	SI_SPILL_V128_SAVE %8155:vreg_128, %stack.0, $sp_reg, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5)

*** Bad machine code: Illegal physical register for instruction ***
- function:    test
- basic block: %bb.146  (0x60b5c40) [29456B;29808B)
- instruction: 29640B	SI_SPILL_V128_SAVE %8155:vreg_128, %stack.0, $sp_reg, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5)
- operand 2:   $sp_reg
$sp_reg is not a SReg_32 register.

Yes, this is just a register definition issue (and we should probably just get rid of the sp_reg pseudo register at this point)

[arsenm]

I can take a stab at reducing the MIR, I still have a number of patches that never made it upstream. I forgot that I never pushed the block reduction for instance

[arsenm]

$sp_reg is not a SReg_32 register.

Yes, this is just a register definition issue (and we should probably just get rid of the sp_reg pseudo register at this point)

The problem here is also avoidable, too much of the machineFunctionInfo was deleted. Needs to set sp_reg to the real value

[jayfoad]

The problem here is also avoidable, too much of the machineFunctionInfo was deleted. Needs to set sp_reg to the real value

Thanks. I should not have deleted the definition of stackPtrOffsetReg. Updated test case: zz.txt

[arsenm]

I've made some progress reducing this, but this is a tough one. It's another case where it depends on the exact slot indexes matter, so you have to run multiple passes to avoid the fresh LiveIntervals

[arsenm]

Still really big issue109294.mir.zip

[arsenm]

I think this is so sensitive because the SIMachineFunctionFields used for WWM spilling are still not serialized. We're losing reserved registers by resuming the compile