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[DAGCombiner] Handle constant threshold
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3 files changed

+54
-68
lines changed

3 files changed

+54
-68
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13418,6 +13418,24 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
1341813418
}
1341913419
}
1342013420
}
13421+
13422+
// (vselect (ugt x, C), (add x, ~C), x) -> (umin (add x, ~C), x)
13423+
// (vselect (ult x, C), x, (add x, -C)) -> (umin x, (add x, -C))
13424+
APInt C;
13425+
if (sd_match(RHS, m_ConstInt(C)) && hasUMin(VT)) {
13426+
if (CC == ISD::SETUGT && LHS == N2 &&
13427+
sd_match(N1, m_Add(m_Specific(N2), m_SpecificInt(~C)))) {
13428+
SDValue AddC = DAG.getConstant(~C, DL, VT);
13429+
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N2, AddC);
13430+
return DAG.getNode(ISD::UMIN, DL, VT, Add, N2);
13431+
}
13432+
if (CC == ISD::SETULT && LHS == N1 &&
13433+
sd_match(N2, m_Add(m_Specific(N1), m_SpecificInt(-C)))) {
13434+
SDValue AddC = DAG.getConstant(-C, DL, VT);
13435+
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, AddC);
13436+
return DAG.getNode(ISD::UMIN, DL, VT, N1, Add);
13437+
}
13438+
}
1342113439
}
1342213440

1342313441
if (SimplifySelectOps(N, N1, N2))

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll‎

Lines changed: 18 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -5815,9 +5815,9 @@ define <2 x i64> @vsub_if_uge_swapped_v2i64(<2 x i64> %va, <2 x i64> %vb) {
58155815
define <8 x i8> @sub_if_uge_C_v8i8(<8 x i8> %x) {
58165816
; CHECK-LABEL: sub_if_uge_C_v8i8:
58175817
; CHECK: # %bb.0:
5818-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
5819-
; CHECK-NEXT: vmsgtu.vi v0, v8, 12
5820-
; CHECK-NEXT: vadd.vi v8, v8, -13, v0.t
5818+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
5819+
; CHECK-NEXT: vadd.vi v9, v8, -13
5820+
; CHECK-NEXT: vminu.vv v8, v9, v8
58215821
; CHECK-NEXT: ret
58225822
%cmp = icmp ugt <8 x i8> %x, splat (i8 12)
58235823
%sub = add <8 x i8> %x, splat (i8 -13)
@@ -5828,11 +5828,10 @@ define <8 x i8> @sub_if_uge_C_v8i8(<8 x i8> %x) {
58285828
define <8 x i16> @sub_if_uge_C_v8i16(<8 x i16> %x) {
58295829
; CHECK-LABEL: sub_if_uge_C_v8i16:
58305830
; CHECK: # %bb.0:
5831-
; CHECK-NEXT: li a0, 2000
5832-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
5833-
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
58345831
; CHECK-NEXT: li a0, -2001
5835-
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
5832+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5833+
; CHECK-NEXT: vadd.vx v9, v8, a0
5834+
; CHECK-NEXT: vminu.vv v8, v9, v8
58365835
; CHECK-NEXT: ret
58375836
%cmp = icmp ugt <8 x i16> %x, splat (i16 2000)
58385837
%sub = add <8 x i16> %x, splat (i16 -2001)
@@ -5843,13 +5842,11 @@ define <8 x i16> @sub_if_uge_C_v8i16(<8 x i16> %x) {
58435842
define <4 x i32> @sub_if_uge_C_v4i32(<4 x i32> %x) {
58445843
; CHECK-LABEL: sub_if_uge_C_v4i32:
58455844
; CHECK: # %bb.0:
5846-
; CHECK-NEXT: lui a0, 16
5847-
; CHECK-NEXT: addi a0, a0, -16
5848-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
5849-
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
58505845
; CHECK-NEXT: lui a0, 1048560
58515846
; CHECK-NEXT: addi a0, a0, 15
5852-
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
5847+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5848+
; CHECK-NEXT: vadd.vx v9, v8, a0
5849+
; CHECK-NEXT: vminu.vv v8, v9, v8
58535850
; CHECK-NEXT: ret
58545851
%cmp = icmp ugt <4 x i32> %x, splat (i32 65520)
58555852
%sub = add <4 x i32> %x, splat (i32 -65521)
@@ -5860,14 +5857,11 @@ define <4 x i32> @sub_if_uge_C_v4i32(<4 x i32> %x) {
58605857
define <4 x i32> @sub_if_uge_C_swapped_v4i32(<4 x i32> %x) {
58615858
; CHECK-LABEL: sub_if_uge_C_swapped_v4i32:
58625859
; CHECK: # %bb.0:
5863-
; CHECK-NEXT: lui a0, 16
5864-
; CHECK-NEXT: addi a0, a0, -15
5865-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5866-
; CHECK-NEXT: vmsltu.vx v0, v8, a0
58675860
; CHECK-NEXT: lui a0, 1048560
58685861
; CHECK-NEXT: addi a0, a0, 15
5862+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
58695863
; CHECK-NEXT: vadd.vx v9, v8, a0
5870-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5864+
; CHECK-NEXT: vminu.vv v8, v8, v9
58715865
; CHECK-NEXT: ret
58725866
%cmp = icmp ult <4 x i32> %x, splat (i32 65521)
58735867
%sub = add <4 x i32> %x, splat (i32 -65521)
@@ -5879,38 +5873,28 @@ define <2 x i64> @sub_if_uge_C_v2i64(<2 x i64> %x) nounwind {
58795873
; RV32-LABEL: sub_if_uge_C_v2i64:
58805874
; RV32: # %bb.0:
58815875
; RV32-NEXT: addi sp, sp, -16
5882-
; RV32-NEXT: li a0, 1
5883-
; RV32-NEXT: lui a1, 172127
5884-
; RV32-NEXT: mv a2, sp
5885-
; RV32-NEXT: addi a1, a1, 512
5886-
; RV32-NEXT: sw a1, 0(sp)
5887-
; RV32-NEXT: sw a0, 4(sp)
58885876
; RV32-NEXT: li a0, -2
5889-
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
5890-
; RV32-NEXT: vlse64.v v9, (a2), zero
58915877
; RV32-NEXT: lui a1, 876449
58925878
; RV32-NEXT: addi a1, a1, -513
58935879
; RV32-NEXT: sw a1, 8(sp)
58945880
; RV32-NEXT: sw a0, 12(sp)
58955881
; RV32-NEXT: addi a0, sp, 8
5896-
; RV32-NEXT: vlse64.v v10, (a0), zero
5897-
; RV32-NEXT: vmsltu.vv v0, v9, v8
5898-
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
5882+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5883+
; RV32-NEXT: vlse64.v v9, (a0), zero
5884+
; RV32-NEXT: vadd.vv v9, v8, v9
5885+
; RV32-NEXT: vminu.vv v8, v9, v8
58995886
; RV32-NEXT: addi sp, sp, 16
59005887
; RV32-NEXT: ret
59015888
;
59025889
; RV64-LABEL: sub_if_uge_C_v2i64:
59035890
; RV64: # %bb.0:
5904-
; RV64-NEXT: lui a0, 2384
5905-
; RV64-NEXT: addi a0, a0, 761
5906-
; RV64-NEXT: slli a0, a0, 9
5907-
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
5908-
; RV64-NEXT: vmsgtu.vx v0, v8, a0
59095891
; RV64-NEXT: lui a0, 1048278
59105892
; RV64-NEXT: addi a0, a0, -95
59115893
; RV64-NEXT: slli a0, a0, 12
59125894
; RV64-NEXT: addi a0, a0, -513
5913-
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
5895+
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5896+
; RV64-NEXT: vadd.vx v9, v8, a0
5897+
; RV64-NEXT: vminu.vv v8, v9, v8
59145898
; RV64-NEXT: ret
59155899
%cmp = icmp ugt <2 x i64> %x, splat (i64 5000000000)
59165900
%sub = add <2 x i64> %x, splat (i64 -5000000001)

‎llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll‎

Lines changed: 18 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,9 +1001,9 @@ define <vscale x 2 x i64> @vsub_if_uge_swapped_nxv2i64(<vscale x 2 x i64> %va, <
10011001
define <vscale x 2 x i8> @sub_if_uge_C_nxv2i8(<vscale x 2 x i8> %x) {
10021002
; CHECK-LABEL: sub_if_uge_C_nxv2i8:
10031003
; CHECK: # %bb.0:
1004-
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
1005-
; CHECK-NEXT: vmsgtu.vi v0, v8, 12
1006-
; CHECK-NEXT: vadd.vi v8, v8, -13, v0.t
1004+
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1005+
; CHECK-NEXT: vadd.vi v9, v8, -13
1006+
; CHECK-NEXT: vminu.vv v8, v9, v8
10071007
; CHECK-NEXT: ret
10081008
%cmp = icmp ugt <vscale x 2 x i8> %x, splat (i8 12)
10091009
%sub = add <vscale x 2 x i8> %x, splat (i8 -13)
@@ -1014,11 +1014,10 @@ define <vscale x 2 x i8> @sub_if_uge_C_nxv2i8(<vscale x 2 x i8> %x) {
10141014
define <vscale x 2 x i16> @sub_if_uge_C_nxv2i16(<vscale x 2 x i16> %x) {
10151015
; CHECK-LABEL: sub_if_uge_C_nxv2i16:
10161016
; CHECK: # %bb.0:
1017-
; CHECK-NEXT: li a0, 2000
1018-
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
1019-
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
10201017
; CHECK-NEXT: li a0, -2001
1021-
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
1018+
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
1019+
; CHECK-NEXT: vadd.vx v9, v8, a0
1020+
; CHECK-NEXT: vminu.vv v8, v9, v8
10221021
; CHECK-NEXT: ret
10231022
%cmp = icmp ugt <vscale x 2 x i16> %x, splat (i16 2000)
10241023
%sub = add <vscale x 2 x i16> %x, splat (i16 -2001)
@@ -1029,13 +1028,11 @@ define <vscale x 2 x i16> @sub_if_uge_C_nxv2i16(<vscale x 2 x i16> %x) {
10291028
define <vscale x 2 x i32> @sub_if_uge_C_nxv2i32(<vscale x 2 x i32> %x) {
10301029
; CHECK-LABEL: sub_if_uge_C_nxv2i32:
10311030
; CHECK: # %bb.0:
1032-
; CHECK-NEXT: lui a0, 16
1033-
; CHECK-NEXT: addi a0, a0, -16
1034-
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
1035-
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
10361031
; CHECK-NEXT: lui a0, 1048560
10371032
; CHECK-NEXT: addi a0, a0, 15
1038-
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
1033+
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1034+
; CHECK-NEXT: vadd.vx v9, v8, a0
1035+
; CHECK-NEXT: vminu.vv v8, v9, v8
10391036
; CHECK-NEXT: ret
10401037
%cmp = icmp ugt <vscale x 2 x i32> %x, splat (i32 65520)
10411038
%sub = add <vscale x 2 x i32> %x, splat (i32 -65521)
@@ -1046,14 +1043,11 @@ define <vscale x 2 x i32> @sub_if_uge_C_nxv2i32(<vscale x 2 x i32> %x) {
10461043
define <vscale x 2 x i32> @sub_if_uge_C_swapped_nxv2i32(<vscale x 2 x i32> %x) {
10471044
; CHECK-LABEL: sub_if_uge_C_swapped_nxv2i32:
10481045
; CHECK: # %bb.0:
1049-
; CHECK-NEXT: lui a0, 16
1050-
; CHECK-NEXT: addi a0, a0, -15
1051-
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1052-
; CHECK-NEXT: vmsltu.vx v0, v8, a0
10531046
; CHECK-NEXT: lui a0, 1048560
10541047
; CHECK-NEXT: addi a0, a0, 15
1048+
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
10551049
; CHECK-NEXT: vadd.vx v9, v8, a0
1056-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
1050+
; CHECK-NEXT: vminu.vv v8, v8, v9
10571051
; CHECK-NEXT: ret
10581052
%cmp = icmp ult <vscale x 2 x i32> %x, splat (i32 65521)
10591053
%sub = add <vscale x 2 x i32> %x, splat (i32 -65521)
@@ -1065,38 +1059,28 @@ define <vscale x 2 x i64> @sub_if_uge_C_nxv2i64(<vscale x 2 x i64> %x) nounwind
10651059
; RV32-LABEL: sub_if_uge_C_nxv2i64:
10661060
; RV32: # %bb.0:
10671061
; RV32-NEXT: addi sp, sp, -16
1068-
; RV32-NEXT: li a0, 1
1069-
; RV32-NEXT: lui a1, 172127
1070-
; RV32-NEXT: mv a2, sp
1071-
; RV32-NEXT: addi a1, a1, 512
1072-
; RV32-NEXT: sw a1, 0(sp)
1073-
; RV32-NEXT: sw a0, 4(sp)
10741062
; RV32-NEXT: li a0, -2
1075-
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
1076-
; RV32-NEXT: vlse64.v v10, (a2), zero
10771063
; RV32-NEXT: lui a1, 876449
10781064
; RV32-NEXT: addi a1, a1, -513
10791065
; RV32-NEXT: sw a1, 8(sp)
10801066
; RV32-NEXT: sw a0, 12(sp)
10811067
; RV32-NEXT: addi a0, sp, 8
1082-
; RV32-NEXT: vlse64.v v12, (a0), zero
1083-
; RV32-NEXT: vmsltu.vv v0, v10, v8
1084-
; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
1068+
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1069+
; RV32-NEXT: vlse64.v v10, (a0), zero
1070+
; RV32-NEXT: vadd.vv v10, v8, v10
1071+
; RV32-NEXT: vminu.vv v8, v10, v8
10851072
; RV32-NEXT: addi sp, sp, 16
10861073
; RV32-NEXT: ret
10871074
;
10881075
; RV64-LABEL: sub_if_uge_C_nxv2i64:
10891076
; RV64: # %bb.0:
1090-
; RV64-NEXT: lui a0, 2384
1091-
; RV64-NEXT: addi a0, a0, 761
1092-
; RV64-NEXT: slli a0, a0, 9
1093-
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
1094-
; RV64-NEXT: vmsgtu.vx v0, v8, a0
10951077
; RV64-NEXT: lui a0, 1048278
10961078
; RV64-NEXT: addi a0, a0, -95
10971079
; RV64-NEXT: slli a0, a0, 12
10981080
; RV64-NEXT: addi a0, a0, -513
1099-
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
1081+
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1082+
; RV64-NEXT: vadd.vx v10, v8, a0
1083+
; RV64-NEXT: vminu.vv v8, v10, v8
11001084
; RV64-NEXT: ret
11011085
%cmp = icmp ugt <vscale x 2 x i64> %x, splat (i64 5000000000)
11021086
%sub = add <vscale x 2 x i64> %x, splat (i64 -5000000001)

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