diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 997cab6618062f..704de4f2783fc9 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1488,37 +1488,25 @@ class getSDWADstForVT { // instructions for the given VT. class getVOPSrc0ForVT { RegisterOperand ret = - !if(VT.isFP, - !if(!eq(VT.Size, 64), - VSrc_f64, - !if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), - !if(IsTrue16, - !if(IsFake16, VSrcFake16_f16_Lo128, VSrcT_f16_Lo128), - VSrc_f16 - ), - !if(!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)), - VSrc_v2f16, - !if(!or(!eq(VT.Value, v4f16.Value), !eq(VT.Value, v4bf16.Value)), - AVSrc_64, - VSrc_f32 - ) - ) - ) - ), - !if(!eq(VT.Size, 64), - VSrc_b64, - !if(!eq(VT.Value, i16.Value), - !if(IsTrue16, - !if(IsFake16, VSrcFake16_b16_Lo128, VSrcT_b16_Lo128), - VSrc_b16 - ), - !if(!eq(VT.Value, v2i16.Value), - VSrc_v2b16, - VSrc_b32 - ) - ) - ) - ); + !cond(!eq(VT, i64) : VSrc_b64, + !eq(VT, f64) : VSrc_f64, + !eq(VT, i32) : VSrc_b32, + !eq(VT, f32) : VSrc_f32, + !eq(VT, i16) : !if(IsTrue16, + !if(IsFake16, VSrcFake16_b16_Lo128, VSrcT_b16_Lo128), + VSrc_b16), + !eq(VT, f16) : !if(IsTrue16, + !if(IsFake16, VSrcFake16_f16_Lo128, VSrcT_f16_Lo128), + VSrc_f16), + !eq(VT, bf16) : !if(IsTrue16, + !if(IsFake16, VSrcFake16_f16_Lo128, VSrcT_f16_Lo128), + VSrc_f16), + !eq(VT, v2i16) : VSrc_v2b16, + !eq(VT, v2f16) : VSrc_v2f16, + !eq(VT, v2bf16) : VSrc_v2f16, + !eq(VT, v4f16) : AVSrc_64, + !eq(VT, v4bf16) : AVSrc_64, + 1 : VSrc_b32); } class getSOPSrcForVT {