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[Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled
This commit updates the Hexagon backend to handle vxi1 call operands Without HVX enabled. It ensures compatibility for vector types of sizes 4, 8, 16, 32, 64, and 128 x i1 when HVX is not enabled. Change-Id: Iddecb58b7e2884cc7b3b35569c0768e203979e95
1 parent b6820c3 commit b3c925f

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6 files changed

+135
-17
lines changed

6 files changed

+135
-17
lines changed

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,81 @@ static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
156156

157157
#include "HexagonGenCallingConv.inc"
158158

159+
unsigned HexagonTargetLowering::getVectorTypeBreakdownForCallingConv(
160+
LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
161+
unsigned &NumIntermediates, MVT &RegisterVT) const {
162+
163+
bool isBoolVector = VT.getVectorElementType() == MVT::i1;
164+
bool isPowerOf2 = VT.isPow2VectorType();
165+
unsigned NumElts = VT.getVectorNumElements();
166+
167+
// Split vectors of type vXi1 into (X/8) vectors of type v8i1,
168+
// where X is divisible by 8.
169+
if (isBoolVector && !Subtarget.useHVXOps() && isPowerOf2 && NumElts >= 8) {
170+
RegisterVT = MVT::v8i8;
171+
IntermediateVT = MVT::v8i1;
172+
NumIntermediates = NumElts / 8;
173+
return NumIntermediates;
174+
}
175+
176+
// In HVX 64-byte mode, vectors of type vXi1 are split into (X / 64) vectors
177+
// of type v64i1, provided that X is divisible by 64.
178+
if (isBoolVector && Subtarget.useHVX64BOps() && isPowerOf2 && NumElts >= 64) {
179+
RegisterVT = MVT::v64i8;
180+
IntermediateVT = MVT::v64i1;
181+
NumIntermediates = NumElts / 64;
182+
return NumIntermediates;
183+
}
184+
185+
// In HVX 128-byte mode, vectors of type vXi1 are split into (X / 128) vectors
186+
// of type v128i1, provided that X is divisible by 128.
187+
if (isBoolVector && Subtarget.useHVX128BOps() && isPowerOf2 &&
188+
NumElts >= 128) {
189+
RegisterVT = MVT::v128i8;
190+
IntermediateVT = MVT::v128i1;
191+
NumIntermediates = NumElts / 128;
192+
return NumIntermediates;
193+
}
194+
195+
return TargetLowering::getVectorTypeBreakdownForCallingConv(
196+
Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
197+
}
198+
199+
std::pair<MVT, unsigned>
200+
HexagonTargetLowering::handleMaskRegisterForCallingConv(
201+
const HexagonSubtarget &Subtarget, EVT VT) const {
202+
assert(VT.getVectorElementType() == MVT::i1);
203+
204+
const unsigned NumElems = VT.getVectorNumElements();
205+
206+
if (!VT.isPow2VectorType())
207+
return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
208+
209+
if (!Subtarget.useHVXOps() && NumElems >= 8)
210+
return {MVT::v8i8, NumElems / 8};
211+
212+
if (Subtarget.useHVX64BOps() && NumElems >= 64)
213+
return {MVT::v64i8, NumElems / 64};
214+
215+
if (Subtarget.useHVX128BOps() && NumElems >= 128)
216+
return {MVT::v128i8, NumElems / 128};
217+
218+
return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
219+
}
220+
221+
MVT HexagonTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
222+
CallingConv::ID CC,
223+
EVT VT) const {
224+
225+
if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
226+
auto [RegisterVT, NumRegisters] =
227+
handleMaskRegisterForCallingConv(Subtarget, VT);
228+
if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
229+
return RegisterVT;
230+
}
231+
232+
return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
233+
}
159234

160235
SDValue
161236
HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)

‎llvm/lib/Target/Hexagon/HexagonISelLowering.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,9 @@ class HexagonTargetLowering : public TargetLowering {
183183
SelectionDAG &DAG) const override;
184184

185185
const char *getTargetNodeName(unsigned Opcode) const override;
186+
std::pair<MVT, unsigned>
187+
handleMaskRegisterForCallingConv(const HexagonSubtarget &Subtarget,
188+
EVT VT) const;
186189

187190
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
188191
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
@@ -263,6 +266,14 @@ class HexagonTargetLowering : public TargetLowering {
263266
Register getRegisterByName(const char* RegName, LLT VT,
264267
const MachineFunction &MF) const override;
265268

269+
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
270+
CallingConv::ID CC, EVT VT,
271+
EVT &IntermediateVT,
272+
unsigned &NumIntermediates,
273+
MVT &RegisterVT) const override;
274+
275+
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
276+
EVT VT) const override;
266277
/// If a physical register, this returns the register that receives the
267278
/// exception address on entry to an EH pad.
268279
Register

‎llvm/test/CodeGen/Hexagon/calloperand-v128i1.ll‎

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,20 @@
1-
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s
1+
;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
2+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefixes=CHECK-64,CHECK-64-128
3+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefixes=CHECK-128,CHECK-64-128
24

35
; CHECK-LABEL: compare_vectors
4-
; CHECK: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
5-
; CHECK: [[REG2:(r[0-9]+)]] = #-1
6-
; CHECK: v0 = vand([[REG1]],[[REG2]])
7-
6+
; CHECK: [[REG8:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
9+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
10+
; CHECK-128: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
11+
; CHECK-128: [[REG2:(r[0-9]+)]] = #-1
12+
; CHECK-128: v0 = vand([[REG1]],[[REG2]])
13+
; CHECK-64: [[REG5:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
14+
; CHECK-64: [[REG6:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
15+
; CHECK-64: [[REG7:(r[0-9]+)]] = #-1
16+
; CHECK-64: v0 = vand([[REG5]],[[REG7]])
17+
; CHECK-64: v1 = vand([[REG6]],[[REG7]])
818
define void @compare_vectors(<128 x i8> %a, <128 x i8> %b) {
919
entry:
1020
%result = icmp eq <128 x i8> %a, %b
@@ -13,11 +23,13 @@ entry:
1323
}
1424

1525
; CHECK-LABEL: f.1:
16-
; CHECK: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
17-
; CHECK: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
18-
; CHECK: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
26+
; CHECK: [[REG9:(r[0-9]+)]] = and([[REG9]],##16843009)
27+
; CHECK: [[REG10:(r[0-9]+)]] = and([[REG10]],##16843009)
28+
; CHECK-64-128: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
29+
; CHECK-64-128: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
30+
; CHECK-64-128: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
1931

20-
define i32 @f.1(<128 x i1> %vec) {
32+
define i32 @f.1(<128 x i1> %vec){
2133
%element = extractelement <128 x i1> %vec, i32 6
2234
%is_true = icmp eq i1 %element, true
2335
br i1 %is_true, label %if_true, label %if_false

‎llvm/test/CodeGen/Hexagon/calloperand-v16i1.ll‎

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,15 @@
1-
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK
2-
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK
1+
;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
2+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-HVX
3+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-HVX
34

45
; CHECK-LABEL: compare_vectors
5-
; CHECK: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
6-
; CHECK: [[REG2:(r[0-9]+)]] = #-1
7-
; CHECK: v0 = vand([[REG1]],[[REG2]])
6+
; CHECK: [[REG5:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG5]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG5]])
9+
10+
; CHECK-HVX: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
11+
; CHECK-HVX: [[REG2:(r[0-9]+)]] = #-1
12+
; CHECK-HVX: v0 = vand([[REG1]],[[REG2]])
813

914
define void @compare_vectors(<16 x i32> %a, <16 x i32> %b) {
1015
entry:
@@ -14,9 +19,11 @@ entry:
1419
}
1520

1621
; CHECK-LABEL: f.1:
17-
; CHECK: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
18-
; CHECK: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
19-
; CHECK: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
22+
; CHECK: [[REG3:(r[0-9]+)]] = and([[REG3]],##16843009)
23+
; CHECK: [[REG4:(r[0-9]+)]] = and([[REG4]],##16843009)
24+
; CHECK-HVX: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
25+
; CHECK-HVX: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
26+
; CHECK-HVX: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
2027

2128
define i32 @f.1(<16 x i1> %vec) {
2229
%element = extractelement <16 x i1> %vec, i32 6

‎llvm/test/CodeGen/Hexagon/calloperand-v32i1.ll‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
1+
; RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
12
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-64
23
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-128
34

45
; CHECK-LABEL: compare_vectors
6+
; CHECK: [[REG8:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
59
; CHECK-64: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
610
; CHECK-64: [[REG2:(r[0-9]+)]] = #-1
711
; CHECK-64: v0 = vand([[REG1]],[[REG2]])
@@ -21,6 +25,8 @@ entry:
2125
}
2226

2327
; CHECK-LABEL: f.1:
28+
; CHECK: [[REG9:(r[0-9]+)]] = and([[REG9]],##16843009)
29+
; CHECK: [[REG10:(r[0-9]+)]] = and([[REG10]],##16843009)
2430
; CHECK-64: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
2531
; CHECK-64: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
2632
; CHECK-64: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})

‎llvm/test/CodeGen/Hexagon/calloperand-v64i1.ll‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,12 @@
1+
; RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
12
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-64
23
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-128
34

45
; CHECK-LABEL: compare_vectors
6+
; CHECK: [[REG8:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
9+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
510
; CHECK-64: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
611
; CHECK-64: [[REG2:(r[0-9]+)]] = #-1
712
; CHECK-64: v0 = vand([[REG1]],[[REG2]])
@@ -21,6 +26,8 @@ entry:
2126
}
2227

2328
; CHECK-LABEL: f.1:
29+
; CHECK: [[REG9:(r[0-9]+)]] = and([[REG9]],##16843009)
30+
; CHECK: [[REG10:(r[0-9]+)]] = and([[REG10]],##16843009)
2431
; CHECK-64: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
2532
; CHECK-64: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
2633
; CHECK-64: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})

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