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[PowerPC][AIX] Specify correct ABI alignment for double
Add `f64:32:64` to the data layout for AIX, to indicate that doubles have a 32-bit ABI alignment and 64-bit preferred alignment. Clang was already taking this into account, but it was not reflected in LLVM's data layout. Fixes #133599.
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13 files changed

+239
-273
lines changed

13 files changed

+239
-273
lines changed

‎clang/lib/Basic/Targets/PPC.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -390,7 +390,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
390390
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
391391
: PPCTargetInfo(Triple, Opts) {
392392
if (Triple.isOSAIX())
393-
resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");
393+
resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32-f64:32:64");
394394
else if (Triple.getArch() == llvm::Triple::ppcle)
395395
resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
396396
else
@@ -449,7 +449,7 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
449449

450450
if (Triple.isOSAIX()) {
451451
// TODO: Set appropriate ABI for AIX platform.
452-
DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64";
452+
DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64-f64:32:64";
453453
LongDoubleWidth = 64;
454454
LongDoubleAlign = DoubleAlign = 32;
455455
LongDoubleFormat = &llvm::APFloat::IEEEdouble();

‎clang/lib/CodeGen/CodeGenModule.cpp‎

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -378,15 +378,11 @@ static void checkDataLayoutConsistency(const TargetInfo &Target,
378378
Check("bfloat", llvm::Type::getBFloatTy(Context), Target.BFloat16Align);
379379
Check("float", llvm::Type::getFloatingPointTy(Context, *Target.FloatFormat),
380380
Target.FloatAlign);
381-
// FIXME: AIX specifies wrong double alignment in DataLayout
382-
if (!Triple.isOSAIX()) {
383-
Check("double",
384-
llvm::Type::getFloatingPointTy(Context, *Target.DoubleFormat),
385-
Target.DoubleAlign);
386-
Check("long double",
387-
llvm::Type::getFloatingPointTy(Context, *Target.LongDoubleFormat),
388-
Target.LongDoubleAlign);
389-
}
381+
Check("double", llvm::Type::getFloatingPointTy(Context, *Target.DoubleFormat),
382+
Target.DoubleAlign);
383+
Check("long double",
384+
llvm::Type::getFloatingPointTy(Context, *Target.LongDoubleFormat),
385+
Target.LongDoubleAlign);
390386
if (Target.hasFloat128Type())
391387
Check("__float128", llvm::Type::getFP128Ty(Context), Target.Float128Align);
392388
if (Target.hasIbm128Type())

‎llvm/lib/IR/AutoUpgrade.cpp‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6066,7 +6066,13 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
60666066
if (Pos != size_t(-1))
60676067
Res.insert(Pos + I64.size(), I128);
60686068
}
6069-
return Res;
6069+
}
6070+
6071+
if (T.isPPC() && T.isOSAIX() && !DL.contains("f64:32:64") && !DL.empty()) {
6072+
size_t Pos = Res.find("-S128");
6073+
if (Pos == StringRef::npos)
6074+
Pos = Res.size();
6075+
Res.insert(Pos, "-f64:32:64");
60706076
}
60716077

60726078
if (!T.isX86())

‎llvm/lib/TargetParser/TargetDataLayout.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -246,6 +246,10 @@ static std::string computePowerDataLayout(const Triple &T) {
246246
else
247247
Ret += "-n32";
248248

249+
// The ABI alignment for doubles on AIX is 4 bytes.
250+
if (T.isOSAIX())
251+
Ret += "-f64:32:64";
252+
249253
// Specify the vector alignment explicitly. For v256i1 and v512i1, the
250254
// calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
251255
// which is 256 and 512 bytes - way over aligned.

‎llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll‎

Lines changed: 70 additions & 82 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/PowerPC/aix-cc-abi.ll‎

Lines changed: 81 additions & 93 deletions
Original file line numberDiff line numberDiff line change
@@ -1012,22 +1012,18 @@ define void @call_test_stackarg_float() {
10121012
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
10131013
; ASM32PWR4-NEXT: stw 0, 88(1)
10141014
; ASM32PWR4-NEXT: li 4, 2
1015+
; ASM32PWR4-NEXT: li 5, 3
10151016
; ASM32PWR4-NEXT: li 6, 4
10161017
; ASM32PWR4-NEXT: li 7, 5
1017-
; ASM32PWR4-NEXT: li 8, 6
10181018
; ASM32PWR4-NEXT: lfs 1, 0(3)
10191019
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
1020+
; ASM32PWR4-NEXT: li 8, 6
10201021
; ASM32PWR4-NEXT: li 9, 7
1021-
; ASM32PWR4-NEXT: li 10, 8
10221022
; ASM32PWR4-NEXT: lfd 2, 0(3)
10231023
; ASM32PWR4-NEXT: li 3, 1
1024-
; ASM32PWR4-NEXT: stfd 2, 72(1)
1025-
; ASM32PWR4-NEXT: lwz 5, 76(1)
1026-
; ASM32PWR4-NEXT: lwz 11, 72(1)
1027-
; ASM32PWR4-NEXT: stw 5, 64(1)
1028-
; ASM32PWR4-NEXT: li 5, 3
1024+
; ASM32PWR4-NEXT: li 10, 8
1025+
; ASM32PWR4-NEXT: stfd 2, 60(1)
10291026
; ASM32PWR4-NEXT: stfs 1, 56(1)
1030-
; ASM32PWR4-NEXT: stw 11, 60(1)
10311027
; ASM32PWR4-NEXT: bl .test_stackarg_float[PR]
10321028
; ASM32PWR4-NEXT: nop
10331029
; ASM32PWR4-NEXT: addi 1, 1, 80
@@ -1130,24 +1126,20 @@ define void @call_test_stackarg_float3() {
11301126
; ASM32PWR4-NEXT: stwu 1, -80(1)
11311127
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
11321128
; ASM32PWR4-NEXT: stw 0, 88(1)
1129+
; ASM32PWR4-NEXT: li 4, 2
11331130
; ASM32PWR4-NEXT: li 5, 3
11341131
; ASM32PWR4-NEXT: li 6, 4
11351132
; ASM32PWR4-NEXT: li 7, 5
1136-
; ASM32PWR4-NEXT: li 8, 6
11371133
; ASM32PWR4-NEXT: lfd 1, 0(3)
11381134
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
1135+
; ASM32PWR4-NEXT: li 8, 6
11391136
; ASM32PWR4-NEXT: li 9, 7
11401137
; ASM32PWR4-NEXT: stfd 1, 72(1)
1138+
; ASM32PWR4-NEXT: lwz 10, 72(1)
11411139
; ASM32PWR4-NEXT: lfs 2, 0(3)
11421140
; ASM32PWR4-NEXT: li 3, 1
1143-
; ASM32PWR4-NEXT: stfd 1, 64(1)
1144-
; ASM32PWR4-NEXT: lwz 4, 68(1)
1145-
; ASM32PWR4-NEXT: lwz 10, 72(1)
1146-
; ASM32PWR4-NEXT: lwz 11, 64(1)
1147-
; ASM32PWR4-NEXT: stw 4, 56(1)
1148-
; ASM32PWR4-NEXT: li 4, 2
11491141
; ASM32PWR4-NEXT: stfs 2, 60(1)
1150-
; ASM32PWR4-NEXT: stw 11, 52(1)
1142+
; ASM32PWR4-NEXT: stfd 1, 52(1)
11511143
; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR]
11521144
; ASM32PWR4-NEXT: nop
11531145
; ASM32PWR4-NEXT: addi 1, 1, 80
@@ -1570,99 +1562,95 @@ define void @caller_fpr_stack() {
15701562
; ASM32PWR4-LABEL: caller_fpr_stack:
15711563
; ASM32PWR4: # %bb.0: # %entry
15721564
; ASM32PWR4-NEXT: mflr 0
1573-
; ASM32PWR4-NEXT: stwu 1, -160(1)
1565+
; ASM32PWR4-NEXT: stwu 1, -144(1)
15741566
; ASM32PWR4-NEXT: lwz 3, L..C19(2) # @d15
1575-
; ASM32PWR4-NEXT: stw 0, 168(1)
1576-
; ASM32PWR4-NEXT: lwz 5, L..C20(2) # %const.1
1577-
; ASM32PWR4-NEXT: lwz 4, L..C21(2) # @f14
1567+
; ASM32PWR4-NEXT: lwz 4, L..C20(2) # @f14
1568+
; ASM32PWR4-NEXT: lwz 5, L..C21(2) # @f16
1569+
; ASM32PWR4-NEXT: stw 0, 152(1)
1570+
; ASM32PWR4-NEXT: lis 6, 16361
1571+
; ASM32PWR4-NEXT: ori 6, 6, 39321
15781572
; ASM32PWR4-NEXT: lfd 0, 0(3)
1579-
; ASM32PWR4-NEXT: lwz 3, L..C22(2) # @f16
1580-
; ASM32PWR4-NEXT: lwz 3, 0(3)
1581-
; ASM32PWR4-NEXT: stw 3, 140(1)
1582-
; ASM32PWR4-NEXT: li 3, 0
1583-
; ASM32PWR4-NEXT: stw 3, 60(1)
1584-
; ASM32PWR4-NEXT: lis 3, 16352
1585-
; ASM32PWR4-NEXT: stw 3, 56(1)
1586-
; ASM32PWR4-NEXT: lis 3, 13107
1587-
; ASM32PWR4-NEXT: ori 3, 3, 13107
1588-
; ASM32PWR4-NEXT: stw 3, 68(1)
1589-
; ASM32PWR4-NEXT: lis 3, 16355
1590-
; ASM32PWR4-NEXT: ori 3, 3, 13107
1591-
; ASM32PWR4-NEXT: stw 3, 64(1)
1592-
; ASM32PWR4-NEXT: lis 3, 26214
1593-
; ASM32PWR4-NEXT: ori 3, 3, 26214
1594-
; ASM32PWR4-NEXT: stw 3, 76(1)
1595-
; ASM32PWR4-NEXT: lis 3, 16358
1596-
; ASM32PWR4-NEXT: ori 3, 3, 26214
1597-
; ASM32PWR4-NEXT: stw 3, 72(1)
1598-
; ASM32PWR4-NEXT: lis 3, -26215
1599-
; ASM32PWR4-NEXT: ori 3, 3, 39322
1600-
; ASM32PWR4-NEXT: stw 3, 84(1)
1601-
; ASM32PWR4-NEXT: stw 3, 100(1)
1602-
; ASM32PWR4-NEXT: lis 3, 16313
1603-
; ASM32PWR4-NEXT: ori 3, 3, 39321
1604-
; ASM32PWR4-NEXT: stw 3, 96(1)
1605-
; ASM32PWR4-NEXT: lis 3, -15729
1606-
; ASM32PWR4-NEXT: ori 3, 3, 23593
1607-
; ASM32PWR4-NEXT: stw 3, 108(1)
1608-
; ASM32PWR4-NEXT: lis 3, 16316
1609-
; ASM32PWR4-NEXT: ori 3, 3, 10485
1610-
; ASM32PWR4-NEXT: stw 3, 104(1)
1611-
; ASM32PWR4-NEXT: lis 3, -5243
1612-
; ASM32PWR4-NEXT: ori 3, 3, 7864
1613-
; ASM32PWR4-NEXT: stw 3, 116(1)
1614-
; ASM32PWR4-NEXT: lis 3, 16318
1615-
; ASM32PWR4-NEXT: ori 3, 3, 47185
1616-
; ASM32PWR4-NEXT: stw 3, 112(1)
1617-
; ASM32PWR4-NEXT: lis 3, 2621
1618-
; ASM32PWR4-NEXT: ori 3, 3, 28836
1619-
; ASM32PWR4-NEXT: stw 3, 124(1)
1620-
; ASM32PWR4-NEXT: lis 3, 16320
1621-
; ASM32PWR4-NEXT: ori 3, 3, 41943
1622-
; ASM32PWR4-NEXT: stw 3, 120(1)
1623-
; ASM32PWR4-NEXT: lwz 3, L..C23(2) # %const.0
1624-
; ASM32PWR4-NEXT: lfd 2, 0(3)
1625-
; ASM32PWR4-NEXT: lwz 3, L..C24(2) # %const.2
1573+
; ASM32PWR4-NEXT: lwz 3, 0(4)
1574+
; ASM32PWR4-NEXT: lwz 4, 0(5)
1575+
; ASM32PWR4-NEXT: li 5, 0
1576+
; ASM32PWR4-NEXT: stw 5, 60(1)
1577+
; ASM32PWR4-NEXT: lis 5, 16352
1578+
; ASM32PWR4-NEXT: stw 5, 56(1)
1579+
; ASM32PWR4-NEXT: lis 5, 13107
1580+
; ASM32PWR4-NEXT: ori 5, 5, 13107
1581+
; ASM32PWR4-NEXT: stw 5, 68(1)
1582+
; ASM32PWR4-NEXT: lis 5, 16355
1583+
; ASM32PWR4-NEXT: ori 5, 5, 13107
1584+
; ASM32PWR4-NEXT: stw 5, 64(1)
1585+
; ASM32PWR4-NEXT: lis 5, 26214
1586+
; ASM32PWR4-NEXT: ori 5, 5, 26214
1587+
; ASM32PWR4-NEXT: stw 5, 76(1)
1588+
; ASM32PWR4-NEXT: lis 5, 16358
1589+
; ASM32PWR4-NEXT: ori 5, 5, 26214
1590+
; ASM32PWR4-NEXT: stw 5, 72(1)
1591+
; ASM32PWR4-NEXT: lis 5, -26215
1592+
; ASM32PWR4-NEXT: ori 5, 5, 39322
1593+
; ASM32PWR4-NEXT: stw 5, 84(1)
1594+
; ASM32PWR4-NEXT: stw 5, 100(1)
1595+
; ASM32PWR4-NEXT: lis 5, 16313
1596+
; ASM32PWR4-NEXT: ori 5, 5, 39321
1597+
; ASM32PWR4-NEXT: stw 5, 96(1)
1598+
; ASM32PWR4-NEXT: lis 5, -15729
1599+
; ASM32PWR4-NEXT: ori 5, 5, 23593
1600+
; ASM32PWR4-NEXT: stw 5, 108(1)
1601+
; ASM32PWR4-NEXT: lis 5, 16316
1602+
; ASM32PWR4-NEXT: ori 5, 5, 10485
1603+
; ASM32PWR4-NEXT: stw 5, 104(1)
1604+
; ASM32PWR4-NEXT: lis 5, -5243
1605+
; ASM32PWR4-NEXT: ori 5, 5, 7864
1606+
; ASM32PWR4-NEXT: stw 5, 116(1)
1607+
; ASM32PWR4-NEXT: lis 5, 16318
1608+
; ASM32PWR4-NEXT: ori 5, 5, 47185
1609+
; ASM32PWR4-NEXT: stw 6, 80(1)
1610+
; ASM32PWR4-NEXT: lis 6, -13108
1611+
; ASM32PWR4-NEXT: ori 6, 6, 52429
1612+
; ASM32PWR4-NEXT: stw 5, 112(1)
1613+
; ASM32PWR4-NEXT: lis 5, 2621
1614+
; ASM32PWR4-NEXT: ori 5, 5, 28836
1615+
; ASM32PWR4-NEXT: stw 6, 92(1)
1616+
; ASM32PWR4-NEXT: lis 6, 16364
1617+
; ASM32PWR4-NEXT: ori 6, 6, 52428
1618+
; ASM32PWR4-NEXT: stw 5, 124(1)
1619+
; ASM32PWR4-NEXT: lis 5, 16320
1620+
; ASM32PWR4-NEXT: ori 5, 5, 41943
1621+
; ASM32PWR4-NEXT: stw 6, 88(1)
1622+
; ASM32PWR4-NEXT: lwz 6, L..C22(2) # %const.0
1623+
; ASM32PWR4-NEXT: stw 5, 120(1)
1624+
; ASM32PWR4-NEXT: lwz 5, L..C23(2) # %const.1
1625+
; ASM32PWR4-NEXT: lfd 2, 0(6)
1626+
; ASM32PWR4-NEXT: lwz 6, L..C24(2) # %const.2
16261627
; ASM32PWR4-NEXT: lfd 3, 0(5)
16271628
; ASM32PWR4-NEXT: lwz 5, L..C25(2) # %const.3
1628-
; ASM32PWR4-NEXT: lfd 4, 0(3)
1629-
; ASM32PWR4-NEXT: lwz 3, L..C26(2) # %const.4
1629+
; ASM32PWR4-NEXT: lfd 4, 0(6)
1630+
; ASM32PWR4-NEXT: lwz 6, L..C26(2) # %const.4
16301631
; ASM32PWR4-NEXT: lfd 6, 0(5)
16311632
; ASM32PWR4-NEXT: lwz 5, L..C27(2) # %const.5
1632-
; ASM32PWR4-NEXT: lwz 4, 0(4)
1633-
; ASM32PWR4-NEXT: lfd 7, 0(3)
1634-
; ASM32PWR4-NEXT: lwz 3, L..C28(2) # %const.6
1633+
; ASM32PWR4-NEXT: lfd 7, 0(6)
1634+
; ASM32PWR4-NEXT: lwz 6, L..C28(2) # %const.6
16351635
; ASM32PWR4-NEXT: lfd 8, 0(5)
16361636
; ASM32PWR4-NEXT: lwz 5, L..C29(2) # %const.7
1637-
; ASM32PWR4-NEXT: stw 4, 128(1)
1638-
; ASM32PWR4-NEXT: lis 4, 16361
1639-
; ASM32PWR4-NEXT: ori 4, 4, 39321
1640-
; ASM32PWR4-NEXT: lfd 9, 0(3)
1641-
; ASM32PWR4-NEXT: lwz 3, L..C30(2) # %const.8
1637+
; ASM32PWR4-NEXT: lfd 9, 0(6)
1638+
; ASM32PWR4-NEXT: lwz 6, L..C30(2) # %const.8
16421639
; ASM32PWR4-NEXT: lfd 1, 0(5)
16431640
; ASM32PWR4-NEXT: lwz 5, L..C31(2) # %const.9
1644-
; ASM32PWR4-NEXT: stw 4, 80(1)
1645-
; ASM32PWR4-NEXT: lis 4, -13108
1641+
; ASM32PWR4-NEXT: lfd 11, 0(6)
1642+
; ASM32PWR4-NEXT: lwz 6, L..C32(2) # %const.10
16461643
; ASM32PWR4-NEXT: fmr 10, 1
1647-
; ASM32PWR4-NEXT: ori 4, 4, 52429
1648-
; ASM32PWR4-NEXT: lfd 11, 0(3)
1649-
; ASM32PWR4-NEXT: lwz 3, L..C32(2) # %const.10
16501644
; ASM32PWR4-NEXT: lfd 12, 0(5)
16511645
; ASM32PWR4-NEXT: lwz 5, L..C33(2) # %const.11
1652-
; ASM32PWR4-NEXT: stw 4, 92(1)
1653-
; ASM32PWR4-NEXT: lis 4, 16364
1654-
; ASM32PWR4-NEXT: ori 4, 4, 52428
1655-
; ASM32PWR4-NEXT: stfd 0, 152(1)
1656-
; ASM32PWR4-NEXT: stw 4, 88(1)
1657-
; ASM32PWR4-NEXT: lwz 4, 156(1)
1658-
; ASM32PWR4-NEXT: lfd 13, 0(3)
1646+
; ASM32PWR4-NEXT: lfd 13, 0(6)
16591647
; ASM32PWR4-NEXT: lfs 5, 0(5)
1660-
; ASM32PWR4-NEXT: lwz 3, 152(1)
1661-
; ASM32PWR4-NEXT: stw 4, 136(1)
1662-
; ASM32PWR4-NEXT: stw 3, 132(1)
1648+
; ASM32PWR4-NEXT: stfd 0, 132(1)
1649+
; ASM32PWR4-NEXT: stw 4, 140(1)
1650+
; ASM32PWR4-NEXT: stw 3, 128(1)
16631651
; ASM32PWR4-NEXT: bl .test_fpr_stack
16641652
; ASM32PWR4-NEXT: nop
1665-
; ASM32PWR4-NEXT: addi 1, 1, 160
1653+
; ASM32PWR4-NEXT: addi 1, 1, 144
16661654
; ASM32PWR4-NEXT: lwz 0, 8(1)
16671655
; ASM32PWR4-NEXT: mtlr 0
16681656
; ASM32PWR4-NEXT: blr

‎llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ entry:
160160
; CHECK-ASM-LABEL: .main:{{[[:space:]] *}}# %bb.0:
161161
; CHECK-FUNC-LABEL: .csect .main[PR],5{{[[:space:]] *}}# %bb.0
162162
; COMMON-NEXT: mflr 0
163-
; COMMON: stw 0, 168(1)
163+
; COMMON: stw 0, 152(1)
164164
; COMMON: mtlr 0
165165
; COMMON-NEXT: blr
166166
; COMMON-NEXT: L..main0:

‎llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,8 @@
2929
%struct.anon = type <{ i32, double }>
3030
@astruct = global [1 x %struct.anon] [%struct.anon <{ i32 1, double 7.000000e+00 }>], align 1
3131

32-
%struct.anon2 = type { double, i32 }
33-
@bstruct = global [1 x %struct.anon2] [%struct.anon2 { double 7.000000e+00 , i32 1}], align 8
32+
%struct.anon2 = type { double, i32, [4 x i8] }
33+
@bstruct = global [1 x %struct.anon2] [%struct.anon2 { double 7.000000e+00 , i32 1, [4 x i8] undef }], align 8
3434

3535
@a = common global i32 0, align 4
3636
@b = common global i64 0, align 8

‎llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll‎

Lines changed: 23 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -115,23 +115,17 @@ define double @double_va_arg(double %a, ...) local_unnamed_addr {
115115
; CHECK-NEXT: liveins: $f1, $r5, $r6, $r7, $r8, $r9, $r10
116116
; CHECK-NEXT: {{ $}}
117117
; CHECK-NEXT: renamable $r3 = ADDI %fixed-stack.0, 0
118+
; CHECK-NEXT: STW killed renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16)
119+
; CHECK-NEXT: STW killed renamable $r6, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4)
118120
; CHECK-NEXT: STW killed renamable $r7, 8, %fixed-stack.0 :: (store (s32), align 8)
119-
; CHECK-NEXT: STW renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16)
120-
; CHECK-NEXT: STW renamable $r6, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4)
121121
; CHECK-NEXT: STW killed renamable $r8, 12, %fixed-stack.0 :: (store (s32))
122+
; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %ir.argp.cur2, align 16)
122123
; CHECK-NEXT: STW killed renamable $r9, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16, align 16)
123124
; CHECK-NEXT: STW killed renamable $r10, 20, %fixed-stack.0 :: (store (s32))
124-
; CHECK-NEXT: STW renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
125-
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.1.arg2 :: (store (s32) into %ir.arg2)
126-
; CHECK-NEXT: STW renamable $r5, 0, %stack.2 :: (store (s32) into %stack.2, align 8)
127-
; CHECK-NEXT: STW renamable $r6, 4, %stack.2 :: (store (s32) into %stack.2 + 4)
128-
; CHECK-NEXT: renamable $f0 = LFD 0, %stack.2 :: (load (s64) from %stack.2)
129-
; CHECK-NEXT: STW killed renamable $r5, 0, %stack.3 :: (store (s32) into %stack.3, align 8)
130-
; CHECK-NEXT: STW killed renamable $r6, 4, %stack.3 :: (store (s32) into %stack.3 + 4)
131-
; CHECK-NEXT: renamable $f2 = LFD 0, %stack.3 :: (load (s64) from %stack.3)
132-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
133-
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
134-
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
125+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD renamable $f0, killed renamable $f1, implicit $rm
126+
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, renamable $f0, implicit $rm
127+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
128+
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
135129
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
136130
entry:
137131
%arg1 = alloca ptr, align 4
@@ -163,31 +157,24 @@ define double @double_stack_va_arg(double %one, double %two, double %three, doub
163157
; CHECK: bb.0.entry:
164158
; CHECK-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
165159
; CHECK-NEXT: {{ $}}
160+
; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %ir.argp.cur142, align 16)
161+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
162+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm
163+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm
164+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, implicit $rm
165+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, implicit $rm
166+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, implicit $rm
167+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f8, implicit $rm
168+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f9, implicit $rm
169+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f10, implicit $rm
170+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f11, implicit $rm
171+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f12, implicit $rm
172+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f13, implicit $rm
173+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, renamable $f0, implicit $rm
174+
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, renamable $f0, implicit $rm
175+
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
166176
; CHECK-NEXT: renamable $r3 = ADDI %fixed-stack.0, 0
167177
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
168-
; CHECK-NEXT: renamable $r3 = LWZ 0, %fixed-stack.0 :: (load (s32) from %ir.argp.cur142, align 16)
169-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
170-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm
171-
; CHECK-NEXT: STW renamable $r3, 0, %stack.2 :: (store (s32) into %stack.2, align 8)
172-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm
173-
; CHECK-NEXT: renamable $r4 = LWZ 4, %fixed-stack.0 :: (load (s32) from %ir.argp.cur142 + 4)
174-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm
175-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm
176-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm
177-
; CHECK-NEXT: STW renamable $r4, 4, %stack.2 :: (store (s32) into %stack.2 + 4)
178-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm
179-
; CHECK-NEXT: renamable $f1 = LFD 0, %stack.2 :: (load (s64) from %stack.2)
180-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm
181-
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.3 :: (store (s32) into %stack.3, align 8)
182-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm
183-
; CHECK-NEXT: STW killed renamable $r4, 4, %stack.3 :: (store (s32) into %stack.3 + 4)
184-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm
185-
; CHECK-NEXT: renamable $f2 = LFD 0, %stack.3 :: (load (s64) from %stack.3)
186-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm
187-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm
188-
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
189-
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
190-
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
191178
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
192179
entry:
193180
%arg1 = alloca ptr, align 4

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