From 9c6a2de24b6a9f01efd68546f7ab8c36f71a2352 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Thu, 15 Feb 2024 12:11:51 -0500 Subject: [PATCH] [AMDGPU] Clean up functions for checking inline literals (#81282) This patch cleans up functions for checking inline literals. --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 13 +++---------- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 14 +++----------- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 4 +--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 ++---- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 12 ++---------- 6 files changed, 12 insertions(+), 39 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 5278b552a65514..024adcda0fa061 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -327,7 +327,7 @@ bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const { return TII->isInlineConstant(C->getAPIntValue()); if (const ConstantFPSDNode *C = dyn_cast(N)) - return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt()); + return TII->isInlineConstant(C->getValueAPF()); return false; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index 3b42d88df0c246..f987b747c0e21b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -105,18 +105,11 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel { private: std::pair foldFrameIndex(SDValue N) const; - bool isInlineImmediate(const SDNode *N) const; - - bool isInlineImmediate16(int64_t Imm) const { - return AMDGPU::isInlinableLiteral16(Imm, Subtarget->hasInv2PiInlineImm()); - } - bool isInlineImmediate32(int64_t Imm) const { - return AMDGPU::isInlinableLiteral32(Imm, Subtarget->hasInv2PiInlineImm()); - } + bool isInlineImmediate(const SDNode *N) const; - bool isInlineImmediate64(int64_t Imm) const { - return AMDGPU::isInlinableLiteral64(Imm, Subtarget->hasInv2PiInlineImm()); + bool isInlineImmediate(const APInt &Imm) const { + return Subtarget->getInstrInfo()->isInlineConstant(Imm); } bool isInlineImmediate(const APFloat &Imm) const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 5657880279962b..aed9bffc551f47 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -4106,7 +4106,7 @@ InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectWMMAVISrc(MachineOperand &Root) const { std::optional FPValReg; if (mi_match(Root.getReg(), *MRI, m_GFCstOrSplat(FPValReg))) { - if (TII.isInlineConstant(FPValReg->Value.bitcastToAPInt())) { + if (TII.isInlineConstant(FPValReg->Value)) { return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(FPValReg->Value.bitcastToAPInt().getSExtValue()); }}}; @@ -5746,16 +5746,8 @@ void AMDGPUInstructionSelector::renderFPPow2ToExponent(MachineInstrBuilder &MIB, MIB.addImm(ExpVal); } -bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const { - return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm()); -} - -bool AMDGPUInstructionSelector::isInlineImmediate32(int64_t Imm) const { - return AMDGPU::isInlinableLiteral32(Imm, STI.hasInv2PiInlineImm()); -} - -bool AMDGPUInstructionSelector::isInlineImmediate64(int64_t Imm) const { - return AMDGPU::isInlinableLiteral64(Imm, STI.hasInv2PiInlineImm()); +bool AMDGPUInstructionSelector::isInlineImmediate(const APInt &Imm) const { + return TII.isInlineConstant(Imm); } bool AMDGPUInstructionSelector::isInlineImmediate(const APFloat &Imm) const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index ef7630f137aca6..f561d5d29efc43 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -353,9 +353,7 @@ class AMDGPUInstructionSelector final : public InstructionSelector { void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; - bool isInlineImmediate16(int64_t Imm) const; - bool isInlineImmediate32(int64_t Imm) const; - bool isInlineImmediate64(int64_t Imm) const; + bool isInlineImmediate(const APInt &Imm) const; bool isInlineImmediate(const APFloat &Imm) const; // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 56f0e716423955..7be670f8e76c37 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -12965,10 +12965,8 @@ SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG, const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); - if ((!K0->hasOneUse() || - TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) && - (!K1->hasOneUse() || - TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) { + if ((!K0->hasOneUse() || TII->isInlineConstant(K0->getValueAPF())) && + (!K1->hasOneUse() || TII->isInlineConstant(K1->getValueAPF()))) { return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0), Var, SDValue(K0, 0), SDValue(K1, 0)); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 4b2b79335c8a20..2b47686f23c238 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -797,16 +797,8 @@ def i64imm_32bit : ImmLeaf(Imm); }]>; -def InlineImm16 : ImmLeaf; - -def InlineImm32 : ImmLeaf; - -def InlineImm64 : ImmLeaf; def InlineImmFP32 : FPImmLeaf