Bail if return_type != elt_type

Author: mooori

llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp

@@ -653,16 +653,16 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
     if (VecVT.isScalableVector())
       break;
 
-    Known.Zero.setAllBits();
-    Known.One.setAllBits();
-
     const unsigned EltBitWidth = VecVT.getScalarSizeInBits();
     const unsigned NumSrcElts = VecVT.getNumElements();
+    // A return type different from the vector's element type may lead to
+    // issues with pattern selection. Bail out to avoid that.
+    if (BitWidth > EltBitWidth) {
+      break;
+    }
 
-    // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
-    // anything about the extended bits.
-    if (BitWidth > EltBitWidth)
-      Known = Known.trunc(EltBitWidth);
+    Known.Zero.setAllBits();
+    Known.One.setAllBits();
 
     // If we know the element index, just demand that vector element, else for
     // an unknown element index, ignore DemandedElts and demand them all.
@@ -673,10 +673,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
 
     computeKnownBitsImpl(InVec, Known2, DemandedSrcElts, Depth + 1);
     Known = Known.intersectWith(Known2);
-
-    if (BitWidth > EltBitWidth)
-      Known = Known.anyext(BitWidth);
-
+    
     break;
   }
   case TargetOpcode::G_SHUFFLE_VECTOR: {

llvm/test/CodeGen/AArch64/GlobalISel/knownbits-extract-vector.mir

@@ -115,3 +115,19 @@ body: |
     %1:_(s16) = G_EXTRACT_VECTOR_ELT %sext0, %idx
 ...
 ---
+# Verifies known bit computation bails if return type differs from vector
+# element type. Without bailing, the 8 lowest bits of %4 would be known.
+name: bail_on_different_return_type
+body: |
+  bb.0:
+  ; CHECK-LABEL: name: @bail_on_different_return_type
+  ; CHECK-NEXT: %0:_ KnownBits:00000011 SignBits:6
+  ; CHECK-NEXT: %1:_ KnownBits:00001010 SignBits:4
+  ; CHECK-NEXT: %2:_ KnownBits:0000?01? SignBits:4
+  ; CHECK-NEXT: %idx:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000001 SignBits:63
+  ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+    %0:_(s8) = G_CONSTANT i8 3
+    %1:_(s8) = G_CONSTANT i8 10
+    %2:_(<2 x s8>) = G_BUILD_VECTOR %0, %1
+    %idx:_(s64) = G_CONSTANT i64 1
+    %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %idx