[ARM] Remove MVE VADC/VSBC custom decoders

Author: s-barannikov

llvm/lib/Target/ARM/ARMInstrMVE.td

@@ -5027,6 +5027,7 @@ class MVE_VADCSBC<string iname, bit I, bit subtract,
   : MVE_qDest_qSrc<iname, "i32", (outs MQPR:$Qd, cl_FPSCR_NZCV:$carryout),
                    !con((ins MQPR:$Qn, MQPR:$Qm), carryin),
                    "$Qd, $Qn, $Qm", vpred_r, "", 0b10, pattern> {
+  bits<0> carryout;
   bits<4> Qn;
 
   let Inst{28} = subtract;
@@ -5037,16 +5038,16 @@ class MVE_VADCSBC<string iname, bit I, bit subtract,
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b0;
-
-  // Custom decoder method in order to add the FPSCR operand(s), which
-  // Tablegen won't do right
-  let DecoderMethod = "DecodeMVEVADCInstruction";
 }
 
-def MVE_VADC  : MVE_VADCSBC<"vadc",  0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)>;
+def MVE_VADC  : MVE_VADCSBC<"vadc",  0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)> {
+  bits<0> carryin;
+}
 def MVE_VADCI : MVE_VADCSBC<"vadci", 0b1, 0b0, (ins)>;
 
-def MVE_VSBC  : MVE_VADCSBC<"vsbc",  0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
+def MVE_VSBC  : MVE_VADCSBC<"vsbc",  0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)> {
+  bits<0> carryin;
+}
 def MVE_VSBCI : MVE_VADCSBC<"vsbci", 0b1, 0b1, (ins)>;
 
 class MVE_VQDMULL<string iname, string suffix, bit size, bit T,

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

@@ -608,6 +608,12 @@ static DecodeStatus DecodeVCCRRegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus
+Decodecl_FPSCR_NZCVRegisterClass(MCInst &Inst, const MCDisassembler *Decoder) {
+  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+  return MCDisassembler::Success;
+}
+
 // Operand decoding functions.
 
 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
@@ -2892,32 +2898,6 @@ static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
   return S;
 }
 
-static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
-                                             uint64_t Address,
-                                             const MCDisassembler *Decoder) {
-  DecodeStatus S = MCDisassembler::Success;
-
-  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
-  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
-  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
-    return MCDisassembler::Fail;
-  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
-
-  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
-  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
-  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
-    return MCDisassembler::Fail;
-  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
-  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
-  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
-    return MCDisassembler::Fail;
-  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
-    Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
-
-  Check(S, DecodeVpredROperand(Inst, Decoder));
-  return S;
-}
-
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
                                              uint64_t Address,
                                              const MCDisassembler *Decoder) {