Skip to content

Commit 6e41d60

Browse files
davemgreendavemgreen
authored
[SelectionDAG] Change computeAliasing signature from optional<uint64> to LocationSize. (#83017)
This is another smaller step of #70452, changing the signature of computeAliasing() from optional<uint64_t> to LocationSize, and follow-up changes in DAGCombiner::mayAlias(). There are some test change due to the previous AA->isNoAlias call incorrectly using an unknown size (~UINT64_T(0)). This should then be improved again in #70452 when the types are known to be scalable.
1 parent 6008cd4 commit 6e41d60

File tree

8 files changed

+102
-110
lines changed

8 files changed

+102
-110
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#ifndef LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
1010
#define LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
1111

12+
#include "llvm/Analysis/MemoryLocation.h"
1213
#include "llvm/CodeGen/SelectionDAGNodes.h"
1314
#include <cstdint>
1415

@@ -81,10 +82,8 @@ class BaseIndexOffset {
8182

8283
// Returns true `Op0` and `Op1` can be proven to alias/not alias, in
8384
// which case `IsAlias` is set to true/false.
84-
static bool computeAliasing(const SDNode *Op0,
85-
const std::optional<int64_t> NumBytes0,
86-
const SDNode *Op1,
87-
const std::optional<int64_t> NumBytes1,
85+
static bool computeAliasing(const SDNode *Op0, const LocationSize NumBytes0,
86+
const SDNode *Op1, const LocationSize NumBytes1,
8887
const SelectionDAG &DAG, bool &IsAlias);
8988

9089
/// Parses tree in N for base, index, offset addresses.

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -27835,7 +27835,7 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2783527835
bool IsAtomic;
2783627836
SDValue BasePtr;
2783727837
int64_t Offset;
27838-
std::optional<int64_t> NumBytes;
27838+
LocationSize NumBytes;
2783927839
MachineMemOperand *MMO;
2784027840
};
2784127841

@@ -27853,21 +27853,24 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2785327853
LSN->isAtomic(),
2785427854
LSN->getBasePtr(),
2785527855
Offset /*base offset*/,
27856-
std::optional<int64_t>(Size),
27856+
Size != ~UINT64_C(0) ? LocationSize::precise(Size)
27857+
: LocationSize::beforeOrAfterPointer(),
2785727858
LSN->getMemOperand()};
2785827859
}
2785927860
if (const auto *LN = cast<LifetimeSDNode>(N))
2786027861
return {false /*isVolatile*/,
2786127862
/*isAtomic*/ false,
2786227863
LN->getOperand(1),
2786327864
(LN->hasOffset()) ? LN->getOffset() : 0,
27864-
(LN->hasOffset()) ? std::optional<int64_t>(LN->getSize())
27865-
: std::optional<int64_t>(),
27865+
(LN->hasOffset()) ? LocationSize::precise(LN->getSize())
27866+
: LocationSize::beforeOrAfterPointer(),
2786627867
(MachineMemOperand *)nullptr};
2786727868
// Default.
2786827869
return {false /*isvolatile*/,
27869-
/*isAtomic*/ false, SDValue(),
27870-
(int64_t)0 /*offset*/, std::optional<int64_t>() /*size*/,
27870+
/*isAtomic*/ false,
27871+
SDValue(),
27872+
(int64_t)0 /*offset*/,
27873+
LocationSize::beforeOrAfterPointer() /*size*/,
2787127874
(MachineMemOperand *)nullptr};
2787227875
};
2787327876

@@ -27922,18 +27925,20 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2792227925
int64_t SrcValOffset1 = MUC1.MMO->getOffset();
2792327926
Align OrigAlignment0 = MUC0.MMO->getBaseAlign();
2792427927
Align OrigAlignment1 = MUC1.MMO->getBaseAlign();
27925-
auto &Size0 = MUC0.NumBytes;
27926-
auto &Size1 = MUC1.NumBytes;
27928+
LocationSize Size0 = MUC0.NumBytes;
27929+
LocationSize Size1 = MUC1.NumBytes;
2792727930
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
27928-
Size0.has_value() && Size1.has_value() && *Size0 == *Size1 &&
27929-
OrigAlignment0 > *Size0 && SrcValOffset0 % *Size0 == 0 &&
27930-
SrcValOffset1 % *Size1 == 0) {
27931+
Size0.hasValue() && Size1.hasValue() && Size0 == Size1 &&
27932+
OrigAlignment0 > Size0.getValue() &&
27933+
SrcValOffset0 % Size0.getValue() == 0 &&
27934+
SrcValOffset1 % Size1.getValue() == 0) {
2793127935
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
2793227936
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
2793327937

2793427938
// There is no overlap between these relatively aligned accesses of
2793527939
// similar size. Return no alias.
27936-
if ((OffAlign0 + *Size0) <= OffAlign1 || (OffAlign1 + *Size1) <= OffAlign0)
27940+
if ((OffAlign0 + (int64_t)Size0.getValue()) <= OffAlign1 ||
27941+
(OffAlign1 + (int64_t)Size1.getValue()) <= OffAlign0)
2793727942
return false;
2793827943
}
2793927944

@@ -27946,12 +27951,12 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2794627951
UseAA = false;
2794727952
#endif
2794827953

27949-
if (UseAA && AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() && Size0 &&
27950-
Size1) {
27954+
if (UseAA && AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() &&
27955+
Size0.hasValue() && Size1.hasValue()) {
2795127956
// Use alias analysis information.
2795227957
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
27953-
int64_t Overlap0 = *Size0 + SrcValOffset0 - MinOffset;
27954-
int64_t Overlap1 = *Size1 + SrcValOffset1 - MinOffset;
27958+
int64_t Overlap0 = Size0.getValue() + SrcValOffset0 - MinOffset;
27959+
int64_t Overlap1 = Size1.getValue() + SrcValOffset1 - MinOffset;
2795527960
if (AA->isNoAlias(
2795627961
MemoryLocation(MUC0.MMO->getValue(), Overlap0,
2795727962
UseTBAA ? MUC0.MMO->getAAInfo() : AAMDNodes()),

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -91,11 +91,10 @@ bool BaseIndexOffset::equalBaseIndex(const BaseIndexOffset &Other,
9191
}
9292

9393
bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
94-
const std::optional<int64_t> NumBytes0,
94+
const LocationSize NumBytes0,
9595
const SDNode *Op1,
96-
const std::optional<int64_t> NumBytes1,
96+
const LocationSize NumBytes1,
9797
const SelectionDAG &DAG, bool &IsAlias) {
98-
9998
BaseIndexOffset BasePtr0 = match(Op0, DAG);
10099
if (!BasePtr0.getBase().getNode())
101100
return false;
@@ -105,27 +104,26 @@ bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
105104
return false;
106105

107106
int64_t PtrDiff;
108-
if (NumBytes0 && NumBytes1 &&
109-
BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) {
107+
if (BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) {
110108
// If the size of memory access is unknown, do not use it to analysis.
111109
// One example of unknown size memory access is to load/store scalable
112110
// vector objects on the stack.
113111
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
114112
// following situations arise:
115-
if (PtrDiff >= 0 &&
116-
*NumBytes0 != static_cast<int64_t>(MemoryLocation::UnknownSize)) {
113+
if (PtrDiff >= 0 && NumBytes0.hasValue() && !NumBytes0.isScalable()) {
117114
// [----BasePtr0----]
118115
// [---BasePtr1--]
119116
// ========PtrDiff========>
120-
IsAlias = !(*NumBytes0 <= PtrDiff);
117+
IsAlias = !(static_cast<int64_t>(NumBytes0.getValue().getFixedValue()) <=
118+
PtrDiff);
121119
return true;
122120
}
123-
if (PtrDiff < 0 &&
124-
*NumBytes1 != static_cast<int64_t>(MemoryLocation::UnknownSize)) {
121+
if (PtrDiff < 0 && NumBytes1.hasValue() && !NumBytes1.isScalable()) {
125122
// [----BasePtr0----]
126123
// [---BasePtr1--]
127124
// =====(-PtrDiff)====>
128-
IsAlias = !((PtrDiff + *NumBytes1) <= 0);
125+
IsAlias = !((PtrDiff + static_cast<int64_t>(
126+
NumBytes1.getValue().getFixedValue())) <= 0);
129127
return true;
130128
}
131129
return false;

‎llvm/test/CodeGen/AArch64/alloca-load-store-scalable-array.ll‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -14,12 +14,12 @@ define void @array_1D(ptr %addr) #0 {
1414
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
1515
; CHECK-NEXT: .cfi_offset w29, -16
1616
; CHECK-NEXT: ptrue p0.d
17-
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
18-
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #2, mul vl]
19-
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0, #1, mul vl]
20-
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
21-
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #2, mul vl]
22-
; CHECK-NEXT: st1d { z2.d }, p0, [sp, #1, mul vl]
17+
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #2, mul vl]
18+
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
19+
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
20+
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
21+
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #1, mul vl]
22+
; CHECK-NEXT: st1d { z2.d }, p0, [sp]
2323
; CHECK-NEXT: addvl sp, sp, #3
2424
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
2525
; CHECK-NEXT: ret
@@ -81,18 +81,18 @@ define void @array_2D(ptr %addr) #0 {
8181
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 48 * VG
8282
; CHECK-NEXT: .cfi_offset w29, -16
8383
; CHECK-NEXT: ptrue p0.d
84-
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
85-
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #5, mul vl]
86-
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0, #1, mul vl]
87-
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x0, #4, mul vl]
88-
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x0, #2, mul vl]
89-
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x0, #3, mul vl]
90-
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
91-
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #5, mul vl]
92-
; CHECK-NEXT: st1d { z3.d }, p0, [sp, #4, mul vl]
93-
; CHECK-NEXT: st1d { z5.d }, p0, [sp, #3, mul vl]
94-
; CHECK-NEXT: st1d { z4.d }, p0, [sp, #2, mul vl]
95-
; CHECK-NEXT: st1d { z2.d }, p0, [sp, #1, mul vl]
84+
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #5, mul vl]
85+
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #4, mul vl]
86+
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
87+
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x0, #3, mul vl]
88+
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x0, #1, mul vl]
89+
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x0, #2, mul vl]
90+
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #5, mul vl]
91+
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #4, mul vl]
92+
; CHECK-NEXT: st1d { z3.d }, p0, [sp, #3, mul vl]
93+
; CHECK-NEXT: st1d { z5.d }, p0, [sp, #2, mul vl]
94+
; CHECK-NEXT: st1d { z4.d }, p0, [sp, #1, mul vl]
95+
; CHECK-NEXT: st1d { z2.d }, p0, [sp]
9696
; CHECK-NEXT: addvl sp, sp, #6
9797
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
9898
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,12 @@ define void @test(ptr %addr) #0 {
1313
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
1414
; CHECK-NEXT: .cfi_offset w29, -16
1515
; CHECK-NEXT: ptrue p0.d
16-
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
17-
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #2, mul vl]
18-
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0, #1, mul vl]
19-
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
20-
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #2, mul vl]
21-
; CHECK-NEXT: st1d { z2.d }, p0, [sp, #1, mul vl]
16+
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #2, mul vl]
17+
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
18+
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
19+
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
20+
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #1, mul vl]
21+
; CHECK-NEXT: st1d { z2.d }, p0, [sp]
2222
; CHECK-NEXT: addvl sp, sp, #3
2323
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
2424
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,15 +18,15 @@ define void @test(ptr %addr) {
1818
; CHECK-NEXT: add a2, a0, a1
1919
; CHECK-NEXT: vl1re64.v v8, (a2)
2020
; CHECK-NEXT: slli a2, a1, 1
21-
; CHECK-NEXT: vl1re64.v v9, (a0)
22-
; CHECK-NEXT: add a0, a0, a2
21+
; CHECK-NEXT: add a3, a0, a2
22+
; CHECK-NEXT: vl1re64.v v9, (a3)
2323
; CHECK-NEXT: vl1re64.v v10, (a0)
2424
; CHECK-NEXT: addi a0, sp, 16
25-
; CHECK-NEXT: vs1r.v v9, (a0)
2625
; CHECK-NEXT: add a2, a0, a2
27-
; CHECK-NEXT: vs1r.v v10, (a2)
28-
; CHECK-NEXT: add a0, a0, a1
29-
; CHECK-NEXT: vs1r.v v8, (a0)
26+
; CHECK-NEXT: vs1r.v v9, (a2)
27+
; CHECK-NEXT: add a1, a0, a1
28+
; CHECK-NEXT: vs1r.v v8, (a1)
29+
; CHECK-NEXT: vs1r.v v10, (a0)
3030
; CHECK-NEXT: csrrs a0, vlenb, zero
3131
; CHECK-NEXT: slli a0, a0, 2
3232
; CHECK-NEXT: add sp, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,13 @@ define <vscale x 1 x double> @test(ptr %addr, i64 %vl) {
1616
; CHECK-NEXT: sub sp, sp, a2
1717
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
1818
; CHECK-NEXT: csrrs a2, vlenb, zero
19-
; CHECK-NEXT: vl1re64.v v8, (a0)
20-
; CHECK-NEXT: add a0, a0, a2
19+
; CHECK-NEXT: add a3, a0, a2
20+
; CHECK-NEXT: vl1re64.v v8, (a3)
2121
; CHECK-NEXT: vl1re64.v v9, (a0)
2222
; CHECK-NEXT: addi a0, sp, 16
23-
; CHECK-NEXT: vs1r.v v8, (a0)
2423
; CHECK-NEXT: add a2, a0, a2
25-
; CHECK-NEXT: vs1r.v v9, (a2)
24+
; CHECK-NEXT: vs1r.v v8, (a2)
25+
; CHECK-NEXT: vs1r.v v9, (a0)
2626
; CHECK-NEXT: vl1re64.v v8, (a2)
2727
; CHECK-NEXT: vl1re64.v v9, (a0)
2828
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma

0 commit comments

Comments
 (0)