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[AMDGPU] Stop using make_pair and make_tuple. NFC.
C++17 allows us to call constructors pair and tuple instead of helper functions make_pair and make_tuple. Differential Revision: https://reviews.llvm.org/D139828
1 parent 847fa84 commit 6443c0e

37 files changed

+225
-246
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp‎

Lines changed: 35 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -91,61 +91,59 @@ AMDGPUFunctionArgInfo::getPreloadedValue(
9191
AMDGPUFunctionArgInfo::PreloadedValue Value) const {
9292
switch (Value) {
9393
case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
94-
return std::make_tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer
95-
: nullptr,
96-
&AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));
94+
return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
95+
&AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));
9796
}
9897
case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
99-
return std::make_tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
100-
&AMDGPU::SGPR_64RegClass,
101-
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
98+
return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
99+
&AMDGPU::SGPR_64RegClass,
100+
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
102101
case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
103-
return std::make_tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
104-
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
102+
return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
103+
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
105104
case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
106-
return std::make_tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
107-
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
105+
return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
106+
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
108107
case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
109-
return std::make_tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
110-
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
108+
return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
109+
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
111110
case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:
112-
return std::make_tuple(LDSKernelId ? &LDSKernelId : nullptr,
113-
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
111+
return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
112+
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
114113
case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
115-
return std::make_tuple(
114+
return std::tuple(
116115
PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
117116
&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
118117
case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:
119-
return std::make_tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
120-
&AMDGPU::SGPR_64RegClass,
121-
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
118+
return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
119+
&AMDGPU::SGPR_64RegClass,
120+
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
122121
case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:
123-
return std::make_tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
124-
&AMDGPU::SGPR_64RegClass,
125-
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
122+
return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
123+
&AMDGPU::SGPR_64RegClass,
124+
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
126125
case AMDGPUFunctionArgInfo::DISPATCH_ID:
127-
return std::make_tuple(DispatchID ? &DispatchID : nullptr,
128-
&AMDGPU::SGPR_64RegClass, LLT::scalar(64));
126+
return std::tuple(DispatchID ? &DispatchID : nullptr,
127+
&AMDGPU::SGPR_64RegClass, LLT::scalar(64));
129128
case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:
130-
return std::make_tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
131-
&AMDGPU::SGPR_64RegClass, LLT::scalar(64));
129+
return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
130+
&AMDGPU::SGPR_64RegClass, LLT::scalar(64));
132131
case AMDGPUFunctionArgInfo::DISPATCH_PTR:
133-
return std::make_tuple(DispatchPtr ? &DispatchPtr : nullptr,
134-
&AMDGPU::SGPR_64RegClass,
135-
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
132+
return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,
133+
&AMDGPU::SGPR_64RegClass,
134+
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
136135
case AMDGPUFunctionArgInfo::QUEUE_PTR:
137-
return std::make_tuple(QueuePtr ? &QueuePtr : nullptr,
138-
&AMDGPU::SGPR_64RegClass,
139-
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
136+
return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,
137+
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
140138
case AMDGPUFunctionArgInfo::WORKITEM_ID_X:
141-
return std::make_tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
142-
&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
139+
return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
140+
&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
143141
case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:
144-
return std::make_tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
145-
&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
142+
return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
143+
&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
146144
case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
147-
return std::make_tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
148-
&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
145+
return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
146+
&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
149147
}
150148
llvm_unreachable("unexpected preloaded value type");
151149
}

‎llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -872,7 +872,7 @@ static std::pair<Value*, Value*> getMul64(IRBuilder<> &Builder,
872872
Value *Lo = Builder.CreateTrunc(MUL64, I32Ty);
873873
Value *Hi = Builder.CreateLShr(MUL64, Builder.getInt64(32));
874874
Hi = Builder.CreateTrunc(Hi, I32Ty);
875-
return std::make_pair(Lo, Hi);
875+
return std::pair(Lo, Hi);
876876
}
877877

878878
static Value* getMulHu(IRBuilder<> &Builder, Value *LHS, Value *RHS) {

‎llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -28,24 +28,24 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
2828
else
2929
Offset = Op.getCImm()->getZExtValue();
3030

31-
return std::make_pair(Register(), Offset);
31+
return std::pair(Register(), Offset);
3232
}
3333

3434
int64_t Offset;
3535
if (Def->getOpcode() == TargetOpcode::G_ADD) {
3636
// TODO: Handle G_OR used for add case
3737
if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
38-
return std::make_pair(Def->getOperand(1).getReg(), Offset);
38+
return std::pair(Def->getOperand(1).getReg(), Offset);
3939

4040
// FIXME: matcher should ignore copies
4141
if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
42-
return std::make_pair(Def->getOperand(1).getReg(), Offset);
42+
return std::pair(Def->getOperand(1).getReg(), Offset);
4343
}
4444

4545
Register Base;
4646
if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
4747
KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
48-
return std::make_pair(Base, Offset);
48+
return std::pair(Base, Offset);
4949

5050
// Handle G_PTRTOINT (G_PTR_ADD base, const) case
5151
if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
@@ -54,14 +54,14 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
5454
m_GPtrAdd(m_MInstr(Base), m_ICst(Offset)))) {
5555
// If Base was int converted to pointer, simply return int and offset.
5656
if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
57-
return std::make_pair(Base->getOperand(1).getReg(), Offset);
57+
return std::pair(Base->getOperand(1).getReg(), Offset);
5858

5959
// Register returned here will be of pointer type.
60-
return std::make_pair(Base->getOperand(0).getReg(), Offset);
60+
return std::pair(Base->getOperand(0).getReg(), Offset);
6161
}
6262
}
6363

64-
return std::make_pair(Reg, 0);
64+
return std::pair(Reg, 0);
6565
}
6666

6767
bool AMDGPU::hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget,

‎llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ static std::pair<Type *, Align> getArgumentTypeAlign(const Argument &Arg,
3333
if (!ArgAlign)
3434
ArgAlign = DL.getABITypeAlign(Ty);
3535

36-
return std::make_pair(Ty, *ArgAlign);
36+
return std::pair(Ty, *ArgAlign);
3737
}
3838

3939
namespace llvm {

‎llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,7 @@ void PipelineSolver::convertSyncMapsToArrays() {
347347
for (auto &SUsToCandSGs : SyncInstrMap.second) {
348348
if (PipelineInstrs[PipelineIDx].size() == 0) {
349349
PipelineInstrs[PipelineIDx].push_back(
350-
std::make_pair(SUsToCandSGs.first, SUsToCandSGs.second));
350+
std::pair(SUsToCandSGs.first, SUsToCandSGs.second));
351351
continue;
352352
}
353353
auto SortPosition = PipelineInstrs[PipelineIDx].begin();
@@ -357,8 +357,7 @@ void PipelineSolver::convertSyncMapsToArrays() {
357357
SUsToCandSGs.first->NodeNum > SortPosition->first->NodeNum)
358358
++SortPosition;
359359
PipelineInstrs[PipelineIDx].insert(
360-
SortPosition,
361-
std::make_pair(SUsToCandSGs.first, SUsToCandSGs.second));
360+
SortPosition, std::pair(SUsToCandSGs.first, SUsToCandSGs.second));
362361
}
363362
--PipelineIDx;
364363
}
@@ -508,15 +507,15 @@ void PipelineSolver::populateReadyList(
508507

509508
if (UseCostHeur) {
510509
if (Match->isFull()) {
511-
ReadyList.push_back(std::make_pair(*I, MissPenalty));
510+
ReadyList.push_back(std::pair(*I, MissPenalty));
512511
continue;
513512
}
514513

515514
int TempCost = addEdges(SyncPipeline, CurrSU.first, CandSGID, AddedEdges);
516-
ReadyList.push_back(std::make_pair(*I, TempCost));
515+
ReadyList.push_back(std::pair(*I, TempCost));
517516
removeEdges(AddedEdges);
518517
} else
519-
ReadyList.push_back(std::make_pair(*I, -1));
518+
ReadyList.push_back(std::pair(*I, -1));
520519
}
521520

522521
if (UseCostHeur) {
@@ -913,7 +912,7 @@ int SchedGroup::link(SUnit &SU, bool MakePred,
913912
// the A->B edge impossible, otherwise it returns true;
914913
bool Added = tryAddEdge(A, B);
915914
if (Added)
916-
AddedEdges.push_back(std::make_pair(A, B));
915+
AddedEdges.push_back(std::pair(A, B));
917916
else
918917
++MissedEdges;
919918
}

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1358,7 +1358,7 @@ std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const
13581358
// use constant 0 for soffset. This value must be retained until
13591359
// frame elimination and eliminateFrameIndex will choose the appropriate
13601360
// frame register if need be.
1361-
return std::make_pair(TFI, CurDAG->getTargetConstant(0, DL, MVT::i32));
1361+
return std::pair(TFI, CurDAG->getTargetConstant(0, DL, MVT::i32));
13621362
}
13631363

13641364
bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Parent,

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1473,7 +1473,7 @@ AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
14731473
SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
14741474
SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
14751475

1476-
return std::make_pair(Lo, Hi);
1476+
return std::pair(Lo, Hi);
14771477
}
14781478

14791479
SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
@@ -1505,7 +1505,7 @@ AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
15051505
HiVT = NumElts - LoNumElts == 1
15061506
? EltVT
15071507
: EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts - LoNumElts);
1508-
return std::make_pair(LoVT, HiVT);
1508+
return std::pair(LoVT, HiVT);
15091509
}
15101510

15111511
// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
@@ -1523,7 +1523,7 @@ AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
15231523
SDValue Hi = DAG.getNode(
15241524
HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL,
15251525
HiVT, N, DAG.getVectorIdxConstant(LoVT.getVectorNumElements(), DL));
1526-
return std::make_pair(Lo, Hi);
1526+
return std::pair(Lo, Hi);
15271527
}
15281528

15291529
SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2914,8 +2914,8 @@ computeIndirectRegIndex(MachineRegisterInfo &MRI, const SIRegisterInfo &TRI,
29142914
// Skip out of bounds offsets, or else we would end up using an undefined
29152915
// register.
29162916
if (static_cast<unsigned>(Offset) >= SubRegs.size())
2917-
return std::make_pair(IdxReg, SubRegs[0]);
2918-
return std::make_pair(IdxBaseReg, SubRegs[Offset]);
2917+
return std::pair(IdxReg, SubRegs[0]);
2918+
return std::pair(IdxBaseReg, SubRegs[Offset]);
29192919
}
29202920

29212921
bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
@@ -3526,7 +3526,7 @@ std::pair<Register, unsigned> AMDGPUInstructionSelector::selectVOP3ModsImpl(
35263526
if (OpSel)
35273527
Mods |= SISrcMods::OP_SEL_0;
35283528

3529-
return std::make_pair(Src, Mods);
3529+
return std::pair(Src, Mods);
35303530
}
35313531

35323532
Register AMDGPUInstructionSelector::copyToVGPRIfSrcFolded(
@@ -3659,7 +3659,7 @@ AMDGPUInstructionSelector::selectVOP3PModsImpl(
36593659
// Packed instructions do not have abs modifiers.
36603660
Mods |= SISrcMods::OP_SEL_1;
36613661

3662-
return std::make_pair(Src, Mods);
3662+
return std::pair(Src, Mods);
36633663
}
36643664

36653665
InstructionSelector::ComplexRendererFns
@@ -3894,7 +3894,7 @@ AMDGPUInstructionSelector::selectFlatOffsetImpl(MachineOperand &Root,
38943894
uint64_t FlatVariant) const {
38953895
MachineInstr *MI = Root.getParent();
38963896

3897-
auto Default = std::make_pair(Root.getReg(), 0);
3897+
auto Default = std::pair(Root.getReg(), 0);
38983898

38993899
if (!STI.hasFlatInstOffsets())
39003900
return Default;
@@ -3910,7 +3910,7 @@ AMDGPUInstructionSelector::selectFlatOffsetImpl(MachineOperand &Root,
39103910
if (!TII.isLegalFLATOffset(ConstOffset, AddrSpace, FlatVariant))
39113911
return Default;
39123912

3913-
return std::make_pair(PtrBase, ConstOffset);
3913+
return std::pair(PtrBase, ConstOffset);
39143914
}
39153915

39163916
InstructionSelector::ComplexRendererFns
@@ -4374,7 +4374,7 @@ std::pair<Register, unsigned>
43744374
AMDGPUInstructionSelector::selectDS1Addr1OffsetImpl(MachineOperand &Root) const {
43754375
const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
43764376
if (!RootDef)
4377-
return std::make_pair(Root.getReg(), 0);
4377+
return std::pair(Root.getReg(), 0);
43784378

43794379
int64_t ConstAddr = 0;
43804380

@@ -4386,7 +4386,7 @@ AMDGPUInstructionSelector::selectDS1Addr1OffsetImpl(MachineOperand &Root) const
43864386
if (Offset) {
43874387
if (isDSOffsetLegal(PtrBase, Offset)) {
43884388
// (add n0, c0)
4389-
return std::make_pair(PtrBase, Offset);
4389+
return std::pair(PtrBase, Offset);
43904390
}
43914391
} else if (RootDef->getOpcode() == AMDGPU::G_SUB) {
43924392
// TODO
@@ -4397,7 +4397,7 @@ AMDGPUInstructionSelector::selectDS1Addr1OffsetImpl(MachineOperand &Root) const
43974397

43984398
}
43994399

4400-
return std::make_pair(Root.getReg(), 0);
4400+
return std::pair(Root.getReg(), 0);
44014401
}
44024402

44034403
InstructionSelector::ComplexRendererFns
@@ -4439,7 +4439,7 @@ AMDGPUInstructionSelector::selectDSReadWrite2Impl(MachineOperand &Root,
44394439
unsigned Size) const {
44404440
const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
44414441
if (!RootDef)
4442-
return std::make_pair(Root.getReg(), 0);
4442+
return std::pair(Root.getReg(), 0);
44434443

44444444
int64_t ConstAddr = 0;
44454445

@@ -4453,7 +4453,7 @@ AMDGPUInstructionSelector::selectDSReadWrite2Impl(MachineOperand &Root,
44534453
int64_t OffsetValue1 = Offset + Size;
44544454
if (isDSOffset2Legal(PtrBase, OffsetValue0, OffsetValue1, Size)) {
44554455
// (add n0, c0)
4456-
return std::make_pair(PtrBase, OffsetValue0 / Size);
4456+
return std::pair(PtrBase, OffsetValue0 / Size);
44574457
}
44584458
} else if (RootDef->getOpcode() == AMDGPU::G_SUB) {
44594459
// TODO
@@ -4463,7 +4463,7 @@ AMDGPUInstructionSelector::selectDSReadWrite2Impl(MachineOperand &Root,
44634463

44644464
}
44654465

4466-
return std::make_pair(Root.getReg(), 0);
4466+
return std::pair(Root.getReg(), 0);
44674467
}
44684468

44694469
/// If \p Root is a G_PTR_ADD with a G_CONSTANT on the right hand side, return

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