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luciechoiluciechoi
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Add more unit tests for resource types
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3 files changed

+55
-48
lines changed

3 files changed

+55
-48
lines changed

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 28 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -367,9 +367,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
367367
MachineInstr &I) const;
368368
bool loadHandleBeforePosition(Register &HandleReg, const SPIRVType *ResType,
369369
GIntrinsic &HandleDef, MachineInstr &Pos) const;
370-
void recursivelyDecorateChildAsNonUniform(Register &NonUniformReg,
371-
const SPIRVType *RegType,
372-
MachineInstr &I) const;
370+
void decorateUsesAsNonUniform(Register &NonUniformReg) const;
373371
};
374372

375373
bool sampledTypeIsSignedInteger(const llvm::Type *HandleType) {
@@ -3734,41 +3732,38 @@ bool SPIRVInstructionSelector::selectResourceNonUniformIndex(
37343732
// load/store/sample/atomic must be decorated, so we need to propagate the
37353733
// decoration through access chains and copies.
37363734
// https://docs.vulkan.org/samples/latest/samples/extensions/descriptor_indexing/README.html#_when_to_use_non_uniform_indexing_qualifier
3737-
recursivelyDecorateChildAsNonUniform(ResVReg, ResType, I);
3735+
decorateUsesAsNonUniform(ResVReg);
37383736
return true;
37393737
}
37403738

3741-
void SPIRVInstructionSelector::recursivelyDecorateChildAsNonUniform(
3742-
Register &NonUniformReg, const SPIRVType *RegType, MachineInstr &I) const {
3743-
std::vector<std::tuple<Register, const SPIRVType *, MachineInstr *>> WorkList;
3744-
bool isDecorated = false;
3745-
for (MachineInstr &Use :
3746-
RegType->getMF()->getRegInfo().use_instructions(NonUniformReg)) {
3747-
if (Use.getOpcode() != SPIRV::OpDecorate &&
3748-
Use.getOpcode() != SPIRV::OpAccessChain &&
3749-
Use.getOpcode() != SPIRV::OpCopyObject &&
3750-
Use.getOpcode() != SPIRV::OpLoad)
3751-
continue;
3752-
3753-
if (Use.getOpcode() == SPIRV::OpDecorate &&
3754-
Use.getOperand(1).getImm() == SPIRV::Decoration::NonUniformEXT) {
3755-
isDecorated = true;
3756-
continue;
3739+
void SPIRVInstructionSelector::decorateUsesAsNonUniform(
3740+
Register &NonUniformReg) const {
3741+
std::vector<Register> WorkList = {NonUniformReg};
3742+
while (WorkList.size() > 0) {
3743+
Register CurrentReg = WorkList.at(0);
3744+
WorkList.erase(WorkList.begin());
3745+
3746+
bool isDecorated = false;
3747+
for (MachineInstr &Use : MRI->use_instructions(CurrentReg)) {
3748+
if (Use.getOpcode() == SPIRV::OpDecorate &&
3749+
Use.getOperand(1).getImm() == SPIRV::Decoration::NonUniformEXT) {
3750+
isDecorated = true;
3751+
continue;
3752+
}
3753+
// Check if the instruction has the result register and add it to the
3754+
// worklist.
3755+
if (Use.getOperand(0).isReg() && Use.getOperand(0).isDef()) {
3756+
Register ResultReg = Use.getOperand(0).getReg();
3757+
if (ResultReg == CurrentReg)
3758+
continue;
3759+
WorkList.push_back(ResultReg);
3760+
}
37573761
}
37583762

3759-
Register ResultReg = Use.getOperand(0).getReg();
3760-
SPIRVType *ResultType = GR.getResultType(ResultReg);
3761-
WorkList.push_back(std::make_tuple(ResultReg, ResultType, &Use));
3762-
}
3763-
3764-
if (!isDecorated) {
3765-
buildOpDecorate(NonUniformReg, I, TII, SPIRV::Decoration::NonUniformEXT,
3766-
{});
3767-
}
3768-
3769-
for (auto &Item : WorkList) {
3770-
recursivelyDecorateChildAsNonUniform(std::get<0>(Item), std::get<1>(Item),
3771-
*std::get<2>(Item));
3763+
if (!isDecorated) {
3764+
buildOpDecorate(CurrentReg, *MRI->getVRegDef(CurrentReg), TII,
3765+
SPIRV::Decoration::NonUniformEXT, {});
3766+
}
37723767
}
37733768
return;
37743769
}

‎llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll‎ renamed to ‎llvm/test/CodeGen/SPIRV/hlsl-resources/NonUniformIdx/RWStructuredBufferNonUniformIdx.ll‎

Lines changed: 3 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,31 +8,19 @@
88
; CHECK-DAG: OpDecorate {{%[0-9]+}} NonUniformEXT
99
; CHECK-DAG: OpDecorate {{%[0-9]+}} NonUniformEXT
1010
; CHECK-DAG: OpDecorate %[[#access1:]] NonUniformEXT
11-
@StructuredOut.str = private unnamed_addr constant [14 x i8] c"StructuredOut\00", align 1
12-
; CHECK-DAG: OpDecorate {{%[0-9]+}} NonUniformEXT
13-
; CHECK-DAG: OpDecorate {{%[0-9]+}} NonUniformEXT
14-
; CHECK-DAG: OpDecorate {{%[0-9]+}} NonUniformEXT
15-
; CHECK-DAG: OpDecorate %[[#access2:]] NonUniformEXT
16-
; CHECK-DAG: OpDecorate %[[#load:]] NonUniformEXT
17-
@UnStructuredOut.str = private unnamed_addr constant [16 x i8] c"UnStructuredOut\00", align 1
11+
@ReadWriteStructuredBuf.str = private unnamed_addr constant [23 x i8] c"ReadWriteStructuredBuf\00", align 1
1812

1913
define void @main() local_unnamed_addr #0 {
2014
entry:
2115
%0 = tail call i32 @llvm.spv.thread.id.in.group.i32(i32 0)
2216
%add.i = add i32 %0, 1
2317
%1 = tail call noundef i32 @llvm.spv.resource.nonuniformindex(i32 %add.i)
24-
%2 = tail call target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) @llvm.spv.resource.handlefromimplicitbinding.tspirv.VulkanBuffer_a0v4i32_12_1t(i32 0, i32 0, i32 64, i32 %1, ptr nonnull @StructuredOut.str)
18+
%2 = tail call target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) @llvm.spv.resource.handlefromimplicitbinding.tspirv.VulkanBuffer_a0v4i32_12_1t(i32 0, i32 0, i32 64, i32 %1, ptr nonnull @ReadWriteStructuredBuf.str)
2519
%3 = tail call noundef align 16 dereferenceable(16) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0v4i32_12_1t(target("spirv.VulkanBuffer", [0 x <4 x i32>], 12, 1) %2, i32 98)
2620
%4 = load <4 x i32>, ptr addrspace(11) %3, align 16
2721
%vecins.i = insertelement <4 x i32> %4, i32 99, i64 0
22+
; CHECK: %[[#access1]] = OpAccessChain {{.*}}
2823
; CHECK: OpStore %[[#access1]] {{%[0-9]+}} Aligned 16
2924
store <4 x i32> %vecins.i, ptr addrspace(11) %3, align 16
30-
%5 = tail call noundef i32 @llvm.spv.resource.nonuniformindex(i32 %0)
31-
%6 = tail call target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) @llvm.spv.resource.handlefromimplicitbinding.tspirv.Image_i32_5_2_0_0_2_33t(i32 1, i32 0, i32 64, i32 %5, ptr nonnull @UnStructuredOut.str)
32-
%7 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_2_33t(target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) %6, i32 96)
33-
; CHECK: %[[#access2:]] = OpAccessChain {{.*}}
34-
; CHECK: %[[#load]] = OpLoad {{.*}}
35-
; CHECK: OpImageWrite %[[#load]] {{%[0-9]+}} {{%[0-9]+}}
36-
store i32 95, ptr addrspace(11) %7, align 4
3725
ret void
3826
}

‎llvm/test/CodeGen/SPIRV/hlsl-resources/NonUniformIdx/StructuredBufferNonUniformIdx.ll‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
; RUN: llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - | FileCheck %s --match-full-lines
2+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val %}
3+
4+
; CHECK-DAG: OpCapability Shader
5+
; CHECK-DAG: OpCapability ShaderNonUniformEXT
6+
; CHECK-DAG: OpCapability StorageTexelBufferArrayNonUniformIndexingEXT
7+
; CHECK-DAG: OpDecorate {{%[0-9]+}} NonUniformEXT
8+
; CHECK-DAG: OpDecorate %[[#access:]] NonUniformEXT
9+
; CHECK-DAG: OpDecorate %[[#load:]] NonUniformEXT
10+
@ReadWriteBuf.str = private unnamed_addr constant [13 x i8] c"ReadWriteBuf\00", align 1
11+
12+
define void @main() local_unnamed_addr #0 {
13+
entry:
14+
%0 = tail call i32 @llvm.spv.thread.id.in.group.i32(i32 0)
15+
%1 = tail call noundef i32 @llvm.spv.resource.nonuniformindex(i32 %0)
16+
%2 = tail call target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) @llvm.spv.resource.handlefromimplicitbinding.tspirv.Image_i32_5_2_0_0_2_33t(i32 0, i32 0, i32 64, i32 %1, ptr nonnull @ReadWriteBuf.str)
17+
%3 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_i32_5_2_0_0_2_33t(target("spirv.Image", i32, 5, 2, 0, 0, 2, 33) %2, i32 96)
18+
; CHECK: {{%[0-9]+}} = OpCompositeExtract {{.*}}
19+
; CHECK: %[[#access]] = OpAccessChain {{.*}}
20+
; CHECK: %[[#load]] = OpLoad {{%[0-9]+}} %[[#access]]
21+
; CHECK: OpImageWrite %[[#load]] {{%[0-9]+}} {{%[0-9]+}}
22+
store i32 95, ptr addrspace(11) %3, align 4
23+
ret void
24+
}

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