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KanRobertKanRobert
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[X86][NFC] Remove unnecessary parameters for MaskedShiftAmountPats/MaskedRotateAmountPats and rename one_bit_patterns
This patch is to extract NFC in #78853 into a separate commit.
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‎llvm/lib/Target/X86/X86InstrCompiler.td‎

Lines changed: 46 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1787,63 +1787,62 @@ let Predicates = [HasNDD] in {
17871787
}
17881788

17891789
// Shift amount is implicitly masked.
1790-
multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1790+
multiclass MaskedShiftAmountPats<SDNode frag> {
17911791
// (shift x (and y, 31)) ==> (shift x, y)
17921792
def : Pat<(frag GR8:$src1, (shiftMask32 CL)),
1793-
(!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1793+
(!cast<Instruction>(NAME # "8rCL") GR8:$src1)>;
17941794
def : Pat<(frag GR16:$src1, (shiftMask32 CL)),
1795-
(!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1795+
(!cast<Instruction>(NAME # "16rCL") GR16:$src1)>;
17961796
def : Pat<(frag GR32:$src1, (shiftMask32 CL)),
1797-
(!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1797+
(!cast<Instruction>(NAME # "32rCL") GR32:$src1)>;
17981798
def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst),
1799-
(!cast<Instruction>(name # "8mCL") addr:$dst)>;
1799+
(!cast<Instruction>(NAME # "8mCL") addr:$dst)>;
18001800
def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst),
1801-
(!cast<Instruction>(name # "16mCL") addr:$dst)>;
1801+
(!cast<Instruction>(NAME # "16mCL") addr:$dst)>;
18021802
def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst),
1803-
(!cast<Instruction>(name # "32mCL") addr:$dst)>;
1803+
(!cast<Instruction>(NAME # "32mCL") addr:$dst)>;
18041804

18051805
// (shift x (and y, 63)) ==> (shift x, y)
18061806
def : Pat<(frag GR64:$src1, (shiftMask64 CL)),
1807-
(!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1807+
(!cast<Instruction>(NAME # "64rCL") GR64:$src1)>;
18081808
def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst),
1809-
(!cast<Instruction>(name # "64mCL") addr:$dst)>;
1809+
(!cast<Instruction>(NAME # "64mCL") addr:$dst)>;
18101810
}
18111811

1812-
defm : MaskedShiftAmountPats<shl, "SHL">;
1813-
defm : MaskedShiftAmountPats<srl, "SHR">;
1814-
defm : MaskedShiftAmountPats<sra, "SAR">;
1812+
defm SHL : MaskedShiftAmountPats<shl>;
1813+
defm SHR : MaskedShiftAmountPats<srl>;
1814+
defm SAR : MaskedShiftAmountPats<sra>;
18151815

18161816
// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and
18171817
// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount
18181818
// because over-rotating produces the same result. This is noted in the Intel
18191819
// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation
18201820
// amount could affect EFLAGS results, but that does not matter because we are
18211821
// not tracking flags for these nodes.
1822-
multiclass MaskedRotateAmountPats<SDNode frag, string name> {
1822+
multiclass MaskedRotateAmountPats<SDNode frag> {
18231823
// (rot x (and y, BitWidth - 1)) ==> (rot x, y)
18241824
def : Pat<(frag GR8:$src1, (shiftMask8 CL)),
1825-
(!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1825+
(!cast<Instruction>(NAME # "8rCL") GR8:$src1)>;
18261826
def : Pat<(frag GR16:$src1, (shiftMask16 CL)),
1827-
(!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1827+
(!cast<Instruction>(NAME # "16rCL") GR16:$src1)>;
18281828
def : Pat<(frag GR32:$src1, (shiftMask32 CL)),
1829-
(!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1829+
(!cast<Instruction>(NAME # "32rCL") GR32:$src1)>;
18301830
def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst),
1831-
(!cast<Instruction>(name # "8mCL") addr:$dst)>;
1831+
(!cast<Instruction>(NAME # "8mCL") addr:$dst)>;
18321832
def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst),
1833-
(!cast<Instruction>(name # "16mCL") addr:$dst)>;
1833+
(!cast<Instruction>(NAME # "16mCL") addr:$dst)>;
18341834
def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst),
1835-
(!cast<Instruction>(name # "32mCL") addr:$dst)>;
1835+
(!cast<Instruction>(NAME # "32mCL") addr:$dst)>;
18361836

18371837
// (rot x (and y, 63)) ==> (rot x, y)
18381838
def : Pat<(frag GR64:$src1, (shiftMask64 CL)),
1839-
(!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1839+
(!cast<Instruction>(NAME # "64rCL") GR64:$src1)>;
18401840
def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst),
1841-
(!cast<Instruction>(name # "64mCL") addr:$dst)>;
1841+
(!cast<Instruction>(NAME # "64mCL") addr:$dst)>;
18421842
}
18431843

1844-
1845-
defm : MaskedRotateAmountPats<rotl, "ROL">;
1846-
defm : MaskedRotateAmountPats<rotr, "ROR">;
1844+
defm ROL : MaskedRotateAmountPats<rotl>;
1845+
defm ROR : MaskedRotateAmountPats<rotr>;
18471846

18481847
// Double "funnel" shift amount is implicitly masked.
18491848
// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32)
@@ -1865,34 +1864,33 @@ def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)),
18651864
(SHRD64rrCL GR64:$src1, GR64:$src2)>;
18661865

18671866
// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location.
1868-
multiclass one_bit_patterns<RegisterClass RC, ValueType VT, Instruction BTR,
1869-
Instruction BTS, Instruction BTC,
1870-
PatFrag ShiftMask> {
1871-
def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)),
1872-
(BTR RC:$src1,
1873-
(INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1874-
def : Pat<(or RC:$src1, (shl 1, GR8:$src2)),
1875-
(BTS RC:$src1,
1876-
(INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1877-
def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)),
1878-
(BTC RC:$src1,
1879-
(INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1867+
multiclass OneBitPats<RegisterClass rc, ValueType vt, Instruction btr,
1868+
Instruction bts, Instruction btc, PatFrag mask> {
1869+
def : Pat<(and rc:$src1, (rotl -2, GR8:$src2)),
1870+
(btr rc:$src1,
1871+
(INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1872+
def : Pat<(or rc:$src1, (shl 1, GR8:$src2)),
1873+
(bts rc:$src1,
1874+
(INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1875+
def : Pat<(xor rc:$src1, (shl 1, GR8:$src2)),
1876+
(btc rc:$src1,
1877+
(INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
18801878

18811879
// Similar to above, but removing unneeded masking of the shift amount.
1882-
def : Pat<(and RC:$src1, (rotl -2, (ShiftMask GR8:$src2))),
1883-
(BTR RC:$src1,
1884-
(INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1885-
def : Pat<(or RC:$src1, (shl 1, (ShiftMask GR8:$src2))),
1886-
(BTS RC:$src1,
1887-
(INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1888-
def : Pat<(xor RC:$src1, (shl 1, (ShiftMask GR8:$src2))),
1889-
(BTC RC:$src1,
1890-
(INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1880+
def : Pat<(and rc:$src1, (rotl -2, (mask GR8:$src2))),
1881+
(btr rc:$src1,
1882+
(INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1883+
def : Pat<(or rc:$src1, (shl 1, (mask GR8:$src2))),
1884+
(bts rc:$src1,
1885+
(INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1886+
def : Pat<(xor rc:$src1, (shl 1, (mask GR8:$src2))),
1887+
(btc rc:$src1,
1888+
(INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
18911889
}
18921890

1893-
defm : one_bit_patterns<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>;
1894-
defm : one_bit_patterns<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>;
1895-
defm : one_bit_patterns<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>;
1891+
defm : OneBitPats<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>;
1892+
defm : OneBitPats<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>;
1893+
defm : OneBitPats<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>;
18961894

18971895
//===----------------------------------------------------------------------===//
18981896
// EFLAGS-defining Patterns

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