@@ -197,6 +197,8 @@ for.end:
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define void @bug18724 (i1 %cond ) {
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; UNROLL-LABEL: @bug18724(
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; UNROLL-NEXT: entry:
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+ ; UNROLL-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
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+ ; UNROLL-NEXT: call void @llvm.assume(i1 [[TMP0]])
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; UNROLL-NEXT: br label [[FOR_BODY14:%.*]]
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; UNROLL: for.body14:
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; UNROLL-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ]
@@ -211,6 +213,9 @@ define void @bug18724(i1 %cond) {
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; UNROLL: for.inc23:
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; UNROLL-NEXT: [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ]
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; UNROLL-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1
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+ ; UNROLL-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV3]] to i32
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+ ; UNROLL-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP1]], 0
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+ ; UNROLL-NEXT: call void @llvm.assume(i1 [[CMP13]])
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; UNROLL-NEXT: br label [[FOR_BODY14]]
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;
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; UNROLL-NOSIMPLIFY-LABEL: @bug18724(
@@ -287,6 +292,8 @@ define void @bug18724(i1 %cond) {
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;
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; VEC-LABEL: @bug18724(
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; VEC-NEXT: entry:
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+ ; VEC-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
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+ ; VEC-NEXT: call void @llvm.assume(i1 [[TMP0]])
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; VEC-NEXT: br label [[FOR_BODY14:%.*]]
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; VEC: for.body14:
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; VEC-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ]
@@ -301,6 +308,9 @@ define void @bug18724(i1 %cond) {
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; VEC: for.inc23:
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; VEC-NEXT: [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ]
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; VEC-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1
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+ ; VEC-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV3]] to i32
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+ ; VEC-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP1]], 0
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+ ; VEC-NEXT: call void @llvm.assume(i1 [[CMP13]])
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; VEC-NEXT: br label [[FOR_BODY14]]
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;
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entry:
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