diff --git a/integration_test/Bindings/Python/dialects/seq.py b/integration_test/Bindings/Python/dialects/seq.py
index db37bcc9bdaf..27cb8162a999 100644
--- a/integration_test/Bindings/Python/dialects/seq.py
+++ b/integration_test/Bindings/Python/dialects/seq.py
@@ -85,7 +85,7 @@ def top(module):
   # CHECK-LABEL: === Verilog ===
   print("=== Verilog ===")
 
-  pm = PassManager.parse("builtin.module(lower-seq-to-sv)")
+  pm = PassManager.parse("builtin.module(lower-seq-to-sv,canonicalize)")
   pm.run(m.operation)
   # CHECK: always_ff @(posedge clk)
   # CHECK: my_reg <= {{.+}}
diff --git a/llvm b/llvm
index a527248a3c2d..ddf40e0132cd 160000
--- a/llvm
+++ b/llvm
@@ -1 +1 @@
-Subproject commit a527248a3c2d638b0c92a06992f3f1c1f80842ad
+Subproject commit ddf40e0132cdfb9443e8dce9ca18d4f5595fb73c