Merge pull request #74 from VOGL-electronic/move_LiteXModule

move to LiteXModule

Author: enjoy-digital

litespi/__init__.py

@@ -6,9 +6,9 @@
 
 from migen import *
 
-from litex.soc.integration.doc import AutoDoc
-from litex.soc.interconnect import wishbone, stream
-from litex.soc.interconnect.csr import *
+from litex.gen import *
+
+from litex.soc.interconnect import stream
 
 from litespi.common import *
 from litespi.crossbar import LiteSPICrossbar
@@ -23,7 +23,7 @@ def __init__(self):
         self.cs     = Signal()
 
 
-class LiteSPI(Module, AutoCSR, AutoDoc):
+class LiteSPI(LiteXModule):
     """SPI Controller wrapper.
 
     The ``LiteSPI`` class provides a wrapper that can instantiate both ``LiteSPIMMAP`` and ``LiteSPIMaster`` and connect them to the PHY.
@@ -73,11 +73,11 @@ def __init__(self, phy, clock_domain="sys",
         with_master=True, master_tx_fifo_depth=1, master_rx_fifo_depth=1,
         with_csr=True, with_mmap_write=False):
 
-        self.submodules.crossbar = crossbar = LiteSPICrossbar(clock_domain)
+        self.crossbar = crossbar = LiteSPICrossbar(clock_domain)
         self.comb += phy.cs.eq(crossbar.cs)
 
         if with_mmap:
-            self.submodules.mmap = mmap = LiteSPIMMAP(flash=phy.flash,
+            self.mmap = mmap = LiteSPIMMAP(flash=phy.flash,
                                                       endianness=mmap_endianness,
                                                       with_csr=with_csr,
                                                       with_write=with_mmap_write)
@@ -90,7 +90,7 @@ def __init__(self, phy, clock_domain="sys",
             if hasattr(phy, "dummy_bits"):
                 self.comb += phy.dummy_bits.eq(mmap._spi_dummy_bits)
         if with_master:
-            self.submodules.master = master = LiteSPIMaster(
+            self.master = master = LiteSPIMaster(
                 tx_fifo_depth = master_tx_fifo_depth,
                 rx_fifo_depth = master_rx_fifo_depth)
             port_master = crossbar.get_port(master.cs)

litespi/clkgen.py

@@ -6,11 +6,11 @@
 
 from migen import *
 
-from litex.soc.integration.doc import AutoDoc, ModuleDoc
+from litex.gen import *
 
 from litex.build.io import SDROutput, DDROutput
 
-class DDRLiteSPIClkGen(Module, AutoDoc):
+class DDRLiteSPIClkGen(LiteXModule):
     """SPI Clock generator
 
     The ``DDRLiteSPIClkGen`` class provides a generic SPI clock generator.
@@ -33,7 +33,7 @@ def __init__(self, pads):
         self.specials += DDROutput(i1=en, i2=0, o=pads.clk)
 
 
-class LiteSPIClkGen(Module, AutoDoc):
+class LiteSPIClkGen(LiteXModule):
     """SPI Clock generator
 
     The ``LiteSPIClkGen`` class provides a generic SPI clock generator.

litespi/core/master.py

@@ -5,15 +5,16 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
-from migen.genlib.fsm import FSM, NextState
+
+from litex.gen import *
 
 from litex.soc.interconnect import stream
 from litex.soc.interconnect.csr import *
 
 from litespi.common import *
 
 
-class LiteSPIMaster(Module, AutoCSR):
+class LiteSPIMaster(LiteXModule):
     """Generic LiteSPI Master
 
     The ``LiteSPIMaster`` class provides a generic SPI master that can be controlled using CSRs.
@@ -61,9 +62,8 @@ def __init__(self, cs_width=1, tx_fifo_depth=1, rx_fifo_depth=1):
         # # #
 
         # FIFOs.
-        tx_fifo = stream.SyncFIFO(spi_core2phy_layout, depth=tx_fifo_depth)
-        rx_fifo = stream.SyncFIFO(spi_phy2core_layout, depth=rx_fifo_depth)
-        self.submodules += tx_fifo, rx_fifo
+        self.tx_fifo = tx_fifo = stream.SyncFIFO(spi_core2phy_layout, depth=tx_fifo_depth)
+        self.rx_fifo = rx_fifo = stream.SyncFIFO(spi_phy2core_layout, depth=rx_fifo_depth)
         self.comb += self.sink.connect(rx_fifo.sink)
         self.comb += tx_fifo.source.connect(self.source)
 

litespi/core/mmap.py

@@ -7,6 +7,8 @@
 
 from migen import *
 
+from litex.gen import *
+
 from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect import wishbone, stream
@@ -29,7 +31,7 @@
     8: 0b11111111,
 }
 
-class LiteSPIMMAP(Module, AutoCSR):
+class LiteSPIMMAP(LiteXModule):
     """Memory-mapped SPI Flash controller.
 
     The ``LiteSPIMMAP`` class provides a Wishbone slave that must be connected to a LiteSPI PHY.
@@ -83,8 +85,7 @@ def __init__(self, flash, clock_domain="sys", endianness="big", with_csr=True, w
         # Burst Control.
         burst_cs      = Signal()
         burst_adr     = Signal(len(bus.adr), reset_less=True)
-        burst_timeout = WaitTimer(MMAP_DEFAULT_TIMEOUT)
-        self.submodules += burst_timeout
+        self.burst_timeout = burst_timeout = WaitTimer(MMAP_DEFAULT_TIMEOUT)
 
         write = Signal()
         write_enabled = Signal()
@@ -123,7 +124,7 @@ def __init__(self, flash, clock_domain="sys", endianness="big", with_csr=True, w
         self.data_write = Signal(32)
 
         # FSM.
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             # Keep CS active after Burst for Timeout.
             burst_timeout.wait.eq(1),

litespi/gen.py

@@ -83,7 +83,7 @@ def __init__(self, platform, module, mode="x4", rate="1:1", divisor="1",
         sim            = False
     ):
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = CRG(platform.request("clk"), platform.request("rst"))
+        self.crg = CRG(platform.request("clk"), platform.request("rst"))
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, clk_freq=int(1e6))
@@ -123,32 +123,28 @@ def print_supported_modules():
 
         if sim:
             from litespi.phy.model import LiteSPIPHYModel
-            spiflash_phy = LiteSPIPHYModel(spiflash_module, init=[i for i in range(16)]) # FIXME: Allow custom init?
-            self.submodules += spiflash_phy
+            self.spiflash_phy = spiflash_phy = LiteSPIPHYModel(spiflash_module, init=[i for i in range(16)]) # FIXME: Allow custom init?
         else:
             pads = self.platform.request("spiflash" if mode == "x1" else "spiflash4x")
-            spiflash_phy = LiteSPIPHY(
+            self.spiflash_phy = spiflash_phy = LiteSPIPHY(
                 pads            = pads,
                 flash           = spiflash_module,
                 device          = platform.device,
                 default_divisor = int(divisor),
                 rate            = rate
             )
-            self.submodules += spiflash_phy
-
 
         # SPI Flash Core / MMAP --------------------------------------------------------------------
 
         assert bus_standard in ["wishbone", "axi-lite"]
 
-        spiflash_core = LiteSPI(
+        self.spiflash_core = spiflash_core = LiteSPI(
             phy             = spiflash_phy,
             mmap_endianness = bus_endianness,
             with_master     = with_master,
             with_mmap       = True,
             with_csr        = False
         )
-        self.submodules += spiflash_core
 
         # Wishbone.
         if bus_standard == "wishbone":

litespi/phy/generic.py

@@ -5,22 +5,17 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
-from migen.genlib.cdc import MultiReg
 
-from litex.gen.genlib.misc import WaitTimer
+from litex.gen import *
 
 from litespi.common import *
 
-from litex.soc.interconnect.csr import *
-
-from litex.soc.integration.doc import AutoDoc
-
 from litespi.phy.generic_sdr import LiteSPISDRPHYCore
 from litespi.phy.generic_ddr import LiteSPIDDRPHYCore
 
 # LiteSPI PHY --------------------------------------------------------------------------------------
 
-class LiteSPIPHY(Module, AutoCSR, AutoDoc):
+class LiteSPIPHY(LiteXModule):
     """LiteSPI PHY instantiator
 
     The ``LiteSPIPHY`` class instantiate generic PHY - ``LiteSPIPHYCore`` that can be connected to the ``LiteSPICore``,
@@ -64,22 +59,22 @@ class LiteSPIPHY(Module, AutoCSR, AutoDoc):
     def __init__(self, pads, flash, device="xc7", clock_domain="sys", default_divisor=9, cs_delay=10, rate="1:1", extra_latency=0):
         assert rate in ["1:1", "1:2"]
         if rate == "1:1":
-            self.phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay)
+            phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay)
         if rate == "1:2":
-            self.phy = LiteSPIDDRPHYCore(pads, flash, cs_delay, extra_latency)
+            phy = LiteSPIDDRPHYCore(pads, flash, cs_delay, extra_latency)
 
         self.flash = flash
 
-        self.source = self.phy.source
-        self.sink   = self.phy.sink
-        self.cs     = self.phy.cs
+        self.source = phy.source
+        self.sink   = phy.sink
+        self.cs     = phy.cs
 
         # # #
 
         if clock_domain != "sys":
-            self.phy = ClockDomainsRenamer(clock_domain)(self.phy)
+            phy = ClockDomainsRenamer(clock_domain)(phy)
 
-        self.submodules.spiflash_phy = self.phy
+        self.spiflash_phy = phy
 
     def get_csrs(self):
         return self.spiflash_phy.get_csrs()

litespi/phy/generic_ddr.py

@@ -5,24 +5,21 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
-from migen.genlib.cdc import MultiReg
+
+from litex.gen import *
 
 from litex.gen.genlib.misc import WaitTimer
 
 from litespi.common import *
 from litespi.clkgen import DDRLiteSPIClkGen
 
 from litex.soc.interconnect import stream
-from litex.soc.interconnect.csr import *
 
 from litex.build.io import DDRTristate
 
-from litex.soc.integration.doc import AutoDoc
-
-
 # LiteSPI DDR PHY Core -----------------------------------------------------------------------------
 
-class LiteSPIDDRPHYCore(Module, AutoCSR, AutoDoc):
+class LiteSPIDDRPHYCore(LiteXModule):
     """LiteSPI PHY DDR instantiator
 
     The ``DDRLiteSPIPHYCore`` class provides a generic PHY that can be connected to the ``LiteSPICore``.
@@ -73,12 +70,11 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
             assert not flash.ddr
 
         # Clock Generator.
-        self.submodules.clkgen = clkgen = DDRLiteSPIClkGen(pads)
+        self.clkgen = clkgen = DDRLiteSPIClkGen(pads)
 
         # CS control.
-        cs_timer  = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
+        self.cs_timer = cs_timer  = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
         cs_enable = Signal()
-        self.submodules += cs_timer
         self.comb += cs_timer.wait.eq(self.cs)
         self.comb += cs_enable.eq(cs_timer.done)
         self.comb += pads.cs_n.eq(~cs_enable)
@@ -141,7 +137,7 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
         )
 
         # FSM.
-        self.submodules.fsm = fsm = FSM(reset_state="WAIT-CMD-DATA")
+        self.fsm = fsm = FSM(reset_state="WAIT-CMD-DATA")
         fsm.act("WAIT-CMD-DATA",
             # Stop Clk.
             NextValue(clkgen.en, 0),

litespi/phy/generic_sdr.py

@@ -7,6 +7,8 @@
 
 from migen import *
 
+from litex.gen import *
+
 from litex.gen.genlib.misc import WaitTimer
 
 from litespi.common import *
@@ -17,11 +19,9 @@
 
 from litex.build.io import SDROutput, SDRInput, SDRTristate
 
-from litex.soc.integration.doc import AutoDoc
-
 # LiteSPI PHY Core ---------------------------------------------------------------------------------
 
-class LiteSPISDRPHYCore(Module, AutoCSR, AutoDoc):
+class LiteSPISDRPHYCore(LiteXModule):
     """LiteSPI PHY instantiator
 
     The ``LiteSPIPHYCore`` class provides a generic PHY that can be connected to the ``LiteSPICore``.
@@ -88,13 +88,12 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
             assert not flash.ddr
 
         # Clock Generator.
-        self.submodules.clkgen = clkgen = LiteSPIClkGen(pads, device)
+        self.clkgen = clkgen = LiteSPIClkGen(pads, device)
         self.comb += clkgen.div.eq(spi_clk_divisor)
 
         # CS control.
-        cs_timer  = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
+        self.cs_timer = cs_timer  = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
         cs_enable = Signal()
-        self.submodules += cs_timer
         self.comb += cs_timer.wait.eq(self.cs)
         self.comb += cs_enable.eq(cs_timer.done)
         self.comb += pads.cs_n.eq(~cs_enable)
@@ -168,7 +167,7 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
         )
 
         # FSM.
-        self.submodules.fsm = fsm = FSM(reset_state="WAIT-CMD-DATA")
+        self.fsm = fsm = FSM(reset_state="WAIT-CMD-DATA")
         fsm.act("WAIT-CMD-DATA",
             # Wait for CS and a CMD from the Core.
             If(cs_enable & sink.valid,