Support for extended BLIF attributes

[gatecat]

Yosys supports several non-standard features of the BLIF specification that bring it more up to speed with a modern netlist format. Some other FPGA consumers of the BLIF format use this already.

For example the .cname feature could be used to give meaningful names for instances, e.g. an SRAM or IP block, that will be manually placed or at least you would like diagnostics and reporting for

Attributes on cells via the .attr feature could potentially be exposed via the Python API enabling e.g. querying cells with an attribute set to handle them specially.

Is there interest in this being added to Coriolis, or do you prefer to stick to the strict BLIF specification?

[jpc-lip6]

I may be wrong, but as far as I am concerned, the BLIF format is supported only because it's the output of Yosys.
So the reference is what Yosys supports. Is there truly use for BLIF outside of Yosys ?

I used the BLIF format as netlist input because it was easier to me than writing a Verilog (netlist only) parser. But eventually I will switch to that.

[gatecat]

There are a few other BLIF supporting tools like ABC but it sounds like, optionally supporting the non-standard but Yosys-supported BLIF features to get a nicer experience seems entirely reasonable.

[mithro]

FYI - The extended BLIF format is actually described at https://docs.verilogtorouting.org/en/latest/vpr/file_formats/

[jpc-lip6]

Thanks for pointig us out, Mithro, I was still on the dusty 1992 documentation. We will implement what's relevant to VLSI when I have a bit of spare time.