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linux/lakka/rpi: patch for scaled modes
ref: raspberrypi/linux#4636
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‎packages/linux/patches/Lakka-raspberrypi/add_support_for_scaled_modes_in_VEC.patch

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From 234cfe71ba316c9666ecd501b7df1a4b5bdb7c03 Mon Sep 17 00:00:00 2001
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From: Mateusz Kwiatkowski <[email protected]>
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Date: Mon, 11 Oct 2021 23:34:25 +0200
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Subject: [PATCH 1/2] drm/vc4: Add vertically scaled progressive modes for VEC
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The Raspberry Pi firmware, when configured to output progressive
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composite video, scales 720x480/720x576 framebuffer into a
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720x240/720x288 physical video mode.
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This commit adds support for replicating such behavior, as this provides
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square-ish virtual pixels, and some userland software rely on this.
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Signed-off-by: Mateusz Kwiatkowski <[email protected]>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 40 +++++++++++++++++++++
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drivers/gpu/drm/vc4/vc4_vec.c | 63 ++++++++++++++++++++++++++++++---
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2 files changed, 98 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
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index 7947cf47b6e13..96b60fb245982 100644
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -334,6 +334,42 @@ static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
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return 0;
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}
26+
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+static int vc4_plane_scaling_adj(struct drm_plane_state *pstate)
28+
+{
29+
+ struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
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+ struct drm_crtc_state *crtc_state;
31+
+
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+ crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
33+
+ pstate->crtc);
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+
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+ if (crtc_state->mode.hdisplay != crtc_state->adjusted_mode.hdisplay) {
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+ vc4_pstate->crtc_x =
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+ DIV_ROUND_CLOSEST(vc4_pstate->crtc_x *
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+ crtc_state->adjusted_mode.hdisplay,
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+ crtc_state->mode.hdisplay);
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+ vc4_pstate->crtc_w =
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+ DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *
42+
+ crtc_state->adjusted_mode.hdisplay,
43+
+ crtc_state->mode.hdisplay);
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+ }
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+
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+ if (crtc_state->mode.vdisplay != crtc_state->adjusted_mode.vdisplay) {
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+ vc4_pstate->crtc_y =
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+ DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *
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+ crtc_state->adjusted_mode.vdisplay,
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+ crtc_state->mode.vdisplay);
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+ vc4_pstate->crtc_h =
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+ DIV_ROUND_CLOSEST(vc4_pstate->crtc_h *
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+ crtc_state->adjusted_mode.vdisplay,
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+ crtc_state->mode.vdisplay);
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+ }
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+
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+ if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h)
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+ return -EINVAL;
59+
+
60+
+ return 0;
61+
+}
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+
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static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
64+
{
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struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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@@ -378,6 +414,10 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
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if (ret)
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return ret;
69+
70+
+ ret = vc4_plane_scaling_adj(state);
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+ if (ret)
72+
+ return ret;
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+
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vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
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vc4_state->crtc_w);
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vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
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diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
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index 255e5c6c48e04..14eb28c859eb4 100644
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--- a/drivers/gpu/drm/vc4/vc4_vec.c
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+++ b/drivers/gpu/drm/vc4/vc4_vec.c
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@@ -253,6 +253,7 @@ enum vc4_vec_tv_mode_id {
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struct vc4_vec_tv_mode {
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const struct drm_display_mode *interlaced_mode;
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const struct drm_display_mode *progressive_mode;
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+ const struct drm_display_mode *scaled_progressive_mode;
86+
u32 config0;
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u32 config1;
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u32 custom_freq;
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@@ -298,6 +299,12 @@ static const struct drm_display_mode drm_mode_240p = {
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240, 240 + 3, 240 + 3 + 3, 262, 0, 0)
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};
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+static const struct drm_display_mode drm_mode_scaled_480p = {
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+ DRM_MODE("720x480 (scaled)", DRM_MODE_TYPE_DRIVER, 2 * 13500,
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+ 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
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+ 2 * 240, 2 * (240 + 3), 2 * (240 + 3 + 3), 2 * 262, 0, 0)
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+};
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+
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static const struct drm_display_mode drm_mode_576i = {
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DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
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720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
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@@ -311,16 +318,24 @@ static const struct drm_display_mode drm_mode_288p = {
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288, 288 + 2, 288 + 2 + 3, 312, 0, 0)
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};
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+static const struct drm_display_mode drm_mode_scaled_576p = {
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+ DRM_MODE("720x576 (scaled)", DRM_MODE_TYPE_DRIVER, 2 * 13500,
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+ 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
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+ 2 * 288, 2 * (288 + 2), 2 * (288 + 2 + 3), 2 * 312, 0, 0)
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+};
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+
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static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
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[VC4_VEC_TV_MODE_NTSC] = {
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.interlaced_mode = &drm_mode_480i,
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.progressive_mode = &drm_mode_240p,
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+ .scaled_progressive_mode = &drm_mode_scaled_480p,
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.config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS,
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},
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[VC4_VEC_TV_MODE_NTSC_J] = {
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.interlaced_mode = &drm_mode_480i,
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.progressive_mode = &drm_mode_240p,
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+ .scaled_progressive_mode = &drm_mode_scaled_480p,
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.config0 = VEC_CONFIG0_NTSC_STD,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS,
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},
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@@ -328,6 +343,7 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
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/* NTSC with PAL chroma frequency */
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.interlaced_mode = &drm_mode_480i,
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.progressive_mode = &drm_mode_240p,
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+ .scaled_progressive_mode = &drm_mode_scaled_480p,
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.config0 = VEC_CONFIG0_NTSC_STD,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
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.custom_freq = 0x2a098acb,
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@@ -335,18 +351,21 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
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[VC4_VEC_TV_MODE_PAL] = {
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.interlaced_mode = &drm_mode_576i,
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.progressive_mode = &drm_mode_288p,
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+ .scaled_progressive_mode = &drm_mode_scaled_576p,
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.config0 = VEC_CONFIG0_PAL_BDGHI_STD,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS,
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},
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[VC4_VEC_TV_MODE_PAL_M] = {
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.interlaced_mode = &drm_mode_480i,
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.progressive_mode = &drm_mode_240p,
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+ .scaled_progressive_mode = &drm_mode_scaled_480p,
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.config0 = VEC_CONFIG0_PAL_M_STD,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS,
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},
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[VC4_VEC_TV_MODE_PAL_N] = {
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.interlaced_mode = &drm_mode_576i,
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.progressive_mode = &drm_mode_288p,
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+ .scaled_progressive_mode = &drm_mode_scaled_576p,
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.config0 = VEC_CONFIG0_PAL_N_STD,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS,
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},
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@@ -354,6 +373,7 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
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/* PAL-M with chroma frequency of regular PAL */
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.interlaced_mode = &drm_mode_480i,
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.progressive_mode = &drm_mode_240p,
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+ .scaled_progressive_mode = &drm_mode_scaled_480p,
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.config0 = VEC_CONFIG0_PAL_M_STD,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
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.custom_freq = 0x2a098acb,
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@@ -361,6 +381,7 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
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[VC4_VEC_TV_MODE_SECAM] = {
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.interlaced_mode = &drm_mode_576i,
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.progressive_mode = &drm_mode_288p,
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+ .scaled_progressive_mode = &drm_mode_scaled_576p,
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.config0 = VEC_CONFIG0_SECAM_STD,
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.config1 = VEC_CONFIG1_C_CVBS_CVBS,
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.custom_freq = 0x29c71c72,
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@@ -420,7 +441,9 @@ static void vc4_vec_connector_destroy(struct drm_connector *connector)
174+
static int vc4_vec_connector_get_modes(struct drm_connector *connector)
175+
{
176+
struct drm_connector_state *state = connector->state;
177+
- struct drm_display_mode *interlaced_mode, *progressive_mode;
178+
+ struct drm_display_mode *interlaced_mode;
179+
+ struct drm_display_mode *progressive_mode;
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+ struct drm_display_mode *scaled_progressive_mode;
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interlaced_mode =
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drm_mode_duplicate(connector->dev,
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@@ -428,24 +451,33 @@ static int vc4_vec_connector_get_modes(struct drm_connector *connector)
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progressive_mode =
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drm_mode_duplicate(connector->dev,
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vc4_vec_tv_modes[state->tv.mode].progressive_mode);
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- if (!interlaced_mode || !progressive_mode) {
189+
+ scaled_progressive_mode =
190+
+ drm_mode_duplicate(connector->dev,
191+
+ vc4_vec_tv_modes[state->tv.mode].scaled_progressive_mode);
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+ if (!interlaced_mode || !progressive_mode || !scaled_progressive_mode) {
193+
DRM_ERROR("Failed to create a new display mode\n");
194+
drm_mode_destroy(connector->dev, interlaced_mode);
195+
drm_mode_destroy(connector->dev, progressive_mode);
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+ drm_mode_destroy(connector->dev, scaled_progressive_mode);
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return -ENOMEM;
198+
}
199+
200+
if (connector->cmdline_mode.specified &&
201+
connector->cmdline_mode.refresh_specified &&
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- !connector->cmdline_mode.interlace)
203+
+ !connector->cmdline_mode.interlace) {
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/* progressive mode set at boot, let's make it preferred */
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- progressive_mode->type |= DRM_MODE_TYPE_PREFERRED;
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- else
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+ if (connector->cmdline_mode.yres > 300)
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+ scaled_progressive_mode->type |= DRM_MODE_TYPE_PREFERRED;
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+ else
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+ progressive_mode->type |= DRM_MODE_TYPE_PREFERRED;
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+ } else {
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/* otherwise, interlaced mode is preferred */
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interlaced_mode->type |= DRM_MODE_TYPE_PREFERRED;
214+
+ }
215+
216+
drm_mode_probed_add(connector, interlaced_mode);
217+
drm_mode_probed_add(connector, progressive_mode);
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+ drm_mode_probed_add(connector, scaled_progressive_mode);
219+
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return 1;
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}
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@@ -628,6 +660,27 @@ static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
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const struct drm_display_mode *reference_mode =
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vc4_vec_tv_modes[conn_state->tv.mode].interlaced_mode;
225+
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+ if (!(crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) &&
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+ crtc_state->adjusted_mode.vtotal > 312) {
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+ /* vertically scaled progressive mode */
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+ if (crtc_state->adjusted_mode.crtc_vdisplay % 2 != 0 ||
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+ crtc_state->adjusted_mode.crtc_vsync_start % 2 != 0 ||
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+ crtc_state->adjusted_mode.crtc_vsync_end % 2 != 0 ||
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+ crtc_state->adjusted_mode.crtc_vtotal % 2 != 0)
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+ return -EINVAL;
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+
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+ crtc_state->adjusted_mode.clock /= 2;
236+
+ crtc_state->adjusted_mode.crtc_clock /= 2;
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+ crtc_state->adjusted_mode.vdisplay /= 2;
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+ crtc_state->adjusted_mode.crtc_vdisplay /= 2;
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+ crtc_state->adjusted_mode.vsync_start /= 2;
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+ crtc_state->adjusted_mode.crtc_vsync_start /= 2;
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+ crtc_state->adjusted_mode.vsync_end /= 2;
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+ crtc_state->adjusted_mode.crtc_vsync_end /= 2;
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+ crtc_state->adjusted_mode.vtotal /= 2;
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+ crtc_state->adjusted_mode.crtc_vtotal /= 2;
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+ }
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+
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if (crtc_state->adjusted_mode.crtc_clock != reference_mode->clock ||
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crtc_state->adjusted_mode.crtc_htotal != reference_mode->htotal ||
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crtc_state->adjusted_mode.crtc_hdisplay % 4 != 0 ||
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From 3c08549f11d5fb031661d8b1d1b2325ea6153656 Mon Sep 17 00:00:00 2001
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From: Mateusz Kwiatkowski <[email protected]>
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Date: Tue, 12 Oct 2021 00:30:02 +0200
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Subject: [PATCH 2/2] drm/vc4: Add support for horizontally caled VEC modes
255+
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Composite output uses non-square pixels. By allowing horizontally scaled
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modes, we can simulate a different pixel clock and thus make it possible
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to simulate square pixels at either 4:3 or 16:9 target aspect ratio.
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Signed-off-by: Mateusz Kwiatkowski <[email protected]>
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---
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drivers/gpu/drm/vc4/vc4_vec.c | 40 ++++++++++++++++++++++++++++++-----
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1 file changed, 35 insertions(+), 5 deletions(-)
264+
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diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
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index 14eb28c859eb4..e60a5c1e01472 100644
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--- a/drivers/gpu/drm/vc4/vc4_vec.c
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+++ b/drivers/gpu/drm/vc4/vc4_vec.c
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@@ -681,13 +681,43 @@ static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
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crtc_state->adjusted_mode.crtc_vtotal /= 2;
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}
272+
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- if (crtc_state->adjusted_mode.crtc_clock != reference_mode->clock ||
274+
- crtc_state->adjusted_mode.crtc_htotal != reference_mode->htotal ||
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- crtc_state->adjusted_mode.crtc_hdisplay % 4 != 0 ||
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- crtc_state->adjusted_mode.crtc_hsync_end -
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- crtc_state->adjusted_mode.crtc_hsync_start < 1)
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+ if (crtc_state->adjusted_mode.hdisplay % 4 != 0 ||
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+ crtc_state->adjusted_mode.hsync_end -
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+ crtc_state->adjusted_mode.hsync_start < 1)
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return -EINVAL;
282+
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+ crtc_state->adjusted_mode.hdisplay =
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+ DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.hdisplay *
285+
+ reference_mode->clock,
286+
+ crtc_state->adjusted_mode.clock);
287+
+ crtc_state->adjusted_mode.hsync_start =
288+
+ DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.hsync_start *
289+
+ reference_mode->clock,
290+
+ crtc_state->adjusted_mode.clock);
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+ crtc_state->adjusted_mode.hsync_end =
292+
+ DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.hsync_end *
293+
+ reference_mode->clock,
294+
+ crtc_state->adjusted_mode.clock);
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+ crtc_state->adjusted_mode.htotal =
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+ DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.htotal *
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+ reference_mode->clock,
298+
+ crtc_state->adjusted_mode.clock);
299+
+ crtc_state->adjusted_mode.clock = reference_mode->clock;
300+
+
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+ if (crtc_state->adjusted_mode.htotal != reference_mode->htotal)
302+
+ return -EINVAL;
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+
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+ if (crtc_state->adjusted_mode.hsync_end -
305+
+ crtc_state->adjusted_mode.hsync_start < 1)
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+ crtc_state->adjusted_mode.hsync_end =
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+ crtc_state->adjusted_mode.hsync_start + 1;
308+
+
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+ crtc_state->adjusted_mode.crtc_clock = crtc_state->adjusted_mode.clock;
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+ crtc_state->adjusted_mode.crtc_hdisplay = crtc_state->adjusted_mode.hdisplay;
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+ crtc_state->adjusted_mode.crtc_hsync_start = crtc_state->adjusted_mode.hsync_start;
312+
+ crtc_state->adjusted_mode.crtc_hsync_end = crtc_state->adjusted_mode.hsync_end;
313+
+ crtc_state->adjusted_mode.crtc_htotal = crtc_state->adjusted_mode.htotal;
314+
+
315+
switch (reference_mode->vtotal) {
316+
case 525:
317+
if (crtc_state->adjusted_mode.crtc_vdisplay < 1 ||

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