Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Incompatibility with the latest GOWIN FPGA Designer 1.9.9 Beta4 #8

Open
cristianoag opened this issue Jan 2, 2024 · 1 comment
Open

Incompatibility with the latest GOWIN FPGA Designer 1.9.9 Beta4 #8

cristianoag opened this issue Jan 2, 2024 · 1 comment

Comments

@cristianoag
Copy link
Contributor

Be aware that the Verilog/VHDL code synthetizes but the Place & Route phase (Floor Planning) cannot complete on the latest GowinSemi FPGA Designer educational version. There ar eincompatibilities with the memory management that blocks that version to finish the process. Download and use the 1.9.8.11 version from https://cdn.gowinsemi.com.cn/Gowin_V1.9.8.11_Education_win.zip
@herraa1
Copy link
Contributor

herraa1 commented May 22, 2024

I can confirm that this was fixed in commit 5715d2c "support to Gowin Beta 1.9.9 Beta-4" so this issue can be closed.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@cristianoag @herraa1