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| 1 | +from starkware.cairo.common.alloc import alloc |
| 2 | +from starkware.cairo.common.bool import FALSE, TRUE |
| 3 | + |
| 4 | +// Tests the QM31_add_mul opcode runners using specific examples as reference. |
| 5 | +// The test is comprised of 10 test cases, each of which tests a different combination of missing_operand, is_imm, and is_mul. |
| 6 | +// is_mul determines whether the operation is a multiplication or an addition of QM31 elements. |
| 7 | +// is_imm determines whether op1 is an immediate. |
| 8 | +// missing_operand determines which operand is missing and needs to be computed by the VM (0 for dst, 1 for op0, 2 fo op1). |
| 9 | +// the combination of is_imm=TRUE with missig_operand=2 is not tested because we do not use arithmetic opcodes to deduce immediates. |
| 10 | +func main{}() { |
| 11 | + let qm31_op0_coordinates_a = 0x544b2fba; |
| 12 | + let qm31_op0_coordinates_b = 0x673cff77; |
| 13 | + let qm31_op0_coordinates_c = 0x60713d44; |
| 14 | + let qm31_op0_coordinates_d = 0x499602d2; |
| 15 | + let qm31_op0 = qm31_op0_coordinates_a + qm31_op0_coordinates_b*(2**36) + qm31_op0_coordinates_c*(2**72) + qm31_op0_coordinates_d*(2**108); |
| 16 | + |
| 17 | + let qm31_op1_coordinates_a = 0x4b18de99; |
| 18 | + let qm31_op1_coordinates_b = 0x55f6fb62; |
| 19 | + let qm31_op1_coordinates_c = 0x6e2290d9; |
| 20 | + let qm31_op1_coordinates_d = 0x7cd851b9; |
| 21 | + let qm31_op1 = qm31_op1_coordinates_a + qm31_op1_coordinates_b*(2**36) + qm31_op1_coordinates_c*(2**72) + qm31_op1_coordinates_d*(2**108); |
| 22 | + |
| 23 | + let qm31_add_dst_coordinates_a = 0x1f640e54; |
| 24 | + let qm31_add_dst_coordinates_b = 0x3d33fada; |
| 25 | + let qm31_add_dst_coordinates_c = 0x4e93ce1e; |
| 26 | + let qm31_add_dst_coordinates_d = 0x466e548c; |
| 27 | + let qm31_add_dst = qm31_add_dst_coordinates_a + qm31_add_dst_coordinates_b*(2**36) + qm31_add_dst_coordinates_c*(2**72) + qm31_add_dst_coordinates_d*(2**108); |
| 28 | + |
| 29 | + let qm31_mul_dst_coordinates_a = 0x38810ab4; |
| 30 | + let qm31_mul_dst_coordinates_b = 0x5a0fd30a; |
| 31 | + let qm31_mul_dst_coordinates_c = 0x2527b81e; |
| 32 | + let qm31_mul_dst_coordinates_d = 0x4b1ed1cd; |
| 33 | + let qm31_mul_dst = qm31_mul_dst_coordinates_a + qm31_mul_dst_coordinates_b*(2**36) + qm31_mul_dst_coordinates_c*(2**72) + qm31_mul_dst_coordinates_d*(2**108); |
| 34 | + |
| 35 | + let runner_output_mul_dst = run_qm31_operation(missing_operand=0, is_imm=FALSE, is_mul=TRUE, dst_or_op0=qm31_op0, op0_or_op1=qm31_op1); |
| 36 | + assert runner_output_mul_dst = qm31_mul_dst; |
| 37 | + let runner_output_add_dst = run_qm31_operation(missing_operand=0, is_imm=FALSE, is_mul=FALSE, dst_or_op0=qm31_op0, op0_or_op1=qm31_op1); |
| 38 | + assert runner_output_add_dst = qm31_add_dst; |
| 39 | + |
| 40 | + let runner_output_mul_op0 = run_qm31_operation(missing_operand=1, is_imm=FALSE, is_mul=TRUE, dst_or_op0=qm31_mul_dst, op0_or_op1=qm31_op1); |
| 41 | + assert runner_output_mul_op0 = qm31_op0; |
| 42 | + let runner_output_add_op0 = run_qm31_operation(missing_operand=1, is_imm=FALSE, is_mul=FALSE, dst_or_op0=qm31_add_dst, op0_or_op1=qm31_op1); |
| 43 | + assert runner_output_add_op0 = qm31_op0; |
| 44 | + |
| 45 | + let runner_output_mul_op1 = run_qm31_operation(missing_operand=2, is_imm=FALSE, is_mul=TRUE, dst_or_op0=qm31_mul_dst, op0_or_op1=qm31_op0); |
| 46 | + assert runner_output_mul_op1 = qm31_op1; |
| 47 | + let runner_output_add_op1 = run_qm31_operation(missing_operand=2, is_imm=FALSE, is_mul=FALSE, dst_or_op0=qm31_add_dst, op0_or_op1=qm31_op0); |
| 48 | + assert runner_output_add_op1 = qm31_op1; |
| 49 | + |
| 50 | + let runner_output_mul_dst = run_qm31_operation(missing_operand=0, is_imm=TRUE, is_mul=TRUE, dst_or_op0=qm31_op0, op0_or_op1=qm31_op1); |
| 51 | + assert runner_output_mul_dst = qm31_mul_dst; |
| 52 | + let runner_output_add_dst = run_qm31_operation(missing_operand=0, is_imm=TRUE, is_mul=FALSE, dst_or_op0=qm31_op0, op0_or_op1=qm31_op1); |
| 53 | + assert runner_output_add_dst = qm31_add_dst; |
| 54 | + |
| 55 | + let runner_output_mul_op0 = run_qm31_operation(missing_operand=1, is_imm=TRUE, is_mul=TRUE, dst_or_op0=qm31_mul_dst, op0_or_op1=qm31_op1); |
| 56 | + assert runner_output_mul_op0 = qm31_op0; |
| 57 | + let runner_output_add_op0 = run_qm31_operation(missing_operand=1, is_imm=TRUE, is_mul=FALSE, dst_or_op0=qm31_add_dst, op0_or_op1=qm31_op1); |
| 58 | + assert runner_output_add_op0 = qm31_op0; |
| 59 | + |
| 60 | + return (); |
| 61 | +} |
| 62 | + |
| 63 | +// Forces the runner to execute the QM31_add_mul opcode with the given operands. |
| 64 | +// missing_operand, is_imm, is_mul determine the configuration of the operation as described above. |
| 65 | +// dst_or_op0 is a felt representing the value of either the op0 (if missing_operand=0) or dst (otherwise) operand. |
| 66 | +// op0_or_op1 is a felt representing the value of either the op0 (if missing_operand=2) or op1 (otherwise) operand. |
| 67 | +// dst_or_op0 and op0_or_op1 are stored within addresses fp-4 and fp-3 respectively, they are passed to the instruction |
| 68 | +// using offsets wrt fp (unless is_imm=TRUE, in which case op1 has offset 1 relative to pc). |
| 69 | +// The missing operand has offset 0 relative to ap. |
| 70 | +// An instruction encoding with the appropriate flags and offsets is built, then written to [pc] and the runner is forced to execute QM31_add_mul. |
| 71 | +// The missing operand is deduced to [ap] and returned. |
| 72 | +func run_qm31_operation( |
| 73 | + missing_operand: felt, |
| 74 | + is_imm: felt, |
| 75 | + is_mul: felt, |
| 76 | + dst_or_op0: felt, |
| 77 | + op0_or_op1: felt, |
| 78 | +) -> felt { |
| 79 | + alloc_locals; |
| 80 | + |
| 81 | + // Set flags and offsets. |
| 82 | + let (local offsets) = alloc(); |
| 83 | + let (local flags) = alloc(); |
| 84 | +
|
| 85 | + assert offsets[missing_operand] = 2**15; // the missing operand will be written to [ap] |
| 86 | +
|
| 87 | + assert flags[2] = is_imm; // flag_op1_imm = 0; |
| 88 | + assert flags[5] = 1-is_mul; // flag_res_add = 1-is_mul; |
| 89 | + assert flags[6] = is_mul; // flag_res_mul = is_mul; |
| 90 | + assert flags[7] = 0; // flag_PC_update_jump = 0; |
| 91 | + assert flags[8] = 0; // flag_PC_update_jump_rel = 0; |
| 92 | + assert flags[9] = 0; // flag_PC_update_jnz = 0; |
| 93 | + assert flags[10] = 0; // flag_ap_update_add = 0; |
| 94 | + assert flags[11] = 0; // flag_ap_update_add_1 = 0; |
| 95 | + assert flags[12] = 0; // flag_opcode_call = 0; |
| 96 | + assert flags[13] = 0; // flag_opcode_ret = 0; |
| 97 | + assert flags[14] = 1; // flag_opcode_assert_eq = 1; |
| 98 | +
|
| 99 | + if (missing_operand == 0) { |
| 100 | + assert offsets[1] = 2**15 - 4; |
| 101 | + assert offsets[2] = 2**15 - 3 + 4 * is_imm; |
| 102 | + assert flags[0] = 0; // flag_dst_base_fp |
| 103 | + assert flags[1] = 1; // flag_op0_base_fp |
| 104 | + } |
| 105 | + if (missing_operand == 1) { |
| 106 | + assert offsets[0] = 2**15 - 4; |
| 107 | + assert offsets[2] = 2**15 - 3 + 4 * is_imm; |
| 108 | + assert flags[0] = 1; // flag_dst_base_fp |
| 109 | + assert flags[1] = 0; // flag_op0_base_fp |
| 110 | + } |
| 111 | + if (missing_operand == 2) { |
| 112 | + assert is_imm = FALSE; |
| 113 | + assert offsets[0] = 2**15 - 4; |
| 114 | + assert offsets[1] = 2**15 - 3; |
| 115 | + assert flags[0] = 1; // flag_dst_base_fp |
| 116 | + assert flags[1] = 1; // flag_op0_base_fp |
| 117 | + } |
| 118 | + assert flags[3] = 2 - is_imm - flags[0] - flags[1]; // flag_op1_base_fp |
| 119 | + assert flags[4] = 1 - is_imm - flags[3]; // flag_op1_base_ap |
| 120 | +
|
| 121 | + // Compute the instruction encoding. |
| 122 | + let flag_num = flags[0] + flags[1]*(2**1) + flags[2]*(2**2) + flags[3]*(2**3) + flags[4]*(2**4) + flags[5]*(2**5) + flags[6]*(2**6) + flags[14]*(2**14); |
| 123 | + let qm31_opcode_extension_num = 3; |
| 124 | + let instruction_encoding = offsets[0] + offsets[1]*(2**16) + offsets[2]*(2**32) + flag_num*(2**48) + qm31_opcode_extension_num*(2**63); |
| 125 | +
|
| 126 | + // Run the instruction and return the result. |
| 127 | + if (is_imm == TRUE) { |
| 128 | + assert op0_or_op1 = 0x7cd851b906e2290d9055f6fb6204b18de99; |
| 129 | + if (missing_operand == 0) { |
| 130 | + if (is_mul == TRUE) { |
| 131 | + assert instruction_encoding=0x1c04680017ffc8000; |
| 132 | + dw 0x1c04680017ffc8000; |
| 133 | + dw 0x7cd851b906e2290d9055f6fb6204b18de99; |
| 134 | + return [ap]; |
| 135 | + } |
| 136 | + assert instruction_encoding=0x1c02680017ffc8000; |
| 137 | + dw 0x1c02680017ffc8000; |
| 138 | + dw 0x7cd851b906e2290d9055f6fb6204b18de99; |
| 139 | + return [ap]; |
| 140 | + } |
| 141 | + if (missing_operand == 1) { |
| 142 | + if (is_mul == TRUE) { |
| 143 | + assert instruction_encoding=0x1c045800180007ffc; |
| 144 | + dw 0x1c045800180007ffc; |
| 145 | + dw 0x7cd851b906e2290d9055f6fb6204b18de99; |
| 146 | + return [ap]; |
| 147 | + } |
| 148 | + assert instruction_encoding=0x1c025800180007ffc; |
| 149 | + dw 0x1c025800180007ffc; |
| 150 | + dw 0x7cd851b906e2290d9055f6fb6204b18de99; |
| 151 | + return [ap]; |
| 152 | + } |
| 153 | + } |
| 154 | +
|
| 155 | + if (missing_operand == 0) { |
| 156 | + if (is_mul == TRUE) { |
| 157 | + assert instruction_encoding=0x1c04a7ffd7ffc8000; |
| 158 | + dw 0x1c04a7ffd7ffc8000; |
| 159 | + return [ap]; |
| 160 | + } |
| 161 | + assert instruction_encoding=0x1c02a7ffd7ffc8000; |
| 162 | + dw 0x1c02a7ffd7ffc8000; |
| 163 | + return [ap]; |
| 164 | + } |
| 165 | + if (missing_operand == 1) { |
| 166 | + if (is_mul == TRUE) { |
| 167 | + assert instruction_encoding=0x1c0497ffd80007ffc; |
| 168 | + dw 0x1c0497ffd80007ffc; |
| 169 | + return [ap]; |
| 170 | + } |
| 171 | + assert instruction_encoding=0x1c0297ffd80007ffc; |
| 172 | + dw 0x1c0297ffd80007ffc; |
| 173 | + return [ap]; |
| 174 | + } |
| 175 | + if (is_mul == TRUE) { |
| 176 | + dw 0x1c05380007ffd7ffc; |
| 177 | + return [ap]; |
| 178 | + } |
| 179 | + dw 0x1c03380007ffd7ffc; |
| 180 | + return [ap]; |
| 181 | +} |
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