Dev blog

[kivikakk]

I thought I'd make a log here of notes while working.

I need to head off now, so current progress:

• now using the memory map (badly) to choose where to locate the kernel. In practice it still places at 0x40000000 (1GiB) on QEMU, but now around 0x08116000 (129MiB) on the ROCKPro64.
• confirmed writing to the framebuffer works on the kernel side on bare metal, so I need to start debugging why the MMU bring up isn't working. This could be painful. I wonder if I try getting a minimal UART setup first so I can actually get some values out of there. It'd need to work pre-MMU, so no virtual memory, all offsets are wrong, etc.

[kivikakk]

Finished a lot of work on dtb.zig, first in making it more or less feature-complete enough for our needs, then in trying it out and realising it allocates way too much memory while parsing a regular-sized device tree.

It seemed like a good place to try Zig's suspend/resume functionality. It's a bit under-documented, and it took me a moment to realise my use would need to avoid await, since that necessitates the presence of an event loop—our execution flow is deterministic. But you still need to use async to allocate the frame. There was a bit of work in making it more ergonomic, and the awkwardness that followed while trying to keep it allocator-free (i.e. need to init in place everywhere).

This culminated in dainboot being able to hastily hack apart the device tree with a loop, and hopefully scope out the UART:

daintree/dainboot/src/dtb.zig

Lines 19 to 87 in e33551d

	while (ev != .End) : (ev = try traverser.next()) {
	switch (state) {
	.Root => switch (ev) {
	.BeginNode => |name| {
	if (std.mem.startsWith(u8, name, "pl011@")) {
	state = .Pl011;
	} else if (std.mem.startsWith(u8, name, "serial@")) {
	serial_value = null;
	state = .Serial;
	} else {
	state = .{ .Irrelevant = 0 };
	}
	},
	.Prop => |prop| {
	if (std.mem.eql(u8, prop.name, "#address-cells")) {
	address_cells = std.mem.bigToNative(u32, @ptrCast(*const u32, @alignCast(@alignOf(u32), prop.value.ptr)).*);
	} else if (std.mem.eql(u8, prop.name, "#size-cells")) {
	size_cells = std.mem.bigToNative(u32, @ptrCast(*const u32, @alignCast(@alignOf(u32), prop.value.ptr)).*);
	}
	},
	else => {},
	},
	.Irrelevant => |*depth| switch (ev) {
	.BeginNode => {
	depth.* += 1;
	},
	.EndNode => {
	if (depth.* == 0) {
	state = .Root;
	} else {
	depth.* -= 1;
	}
	},
	else => {},
	},
	.Pl011 => switch (ev) {
	.Prop => |prop| {
	if (std.mem.eql(u8, prop.name, "reg") and address_cells != null and size_cells != null) {
	return try firstReg(address_cells.?, prop.value);
	}
	},
	.BeginNode => state = .{ .Irrelevant = 1 },
	.EndNode => state = .Root,
	else => {},
	},
	.Serial => switch (ev) {
	.Prop => |prop| {
	if (std.mem.eql(u8, prop.name, "reg") and address_cells != null and size_cells != null) {
	serial_value = try firstReg(address_cells.?, prop.value);
	} else if (std.mem.eql(u8, prop.name, "status")) {
	if (!std.mem.eql(u8, "okay\x00", prop.value)) {
	state = .{ .Irrelevant = 0 };
	}
	}
	},
	.BeginNode => {
	// Don't want any serial with a subnode.
	state = .{ .Irrelevant = 1 };
	},
	.EndNode => {
	if (serial_value) |made_it| {
	return made_it;
	}
	state = .Root;
	},
	else => {},
	},
	}
	}

The heuristic is awful. I don't even check compatible here. Works on my QEMU machine and the ROCKPro64—probably not anywhere else.

[kivikakk]

Today was huge! I got the ROCKPro64 brought up to the same level as QEMU. There were some key realisations of things we needed to do on real hardware that we didn't on virtualised:

1. Clean the instruction cache. A maintenance routine copied straight from Arm documentation did the trick.
   a. Cache struck again later when moving arguments into a struct stored on the stack and I was getting stale reads; again, only on hardware.
2. Map the UART registers with the MMU with MAIR attributes suitable for peripherals, so the MMIO works.
3. Disable trapping of SIMD/floating point/etc. Some Zig routines were being smart.

Everything's a hack right now -- we're just about ready to start loading from the dtb in the kernel -- but there's a cute easter egg on boot now.

[kivikakk]

Refactored the kernel to use the DTB to establish what kind of UART we have, and then use that "driver". (QEMU and ROCKPro64 UARTs have different register configurations; they work the same for just writing bytes out, but reading back needs a different touch.)

Generally cleaned up a lot of hacks and invalidated some old assumptions about things I needed to be doing.

Got waylaid realising that UEFI gives a DTB, and I should preferably use that as the earlier boot stage might modify the DTB it got before giving it to us. (End goal is to get a working PSCI reset or shutdown going.)

[kivikakk]

Lately:

• Patch introducing fw_cfg on Arm to U-Boot nears readiness.
• Patch introducing fw_cfg and ramfb to QEMU riscv virt in the queue to be merged.

I've started work on the riscv port. There was a lot to do to get dainboot going because LLVM can't produce a riscv COFF file. It just won't. Nothing will.

Turns out everyone([1] [2] [3]) hacks around this by prepending a PE32+ header manually, and then doing all the ELF relocations yourself. So now do we:

• buildRiscv64 has some things I'm not proud of.
• relocate is just a little gross.
• Finding out a missing memcpy and memset were causing our builds to include sections that others who'd trod this path before us didn't and thus screwed everything else up was a relief.
  • Sentence fragment: consider revision.

Now it's time to get started on MMU setup on riscv64. #2 has the code in progress.