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DemoWithMemCfg.ucf
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DemoWithMemCfg.ucf
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# clock pin for Nexys 2 Board
NET "clk" LOC= "B8"; # Bank = 0 , Pin name = IP_L13P_0/GCLK8 , Type = GCLK , Sch name = GCLK0
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "clk1" LOC= "U9"; # Bank = 2 , Pin name = IO_L13P_2/D4/GCLK14 , Type = DUAL/GCLK , Sch name = GCLK1
# Pin assignment for UsbCtl
# Connected to Nexys2 onBoard USB controller
NET "EppAstb" LOC= "V14"; # Bank = 2 , Pin name = IP_L23P_2 , Type = INPUT , Sch name = U-FLAGA
NET "EppDstb" LOC= "U14"; # Bank = 2 , Pin name = IP_L23N_2 , Type = INPUT , Sch name = U-FLAGB
NET "UsbFlag" LOC= "V16"; # Bank = 2 , Pin name = IP , Type = INPUT , Sch name = U-FLAGC
NET "EppWait" LOC= "N9"; # Bank = 2 , Pin name = IO_L12P_2/D7/GCLK12 , Type = DUAL/GCLK , Sch name = U-SLRD
NET "UsbDB<0>" LOC= "R14"; # Bank = 2 , Pin name = IO_L24N_2/A20 , Type = DUAL , Sch name = U-FD0
NET "UsbDB<1>" LOC= "R13"; # Bank = 2 , Pin name = IO_L22N_2/A22 , Type = DUAL , Sch name = U-FD1
NET "UsbDB<2>" LOC= "P13"; # Bank = 2 , Pin name = IO_L22P_2/A23 , Type = DUAL , Sch name = U-FD2
NET "UsbDB<3>" LOC= "T12"; # Bank = 2 , Pin name = IO_L20P_2 , Type = I/O , Sch name = U-FD3
NET "UsbDB<4>" LOC= "N11"; # Bank = 2 , Pin name = IO_L18N_2 , Type = I/O , Sch name = U-FD4
NET "UsbDB<5>" LOC= "R11"; # Bank = 2 , Pin name = IO , Type = I/O , Sch name = U-FD5
NET "UsbDB<6>" LOC= "P10"; # Bank = 2 , Pin name = IO_L15N_2/D1/GCLK3 , Type = DUAL/GCLK , Sch name = U-FD6
NET "UsbDB<7>" LOC= "R10"; # Bank = 2 , Pin name = IO_L15P_2/D2/GCLK2 , Type = DUAL/GCLK , Sch name = U-FD7
NET "UsbClk" LOC= "T15"; # Bank = 2 , Pin name = IO/VREF_2 , Type = VREF , Sch name = U-IFCLK
NET "UsbClk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "UsbOE" LOC= "V15"; # Bank = 2 , Pin name = IO_L25P_2/VS2/A19 , Type = DUAL , Sch name = U-SLOE
NET "UsbWR" LOC= "V9"; # Bank = 2 , Pin name = IO_L13N_2/D3/GCLK15 , Type = DUAL/GCLK , Sch name = U-SWLR
NET "UsbPktEnd" LOC= "V12"; # Bank = 2 , Pin name = IO_L19P_2 , Type = I/O , Sch name = U-PKTEND
NET "UsbDir" LOC= "T16"; # Bank = 2 , Pin name = IO_L26P_2/VS0/A17 , Type = DUAL , Sch name = U-SLCS
NET "UsbMode" LOC= "U15"; # Bank = 2 , Pin name = IO_L25N_2/VS1/A18 , Type = DUAL , Sch name = U-INT0#
NET "UsbAdr<0>" LOC= "T14"; # Bank = 2 , Pin name = IO_L24P_2/A21 , Type = DUAL , Sch name = U-FIFOAD0
NET "UsbAdr<1>" LOC= "V13"; # Bank = 2 , Pin name = IO_L19N_2/VREF_2 , Type = VREF , Sch name = U-FIFOAD1
# NET "UsbRdy" LOC= "U13"; # Bank = 2 , Pin name = IP , Type = INPUT , Sch name = U-RDY
# Pin assignment for OnBoardMemCtrl
# Connected to Nexys 2 onBoard Cellular RAM and StrataFlash
NET "MemOE" LOC= "T2"; # Bank = 3 , Pin name = IO_L24P_3 , Type = I/O , Sch name = OE
NET "MemWR" LOC= "N7"; # Bank = 2 , Pin name = IO_L07P_2 , Type = I/O , Sch name = WE
NET "RamAdv" LOC= "J4"; # Bank = 3 , Pin name = IO_L11N_3/LHCLK1 , Type = LHCLK , Sch name = MT-ADV
NET "RamCS" LOC= "R6"; # Bank = 2 , Pin name = IO_L05P_2 , Type = I/O , Sch name = MT-CE
NET "RamClk" LOC= "H5"; # Bank = 3 , Pin name = IO_L08N_3 , Type = I/O , Sch name = MT-CLK
NET "RamCRE" LOC= "P7"; # Bank = 2 , Pin name = IO_L07N_2 , Type = I/O , Sch name = MT-CRE
NET "RamLB" LOC= "K5"; # Bank = 3 , Pin name = IO_L14N_3/LHCLK7 , Type = LHCLK , Sch name = MT-LB
NET "RamUB" LOC= "K4"; # Bank = 3 , Pin name = IO_L13N_3/LHCLK5 , Type = LHCLK , Sch name = MT-UB
NET "RamWait" LOC= "F5"; # Bank = 3 , Pin name = IP , Type = INPUT , Sch name = MT-WAIT
NET "FlashRp" LOC= "T5"; # Bank = 2 , Pin name = IO_L04N_2 , Type = I/O , Sch name = RP#
NET "FlashCS" LOC= "R5"; # Bank = 2 , Pin name = IO_L04P_2 , Type = I/O , Sch name = ST-CE
NET "FlashStSts" LOC= "D3"; # Bank = 3 , Pin name = IP , Type = INPUT , Sch name = ST-STS
NET "MemAdr<1>" LOC= "J1"; # Bank = 3 , Pin name = IO_L12P_3/LHCLK2 , Type = LHCLK , Sch name = ADR1
NET "MemAdr<2>" LOC= "J2"; # Bank = 3 , Pin name = IO_L12N_3/LHCLK3/IRDY2 , Type = LHCLK , Sch name = ADR2
NET "MemAdr<3>" LOC= "H4"; # Bank = 3 , Pin name = IO_L09P_3 , Type = I/O , Sch name = ADR3
NET "MemAdr<4>" LOC= "H1"; # Bank = 3 , Pin name = IO_L10N_3 , Type = I/O , Sch name = ADR4
NET "MemAdr<5>" LOC= "H2"; # Bank = 3 , Pin name = IO_L10P_3 , Type = I/O , Sch name = ADR5
NET "MemAdr<6>" LOC= "J5"; # Bank = 3 , Pin name = IO_L11P_3/LHCLK0 , Type = LHCLK , Sch name = ADR6
NET "MemAdr<7>" LOC= "H3"; # Bank = 3 , Pin name = IO_L09N_3 , Type = I/O , Sch name = ADR7
NET "MemAdr<8>" LOC= "H6"; # Bank = 3 , Pin name = IO_L08P_3 , Type = I/O , Sch name = ADR8
NET "MemAdr<9>" LOC= "F1"; # Bank = 3 , Pin name = IO_L05P_3 , Type = I/O , Sch name = ADR9
NET "MemAdr<10>" LOC= "G3"; # Bank = 3 , Pin name = IO_L06P_3 , Type = I/O , Sch name = ADR10
NET "MemAdr<11>" LOC= "G6"; # Bank = 3 , Pin name = IO_L07P_3 , Type = I/O , Sch name = ADR11
NET "MemAdr<12>" LOC= "G5"; # Bank = 3 , Pin name = IO_L07N_3 , Type = I/O , Sch name = ADR12
NET "MemAdr<13>" LOC= "G4"; # Bank = 3 , Pin name = IO_L06N_3/VREF_3 , Type = VREF , Sch name = ADR13
NET "MemAdr<14>" LOC= "F2"; # Bank = 3 , Pin name = IO_L05N_3 , Type = I/O , Sch name = ADR14
NET "MemAdr<15>" LOC= "E1"; # Bank = 3 , Pin name = IO_L03N_3 , Type = I/O , Sch name = ADR15
NET "MemAdr<16>" LOC= "M5"; # Bank = 3 , Pin name = IO_L19P_3 , Type = I/O , Sch name = ADR16
NET "MemAdr<17>" LOC= "E2"; # Bank = 3 , Pin name = IO_L03P_3 , Type = I/O , Sch name = ADR17
NET "MemAdr<18>" LOC= "C2"; # Bank = 3 , Pin name = IO_L01N_3 , Type = I/O , Sch name = ADR18
NET "MemAdr<19>" LOC= "C1"; # Bank = 3 , Pin name = IO_L01P_3 , Type = I/O , Sch name = ADR19
NET "MemAdr<20>" LOC= "D2"; # Bank = 3 , Pin name = IO_L02N_3/VREF_3 , Type = VREF , Sch name = ADR20
NET "MemAdr<21>" LOC= "K3"; # Bank = 3 , Pin name = IO_L13P_3/LHCLK4/TRDY2 , Type = LHCLK , Sch name = ADR21
NET "MemAdr<22>" LOC= "D1"; # Bank = 3 , Pin name = IO_L02P_3 , Type = I/O , Sch name = ADR22
NET "MemAdr<23>" LOC= "K6"; # Bank = 3 , Pin name = IO_L14P_3/LHCLK6 , Type = LHCLK , Sch name = ADR23
NET "MemDB<0>" LOC= "L1"; # Bank = 3 , Pin name = IO_L15P_3 , Type = I/O , Sch name = DB0
NET "MemDB<1>" LOC= "L4"; # Bank = 3 , Pin name = IO_L16N_3 , Type = I/O , Sch name = DB1
NET "MemDB<2>" LOC= "L6"; # Bank = 3 , Pin name = IO_L17P_3 , Type = I/O , Sch name = DB2
NET "MemDB<3>" LOC= "M4"; # Bank = 3 , Pin name = IO_L18P_3 , Type = I/O , Sch name = DB3
NET "MemDB<4>" LOC= "N5"; # Bank = 3 , Pin name = IO_L20N_3 , Type = I/O , Sch name = DB4
NET "MemDB<5>" LOC= "P1"; # Bank = 3 , Pin name = IO_L21N_3 , Type = I/O , Sch name = DB5
NET "MemDB<6>" LOC= "P2"; # Bank = 3 , Pin name = IO_L21P_3 , Type = I/O , Sch name = DB6
NET "MemDB<7>" LOC= "R2"; # Bank = 3 , Pin name = IO_L23N_3 , Type = I/O , Sch name = DB7
NET "MemDB<8>" LOC= "L3"; # Bank = 3 , Pin name = IO_L16P_3 , Type = I/O , Sch name = DB8
NET "MemDB<9>" LOC= "L5"; # Bank = 3 , Pin name = IO_L17N_3/VREF_3 , Type = VREF , Sch name = DB9
NET "MemDB<10>" LOC= "M3"; # Bank = 3 , Pin name = IO_L18N_3 , Type = I/O , Sch name = DB10
NET "MemDB<11>" LOC= "M6"; # Bank = 3 , Pin name = IO_L19N_3 , Type = I/O , Sch name = DB11
NET "MemDB<12>" LOC= "L2"; # Bank = 3 , Pin name = IO_L15N_3 , Type = I/O , Sch name = DB12
NET "MemDB<13>" LOC= "N4"; # Bank = 3 , Pin name = IO_L20P_3 , Type = I/O , Sch name = DB13
NET "MemDB<14>" LOC= "R3"; # Bank = 3 , Pin name = IO_L23P_3 , Type = I/O , Sch name = DB14
NET "MemDB<15>" LOC= "T1"; # Bank = 3 , Pin name = IO_L24N_3 , Type = I/O , Sch name = DB15
# Pin assignment for DispCtl
# Connected to Nexys 2 onBoard 7seg display
NET "seg<0>" LOC= "L18"; # Bank = 1 , Pin name = IO_L10P_1 , Type = I/O , Sch name = CA
NET "seg<1>" LOC= "F18"; # Bank = 1 , Pin name = IO_L19P_1 , Type = I/O , Sch name = CB
NET "seg<2>" LOC= "D17"; # Bank = 1 , Pin name = IO_L23P_1/HDC , Type = DUAL , Sch name = CC
NET "seg<3>" LOC= "D16"; # Bank = 1 , Pin name = IO_L23N_1/LDC0 , Type = DUAL , Sch name = CD
NET "seg<4>" LOC= "G14"; # Bank = 1 , Pin name = IO_L20P_1 , Type = I/O , Sch name = CE
NET "seg<5>" LOC= "J17"; # Bank = 1 , Pin name = IO_L13P_1/A6/RHCLK4/IRDY1 , Type = RHCLK/DUAL , Sch name = CF
NET "seg<6>" LOC= "H14"; # Bank = 1 , Pin name = IO_L17P_1 , Type = I/O , Sch name = CG
NET "dp" LOC= "C17"; # Bank = 1 , Pin name = IO_L24N_1/LDC2 , Type = DUAL , Sch name = DP
NET "an<0>" LOC= "F17"; # Bank = 1 , Pin name = IO_L19N_1 , Type = I/O , Sch name = AN0
NET "an<1>" LOC= "H17"; # Bank = 1 , Pin name = IO_L16N_1/A0 , Type = DUAL , Sch name = AN1
NET "an<2>" LOC= "C18"; # Bank = 1 , Pin name = IO_L24P_1/LDC1 , Type = DUAL , Sch name = AN2
NET "an<3>" LOC= "F15"; # Bank = 1 , Pin name = IO_L21P_1 , Type = I/O , Sch name = AN3
# Pin assignment for Leds
# Connected to Nexys 2
NET "Led<0>" LOC= "J14"; # Bank = 1 , Pin name = IO_L14N_1/A3/RHCLK7 , Type = RHCLK/DUAL , Sch name = JD10/LD0
NET "Led<1>" LOC= "J15"; # Bank = 1 , Pin name = IO_L14P_1/A4/RHCLK6 , Type = RHCLK/DUAL , Sch name = JD9/LD1
NET "Led<2>" LOC= "K15"; # Bank = 1 , Pin name = IO_L12P_1/A8/RHCLK2 , Type = RHCLK/DUAL , Sch name = JD8/LD2
NET "Led<3>" LOC= "K14"; # Bank = 1 , Pin name = IO_L12N_1/A7/RHCLK3/TRDY1 , Type = RHCLK/DUAL , Sch name = JD7/LD3
# NET "Led<4>" LOC= "E17"; # Bank = 1 , Pin name = IO , Type = I/O , Sch name = LD4?
# NET "Led<5>" LOC= "P15"; # Bank = 1 , Pin name = IO , Type = I/O , Sch name = LD5?
# NET "Led<6>" LOC= "F4"; # Bank = 3 , Pin name = IO , Type = I/O , Sch name = LD6?
# NET "Led<7>" LOC= "R4"; # Bank = 3 , Pin name = IO/VREF_3 , Type = VREF , Sch name = LD7?
NET "Led<4>" LOC= "E16"; # Bank = 1 , Pin name = N.C. , Type = N.C. , Sch name = LD4? other than s3e500
NET "Led<5>" LOC= "P16"; # Bank = 1 , Pin name = N.C. , Type = N.C. , Sch name = LD5? other than s3e500
NET "Led<6>" LOC= "E4"; # Bank = 3 , Pin name = N.C. , Type = N.C. , Sch name = LD6? other than s3e500
NET "Led<7>" LOC= "P4"; # Bank = 3 , Pin name = N.C. , Type = N.C. , Sch name = LD7? other than s3e500
# Pin assignment for Switches
# Connected to Nexys 2
NET "sw<0>" LOC= "G18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW0
NET "sw<1>" LOC= "H18"; # Bank = 1 , Pin name = IP/VREF_1 , Type = VREF , Sch name = SW1
NET "sw<2>" LOC= "K18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW2
NET "sw<3>" LOC= "K17"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW3
NET "sw<4>" LOC= "L14"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW4
NET "sw<5>" LOC= "L13"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW5
NET "sw<6>" LOC= "N17"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW6
NET "sw<7>" LOC= "R17"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = SW7
# Pin assignment for Buttons
# Connected to Nexys 2
NET "btn<0>" LOC= "B18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN0
NET "btn<1>" LOC= "D18"; # Bank = 1 , Pin name = IP/VREF_1 , Type = VREF , Sch name = BTN1
NET "btn<2>" LOC= "E18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN2
NET "btn<3>" LOC= "H13"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN3
# Pin assignment for VGA demo
# Connected to Nexys 2
NET "vgaRed<0>" LOC= "R9"; # Bank = 2 , Pin name = IO/D5 , Type = DUAL , Sch name = RED0
NET "vgaRed<1>" LOC= "T8"; # Bank = 2 , Pin name = IO_L10N_2 , Type = I/O , Sch name = RED1
NET "vgaRed<2>" LOC= "R8"; # Bank = 2 , Pin name = IO_L10P_2 , Type = I/O , Sch name = RED2
NET "vgaGreen<0>" LOC= "N8"; # Bank = 2 , Pin name = IO_L09N_2 , Type = I/O , Sch name = GRN0
NET "vgaGreen<1>" LOC= "P8"; # Bank = 2 , Pin name = IO_L09P_2 , Type = I/O , Sch name = GRN1
NET "vgaGreen<2>" LOC= "P6"; # Bank = 2 , Pin name = IO_L05N_2 , Type = I/O , Sch name = GRN2
NET "vgaBlue<1>" LOC= "U5"; # Bank = 2 , Pin name = IO/VREF_2 , Type = VREF , Sch name = BLU1
NET "vgaBlue<2>" LOC= "U4"; # Bank = 2 , Pin name = IO_L03P_2/DOUT/BUSY , Type = DUAL , Sch name = BLU2
NET "Hsync" LOC= "T4" | PULLUP; # Bank = 2 , Pin name = IO_L03N_2/MOSI/CSI_B , Type = DUAL , Sch name = HSYNC
NET "Vsync" LOC= "U3" | PULLUP; # Bank = 2 , Pin name = IO_L01P_2/CSO_B , Type = DUAL , Sch name = VSYNC
NET "PS2C" LOC= "R12" | PULLUP; # Bank = 2 , Pin name = IO_L20N_2 , Type = I/O , Sch name = PS2C
NET "PS2D" LOC= "P11" | PULLUP; # Bank = 2 , Pin name = IO_L18P_2 , Type = I/O , Sch name = PS2D
# Loop Back tested signals
NET "PIO<0>" LOC= "B4" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L24N_0 , Type = I/O , Sch name = R-IO1
NET "PIO<1>" LOC= "A4" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L24P_0 , Type = I/O , Sch name = R-IO2
NET "PIO<2>" LOC= "C3" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L25P_0 , Type = I/O , Sch name = R-IO3
NET "PIO<3>" LOC= "C4" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO , Type = I/O , Sch name = R-IO4
NET "PIO<4>" LOC= "B6" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L20P_0 , Type = I/O , Sch name = R-IO5
NET "PIO<5>" LOC= "D5" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L23N_0/VREF_0 , Type = VREF , Sch name = R-IO6
NET "PIO<6>" LOC= "C5" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L23P_0 , Type = I/O , Sch name = R-IO7
NET "PIO<7>" LOC= "F7" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L19P_0 , Type = I/O , Sch name = R-IO8
NET "PIO<8>" LOC= "E7" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L19N_0/VREF_0 , Type = VREF , Sch name = R-IO9
NET "PIO<9>" LOC= "A6" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L20N_0 , Type = I/O , Sch name = R-IO10
NET "PIO<10>" LOC= "C7" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L18P_0 , Type = I/O , Sch name = R-IO11
NET "PIO<11>" LOC= "F8" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L17N_0 , Type = I/O , Sch name = R-IO12
NET "PIO<12>" LOC= "D7" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L18N_0/VREF_0 , Type = VREF , Sch name = R-IO13
NET "PIO<13>" LOC= "E8" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L17P_0 , Type = I/O , Sch name = R-IO14
NET "PIO<14>" LOC= "E9" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L15P_0 , Type = I/O , Sch name = R-IO15
NET "PIO<15>" LOC= "C9" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L14P_0/GCLK10 , Type = GCLK , Sch name = R-IO16
NET "PIO<16>" LOC= "A8" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO , Type = I/O , Sch name = R-IO17
NET "PIO<17>" LOC= "G9" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO , Type = I/O , Sch name = R-IO18
NET "PIO<18>" LOC= "F9" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L15N_0 , Type = I/O , Sch name = R-IO19
NET "PIO<19>" LOC= "D10" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L11P_0/GCLK4 , Type = GCLK , Sch name = R-IO20
NET "PIO<20>" LOC= "A10" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L12N_0/GCLK7 , Type = GCLK , Sch name = R-IO21
NET "PIO<21>" LOC= "B10" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L12P_0/GCLK6 , Type = GCLK , Sch name = R-IO22
NET "PIO<22>" LOC= "A11" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO , Type = I/O , Sch name = R-IO23
NET "PIO<23>" LOC= "D11" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L09N_0 , Type = I/O , Sch name = R-IO24
NET "PIO<24>" LOC= "E10" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L11N_0/GCLK5 , Type = GCLK , Sch name = R-IO25
NET "PIO<25>" LOC= "B11" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO/VREF_0 , Type = VREF , Sch name = R-IO26
NET "PIO<26>" LOC= "C11" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L09P_0 , Type = I/O , Sch name = R-IO27
NET "PIO<27>" LOC= "E11" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L08P_0 , Type = I/O , Sch name = R-IO28
NET "PIO<28>" LOC= "F11" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L08N_0 , Type = I/O , Sch name = R-IO29
NET "PIO<29>" LOC= "E12" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L06N_0 , Type = I/O , Sch name = R-IO30
NET "PIO<30>" LOC= "F12" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L06P_0 , Type = I/O , Sch name = R-IO31
NET "PIO<31>" LOC= "A13" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L05P_0 , Type = I/O , Sch name = R-IO32
NET "PIO<32>" LOC= "B13" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L05N_0/VREF_0 , Type = VREF , Sch name = R-IO33
NET "PIO<33>" LOC= "E13" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO , Type = I/O , Sch name = R-IO34
NET "PIO<34>" LOC= "A14" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L04N_0 , Type = I/O , Sch name = R-IO35
NET "PIO<35>" LOC= "C14" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L03N_0/VREF_0 , Type = VREF , Sch name = R-IO36
NET "PIO<36>" LOC= "D14" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L03P_0 , Type = I/O , Sch name = R-IO37
NET "PIO<37>" LOC= "B14" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L04P_0 , Type = I/O , Sch name = R-IO38
NET "PIO<38>" LOC= "A16" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L01N_0 , Type = I/O , Sch name = R-IO39
NET "PIO<39>" LOC= "B16" | DRIVE = 2 | PULLUP ; # Bank = 0 , Pin name = IO_L01P_0 , Type = I/O , Sch name = R-IO40
NET "PIO<40>" LOC= "L15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L09N_1/A11 , Type = DUAL , Sch name = JA1
NET "PIO<41>" LOC= "K12" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L11N_1/A9/RHCLK1 , Type = RHCLK/DUAL , Sch name = JA2
NET "PIO<42>" LOC= "L17" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L10N_1/VREF_1 , Type = VREF , Sch name = JA3
NET "PIO<43>" LOC= "M15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L07P_1 , Type = I/O , Sch name = JA4
NET "PIO<44>" LOC= "K13" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L11P_1/A10/RHCLK0 , Type = RHCLK/DUAL , Sch name = JA7
NET "PIO<45>" LOC= "L16" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L09P_1/A12 , Type = DUAL , Sch name = JA8
NET "PIO<46>" LOC= "M14" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L05P_1 , Type = I/O , Sch name = JA9
NET "PIO<47>" LOC= "M16" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L07N_1 , Type = I/O , Sch name = JA10
NET "PIO<48>" LOC= "M13" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L05N_1/VREF_1 , Type = VREF , Sch name = JB1
NET "PIO<49>" LOC= "R18" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L02P_1/A14 , Type = DUAL , Sch name = JB2
NET "PIO<50>" LOC= "R15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L03P_1 , Type = I/O , Sch name = JB3
NET "PIO<51>" LOC= "T17" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L01N_1/A15 , Type = DUAL , Sch name = JB4
NET "PIO<52>" LOC= "P17" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L06P_1 , Type = I/O , Sch name = JB7
NET "PIO<53>" LOC= "R16" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L03N_1/VREF_1 , Type = VREF , Sch name = JB8
NET "PIO<54>" LOC= "T18" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L02N_1/A13 , Type = DUAL , Sch name = JB9
NET "PIO<55>" LOC= "U18" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L01P_1/A16 , Type = DUAL , Sch name = JB10
NET "PIO<56>" LOC= "G15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L18P_1 , Type = I/O , Sch name = JC1
NET "PIO<57>" LOC= "J16" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L13N_1/A5/RHCLK5 , Type = RHCLK/DUAL , Sch name = JC2
NET "PIO<58>" LOC= "G13" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L20N_1 , Type = I/O , Sch name = JC3
NET "PIO<59>" LOC= "H16" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L16P_1 , Type = I/O , Sch name = JC4
NET "PIO<60>" LOC= "H15" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L17N_1 , Type = I/O , Sch name = JC7
NET "PIO<61>" LOC= "F14" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L21N_1 , Type = I/O , Sch name = JC8
NET "PIO<62>" LOC= "G16" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L18N_1 , Type = I/O , Sch name = JC9
NET "PIO<63>" LOC= "J12" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L15P_1/A2 , Type = DUAL , Sch name = JC10
NET "PIO<64>" LOC= "J13" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L15N_1/A1 , Type = DUAL , Sch name = JD1
NET "PIO<65>" LOC= "M18" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L08N_1 , Type = I/O , Sch name = JD2
NET "PIO<66>" LOC= "N18" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L08P_1 , Type = I/O , Sch name = JD3
NET "PIO<67>" LOC= "P18" | DRIVE = 2 | PULLUP ; # Bank = 1 , Pin name = IO_L06N_1 , Type = I/O , Sch name = JD4
NET "RsRx" LOC= "U6" | DRIVE = 2 | PULLUP ; # Bank = 2 , Pin name = IP , Type = INPUT , Sch name = RS-RX
NET "RsTx" LOC= "P9" | DRIVE = 2 | PULLUP ; # Bank = 2 , Pin name = IO , Type = I/O , Sch name = RS-TX