README-Verilog.md

This is a most popular repository list for Verilog sorted by number of stars

STARS	FORKS	ISSUES	LAST COMMIT	NAME/PLACE	DESCRIPTION
2341	628	56	1 year, 2 months ago	picorv32/1	PicoRV32 - A Size-Optimized RISC-V CPU
2241	946	33	2 years ago	e200_opensource/2	Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
1682	548	24	1 year, 2 months ago	wujian100_open/3	IC design and development should be faster，simpler and more reliable
1583	246	14	2 months ago	darkriscv/4	opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
1422	511	194	4 years ago	hw/5	RTL, Cmodel, and testbench for NVDLA
1417	477	80	30 days ago	verilog-ethernet/6	Verilog Ethernet components for FPGA implementation
1122	1348	44	3 days ago	hdl/7	HDL libraries and projects
1084	276	69	3 months ago	corundum/8	Open source FPGA-based NIC and platform for in-network compute
1047	271	0	12 days ago	basic_verilog/9	Must-have verilog systemverilog modules
1008	133	4	3 months ago	zipcpu/10	A small, light weight, RISC CPU soft core
966	76	3	1 year, 4 months ago	amiga2000-gfxcard/11	MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
945	138	15	2 months ago	serv/12	SERV - The SErial RISC-V CPU
916	265	30	5 months ago	oh/13	Verilog library for ASIC and FPGA designers
868	326	31	a day ago	verilog-axi/14	Verilog AXI components for FPGA implementation
868	301	152	a day ago	OpenLane/15	OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
802	217	10	5 years ago	miaow/16	An open source GPU based off of the AMD Southern Islands ISA.
782	301	203	9 hours ago	OpenROAD/17	OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
774	393	9	4 years ago	ODriveHardware/18	High performance motor control
771	590	86	28 days ago	uhd/19	The USRP™ Hardware Driver Repository
769	203	15	7 months ago	openc910/20	OpenXuantie - OpenC910 Core
750	168	10	1 year, 6 months ago	riscv/21	RISC-V CPU Core (RV32IM)
737	233	10	1 year, 4 months ago	e203_hbirdv2/22	The Ultra-Low Power RISC-V Core
734	152	36	5 months ago	vortex/23	None
645	180	4	2 years ago	open-fpga-verilog-tutorial/24	Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
631	202	12	a month ago	verilog-pcie/25	Verilog PCI express components
610	113	31	11 days ago	apio/26	🌱 Open source ecosystem for open FPGA boards
562	265	39	5 months ago	riffa/27	The RIFFA development repository
557	120	60	a day ago	OpenFPGA/28	An Open-source FPGA IP Generator
552	94	45	a month ago	microwatt/29	A tiny Open POWER ISA softcore written in VHDL 2008
550	108	13	1 year, 6 months ago	biriscv/30	32-bit Superscalar RISC-V CPU
532	101	5	3 years ago	LeFlow/31	Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
508	175	3	1 year, 8 months ago	cores/32	Various HDL (Verilog) IP Cores
507	186	1	5 years ago	mips-cpu/33	MIPS CPU implemented in Verilog
506	129	2	1 year, 7 months ago	step_into_mips/34	一步一步写MIPS CPU
497	80	0	2 months ago	USB_C_Industrial_Camera_FPGA_USB3/35	Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
485	90	0	a day ago	riscv_vhdl/36	Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
465	91	23	1 year, 3 months ago	riscv-formal/37	RISC-V Formal Verification Framework
461	174	4	25 days ago	openwifi-hw/38	open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
444	134	0	5 years ago	verilog/39	Repository for basic (and not so basic) Verilog blocks with high re-use potential
439	136	0	4 months ago	Verilog-Practice/40	HDLBits website practices & solutions
432	196	1	7 years ago	FPGA-Imaging-Library/41	An open source library for image processing on FPGA.
423	31	70	22 days ago	ucr-eecs168-lab/42	The lab schedules for EECS168 at UC Riverside
415	138	32	10 months ago	mor1kx/43	mor1kx - an OpenRISC 1000 processor IP core
405	19	6	3 months ago	graphics-gremlin/44	Open source retro ISA video card
400	131	51	4 months ago	OpenTimer/45	A High-performance Timing Analysis Tool for VLSI Systems
394	54	5	3 months ago	VerilogBoy/46	A Pi emulating a GameBoy sounds cheap. What about an FPGA?
358	91	134	23 days ago	CFU-Playground/47	Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
355	83	15	9 days ago	litepcie/48	Small footprint and configurable PCIe core
347	123	12	1 year, 3 months ago	fpu/49	synthesiseable ieee 754 floating point library in verilog
340	77	171	23 days ago	basejump_stl/50	BaseJump STL: A Standard Template Library for SystemVerilog
339	78	2	4 months ago	wb2axip/51	Bus bridges and other odds and ends
338	12	7	13 days ago	vroom/52	VRoom! RISC-V CPU
335	102	3	4 years ago	CNN-FPGA/53	使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
334	143	16	11 years ago	netfpga/54	NetFPGA 1G infrastructure and gateware
329	125	19	5 years ago	convolution_network_on_FPGA/55	CNN acceleration on virtex-7 FPGA with verilog HDL
318	130	6	1 year, 9 months ago	verilog-i2c/56	Verilog I2C interface for FPGA implementation
317	106	7	3 years ago	icezum/57	🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
300	44	16	24 days ago	apicula/58	Project Apicula 🐝: bitstream documentation for Gowin FPGAs
297	38	23	3 years ago	spispy/59	An open source SPI flash emulator and monitor
278	106	8	4 days ago	verilog-uart/60	Verilog UART
276	91	1	3 years ago	AccDNN/61	A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
276	86	1	1 year, 2 months ago	verilog-6502/62	A Verilog HDL model of the MOS 6502 CPU
272	46	15	1 year, 1 month ago	Piccolo/63	RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
272	79	13	10 months ago	icesugar/64	iCESugar FPGA Board (base on iCE40UP5k)
272	127	8	9 years ago	FPGA-Litecoin-Miner/65	A litecoin scrypt miner implemented with FPGA on-chip memory.
271	42	9	1 year, 8 months ago	Project-Zipline/66	Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
270	65	2	4 years ago	zet/67	Open source implementation of a x86 processor
268	149	8	a month ago	openofdm/68	Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
266	18	16	a day ago	tillitis-key1/69	Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑
256	24	0	a month ago	vdatp/70	Volumetric Display using an Acoustically Trapped Particle
249	87	16	6 months ago	Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/71	Verilog Generator of Neural Net Digit Detector for FPGA
248	54	1	5 years ago	ridecore/72	RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
246	84	1	a month ago	sha256/73	Hardware implementation of the SHA-256 cryptographic hash function
242	69	1	8 months ago	32-Verilog-Mini-Projects/74	Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
242	104	1	a month ago	aes/75	Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
235	52	3	1 year, 8 months ago	fpga_readings/76	Recipe for FPGA cooking
234	63	22	10 years ago	fpga_nes/77	FPGA-based Nintendo Entertainment System Emulator
231	70	110	29 days ago	f4pga-examples/78	Example designs showing different ways to use F4PGA toolchains.
228	88	1	5 years ago	sdram-controller/79	Verilog SDRAM memory controller
226	61	4	7 months ago	nandland/80	All code found on nandland is here. underconstruction.gif
224	7	0	a month ago	Analogue_Pocket_Neogeo/81	Analogue Pocket Neogeo Core compatible with openFPGA
220	43	2	10 months ago	ice40-playground/82	Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
219	189	0	1 year, 3 months ago	fpga/83	The USRP™ Hardware Driver FPGA Repository
219	51	4	3 years ago	raven-picorv32/84	Silicon-validated SoC implementation of the PicoSoc/PicoRV32
219	83	7	11 months ago	SCALE-MAMBA/85	Repository for the SCALE-MAMBA MPC system
214	61	8	7 months ago	openc906/86	OpenXuantie - OpenC906 Core
208	25	7	1 year, 9 months ago	twitchcore/87	It's a core. Made on Twitch.
206	66	5	1 year, 1 month ago	HDL-Bits-Solutions/88	This is a repository containing solutions to the problem statements given in HDL Bits website.
202	57	45	3 months ago	ao486_MiSTer/89	ao486 port for MiSTer
200	46	0	4 months ago	wbuart32/90	A simple, basic, formally verified UART controller
199	47	22	1 year, 1 month ago	Cores-SweRVolf/91	FuseSoC-based SoC for SweRV EH1
195	95	0	3 years ago	AMBA_AXI_AHB_APB/92	AMBA bus lecture material
188	35	7	4 years ago	TinyFPGA-B-Series/93	Open source design files for the TinyFPGA B-Series boards.
185	42	5	4 months ago	ZYNQ-NVDLA/94	NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
184	30	1	4 years ago	SimpleVOut/95	A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
181	11	1	4 years ago	fpga-chip8/96	CHIP-8 console on FPGA
177	36	7	4 years ago	DisplayPort_Verilog/97	A Verilog implementation of DisplayPort protocol for FPGAs
177	47	96	6 days ago	bsg_manycore/98	Tile based architecture designed for computing efficiency, scalability and generality
172	43	1	15 hours ago	livehd/99	Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
171	14	0	8 months ago	fpg1/100	FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.
171	20	0	8 years ago	ez8/101	The Easy 8-bit Processor
169	98	4	9 years ago	uvm_axi/102	uvm AXI BFM(bus functional model)
169	61	5	3 years ago	Tang_E203_Mini/103	LicheeTang 蜂鸟E203 Core
168	68	0	2 years ago	RePlAce/104	RePlAce global placement tool
168	42	0	1 year, 23 days ago	Single_instruction_cycle_OpenMIPS/105	通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
167	54	1	1 year, 5 months ago	core_ddr3_controller/106	A DDR3 memory controller in Verilog for various FPGAs
166	35	2	3 years ago	usbcorev/107	A full-speed device-side USB peripheral core written in Verilog.
164	37	2	7 months ago	Colorlight-FPGA-Projects/108	current focus on Colorlight i5 and i9 module
163	58	25	3 years ago	open-register-design-tool/109	Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
160	37	4	11 months ago	ice40_ultraplus_examples/110	Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
159	18	9	3 months ago	Digital-IDE/111	在vscode上的数字设计开发插件
159	17	4	16 hours ago	amiga_replacement_project/112	This is an attempt to make clean Verilog sources for each chip on the Amiga.
156	35	4	10 months ago	FPGA-peripherals/113	🌱 ❄️ Collection of open-source peripherals in Verilog
156	26	1	3 years ago	display_controller/114	FPGA display controller with support for VGA, DVI, and HDMI.
156	55	1	2 years ago	schoolMIPS/115	CPU microarchitecture, step by step
153	56	4	3 years ago	xk265/116	xk265：HEVC/H.265 Video Encoder IP Core (RTL)
151	56	4	9 years ago	fpganes/117	NES in Verilog
151	6	2	5 days ago	minimax/118	Minimax: a Compressed-First, Microcoded RISC-V CPU
151	186	57	21 hours ago	OpenROAD-flow-scripts/119	OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
147	45	93	20 days ago	caravel/120	Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
146	75	3	6 years ago	FPGA_Based_CNN/121	FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
145	28	0	6 years ago	archexp/122	浙江大学计算机体系结构课程实验
143	61	65	28 days ago	fomu-workshop/123	Support files for participating in a Fomu workshop
141	13	1	1 year, 9 months ago	fedar-f1-rv64im/124	5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
141	26	4	10 months ago	usb3_pipe/125	USB3 PIPE interface for Xilinx 7-Series
141	37	3	a month ago	iceGDROM/126	An FPGA based GDROM emulator for the Sega Dreamcast
138	41	0	9 years ago	milkymist/127	SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
138	44	1	1 year, 3 months ago	FPGAandCNN/128	基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
138	133	25	1 year, 4 months ago	caravel_mpw-one/129	Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
136	26	1	11 months ago	a2o/130	None
134	18	0	5 years ago	vm80a/131	i8080 precise replica in Verilog, based on reverse engineering of real die
134	13	3	1 year, 7 months ago	icestation-32/132	Compact FPGA game console
133	57	0	1 year, 11 months ago	async_fifo/133	A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
132	79	5	5 years ago	Hardware-CNN/134	A convolutional neural network implemented in hardware (verilog)
132	46	5	2 days ago	libsystemctlm-soc/135	SystemC/TLM-2.0 Co-simulation framework
132	20	7	1 year, 8 months ago	DreamcastHDMI/136	Dreamcast HDMI
130	20	1	14 days ago	cpu11/137	Revengineered ancient PDP-11 CPUs, originals and clones
129	39	0	5 years ago	mriscv/138	A 32-bit Microcontroller featuring a RISC-V core
129	74	1	7 years ago	or1200/139	OpenRISC 1200 implementation
128	26	1	5 years ago	RISC-V-CPU/140	RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
127	19	2	2 years ago	lpc_sniffer_tpm/141	A low pin count sniffer for ICEStick - targeting TPM chips
127	46	1	2 years ago	CNN-FPGA/142	Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
125	49	1	1 year, 2 months ago	DetectHumanFaces/143	Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
124	78	14	4 years ago	orpsoc-cores/144	Core description files for FuseSoC
122	27	5	1 year, 2 months ago	Toooba/145	RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
122	13	0	11 months ago	vgasim/146	A Video display simulator
121	12	4	13 hours ago	breaks/147	Nintendo Entertainment System (NES) / Famicom / Famiclones chip reversing
121	23	5	2 years ago	core_jpeg/148	High throughput JPEG decoder in Verilog for FPGA
121	20	3	2 years ago	panologic-g2/149	Pano Logic G2 Reverse Engineering Project
120	52	1	10 years ago	fft-dit-fpga/150	Verilog module for calculation of FFT.
120	37	2	1 year, 5 months ago	icebreaker-verilog-examples/151	This repository contains small example designs that can be used with the open source icestorm flow.
117	81	1	2 years ago	Practical-UVM-Step-By-Step/152	This is the main repository for all the examples for the book Practical UVM
117	40	1	2 years ago	SM3_core/153	None
117	65	26	29 days ago	NeoGeo_MiSTer/154	NeoGeo for MiSTer
116	44	62	29 days ago	Minimig-AGA_MiSTer/155	None
116	8	0	1 year, 10 months ago	riskow/156	Learning how to make a RISC-V
116	51	1	1 year, 2 months ago	ivtest/157	Regression test suite for Icarus Verilog. (OBSOLETE)
116	47	6	2 years ago	vsdflow/158	VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
116	30	0	3 years ago	mips32-cpu/159	奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
116	86	0	4 years ago	FPGA-CNN/160	FPGA implementation of Cellular Neural Network (CNN)
115	63	52	28 days ago	Genesis_MiSTer/161	Sega Genesis for MiSTer
115	51	3	2 years ago	neuralNetwork/162	None
114	32	0	8 years ago	cpu/163	A very primitive but hopefully self-educational CPU in Verilog
114	19	9	4 months ago	icesugar-pro/164	iCESugar series FPGA dev board
113	26	12	7 days ago	SOFA/165	SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
113	11	11	3 days ago	VGChips/166	Video Game custom chips reverse-engineered from silicon
113	32	7	2 years ago	tinyfpga_bx_usbserial/167	USB Serial on the TinyFPGA BX
113	67	5	8 years ago	DSLogic-hdl/168	An open source FPGA design for DSLogic
113	32	2	2 years ago	apple-one/169	An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
112	28	4	8 months ago	MobileNet-in-FPGA/170	Generator of verilog description for FPGA MobileNet implementation
112	267	67	20 days ago	caravel_user_project/171	https://caravel-user-project.readthedocs.io
111	66	3	10 days ago	xkISP/172	xkISP：Xinkai ISP IP Core (HLS)
111	45	1	5 years ago	clacc/173	Deep Learning Accelerator (Convolution Neural Networks)
111	6	0	1 year, 6 months ago	RaspberryPiAtomicNixieClock/174	None
111	47	10	3 years ago	Tang_FPGA_Examples/175	LicheeTang FPGA Examples
110	33	7	9 months ago	corescore/176	CoreScore
108	19	1	7 years ago	oldland-cpu/177	Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
107	25	1	11 months ago	introduction-to-fpga/178	None
106	69	6	5 years ago	Convolutional-Neural-Network/179	Implementation of CNN using Verilog
106	14	3	27 days ago	jt12/180	FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
105	10	1	2 years ago	antikernel/181	The Antikernel operating system project
105	28	3	30 days ago	aib-phy-hardware/182	Advanced Interface Bus (AIB) die-to-die hardware open source
104	4	10	5 months ago	openFPGA-Genesis/183	FPGA implementation of Sega Genesis for Analogue Pocket.
104	33	0	3 years ago	NaiveMIPS-HDL/184	Naïve MIPS32 SoC implementation
104	23	0	2 years ago	openarty/185	An Open Source configuration of the Arty platform
103	26	2	18 days ago	iob-cache/186	Verilog configurable cache
103	13	0	6 years ago	PonyLink/187	A single-wire bi-directional chip-to-chip interface for FPGAs
103	29	1	1 year, 13 days ago	dspfilters/188	A collection of demonstration digital filters
102	44	3	2 years ago	cnn_hardware_acclerator_for_fpga/189	This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
102	9	2	2 months ago	fpga_pio/190	An attempt to recreate the RP2040 PIO in an FPGA
102	21	5	7 years ago	NeoGeoHDMI/191	Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI
101	15	63	3 hours ago	jtcores/192	FPGA cores compatible with multiple arcade game machines
101	29	5	3 years ago	Reindeer/193	PulseRain Reindeer - RISCV RV32I[M] Soft CPU
100	48	1	6 months ago	cdbus/194	CDBUS Protocol and the IP Core for FPGA users
100	33	1	6 years ago	kamikaze/195	Light-weight RISC-V RV32IMC microcontroller core.
100	12	58	4 years ago	spatial-lang/196	Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
99	14	4	30 days ago	ice-chips-verilog/197	IceChips is a library of all common discrete logic devices in Verilog
99	19	0	1 year, 8 months ago	Fuxi/198	Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
99	54	4	7 months ago	opene906/199	OpenXuantie - OpenE906 Core
98	2	3	3 months ago	frankenpi/200	None
98	36	2	18 hours ago	Haasoscope/201	Docs, design, firmware, and software for the Haasoscope
97	43	0	9 years ago	uart/202	Verilog UART
95	12	0	7 years ago	cpus-caddr/203	FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
95	19	0	10 months ago	agc_simulation/204	Verilog simulation files for a replica of the Apollo Guidance Computer
95	34	8	3 years ago	mipsfpga-plus/205	MIPSfpga+ allows loading programs via UART and has a switchable clock
95	14	1	4 years ago	iCE40/206	Lattice iCE40 FPGA experiments - Work in progress
94	47	1	a month ago	opene902/207	OpenXuantie - OpenE902 Core
94	9	2	1 year, 9 months ago	vt52-fpga/208	None
94	35	0	3 years ago	R8051/209	8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
94	26	2	3 years ago	MIPS-pipeline-processor/210	A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
94	26	1	5 years ago	SoftMC/211	SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf
94	23	7	2 years ago	ice40_examples/212	Public examples of ICE40 HX8K examples using Icestorm
93	31	3	5 months ago	benchmarks/213	EPFL logic synthesis benchmarks
93	17	1	23 days ago	OpenCGRA/214	OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
91	31	2	9 years ago	Xilinx-Serial-Miner/215	Bitcoin miner for Xilinx FPGAs
91	29	0	4 years ago	NPU_on_FPGA/216	在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
90	28	0	8 years ago	lm32/217	LatticeMico32 soft processor
89	17	0	1 year, 4 months ago	icebreaker-workshop/218	iCEBreaker Workshop
88	53	6	1 year, 1 month ago	spi-slave/219	SPI Slave for FPGA in Verilog and VHDL
88	32	0	7 years ago	Verilog-caches/220	Various caches written in Verilog-HDL
88	9	1	12 years ago	Homotopy/221	Homotopy theory in Coq.
88	12	0	1 year, 7 months ago	NeoGeoFPGA-sim/222	Simulation only cartridge NeoGeo hardware definition
87	13	5	2 months ago	colorlight-led-cube/223	64x64 LED Cube based on the Colorlight 5a-75B LED driver board.
87	43	7	8 months ago	SD-card-controller/224	WISHBONE SD Card Controller IP Core
87	9	4	5 days ago	nestang/225	NESTang is a Nintendo Entertainment System emulator on the affordable Sipeed Tang Primer 20K FPGA board.
87	31	0	1 year, 1 month ago	CNN-On-FPGA/226	FPGA
86	36	1	4 years ago	zynq-axis/227	Hardware, Linux Driver and Library for the Zynq AXI DMA interface
86	60	2	1 year, 7 months ago	LimeSDR-USB_GW/228	Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board
86	15	10	4 days ago	MacroPlacement/229	Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source
85	26	1	8 years ago	verilog_fixed_point_math_library/230	Fixed Point Math Library for Verilog
85	12	3	6 years ago	fpgaboy/231	Implementation Nintendo's GameBoy console on an FPGA
84	47	1	4 years ago	ethernet_10ge_mac_SV_UVM_tb/232	SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
84	33	0	4 years ago	PASC/233	Parallel Array of Simple Cores. Multicore processor.
83	24	1	2 years ago	ARM_Cortex-M3/234	该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求，在FPGA上搭建Cortex-M3软核、图像协处理器，并通过OV5640摄像头采集车牌图像，实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核，依据AHB-Lite总线协议，将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端，设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据（对应20张车牌）存储在RAM中，输出至AHB总线，由Cortex-M3调用并显示识别结果。
83	46	8	27 days ago	Gameboy_MiSTer/235	Gameboy for MiSTer
83	30	0	4 years ago	8-bits-RISC-CPU-Verilog/236	Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
83	39	9	2 years ago	c5soc_opencl/237	DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
83	30	27	29 days ago	DFFRAM/238	Standard Cell Library based Memory Compiler using FF/Latch cells
83	45	3	10 years ago	Icarus/239	DUAL Spartan6 Development Platform
82	1	11	21 days ago	pixel-wrangler/240	HDMI to whatever adapter
82	31	7	3 years ago	ODIN/241	ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
82	36	0	1 year, 6 months ago	cdpga/242	FPGA core boards / evaluation boards based on CDCTL hardware
81	24	15	5 years ago	c65gs/243	FPGA-based C64 Accelerator / C65 like computer
81	16	1	2 years ago	screen-pong/244	Pong game in a FPGA.
81	11	8	2 months ago	xcrypto/245	XCrypto: a cryptographic ISE for RISC-V
80	18	0	4 years ago	riscv/246	Verilog implementation of a RISC-V core
79	21	2	3 years ago	Verilog-Projects/247	This repository contains source code for past labs and projects involving FPGA and Verilog based designs
79	31	0	4 years ago	mnist_fpga/248	using xilinx xc6slx45 to implement mnist net
78	55	0	7 years ago	IPCORE/249	None
78	25	1	10 years ago	Multiplier16X16/250	Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
78	2	0	6 months ago	PDP-1/251	None
78	19	0	1 year, 2 months ago	UltraMIPS_NSCSCC/252	UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
78	14	0	2 years ago	mc6809/253	Cycle-Accurate MC6809/E implementation, Verilog
77	32	0	4 years ago	VidorFPGA/254	repository for Vidor FPGA IP blocks and projects
77	38	3	3 years ago	verilog-cam/255	Verilog Content Addressable Memory Module
76	16	4	11 months ago	OpenSERDES/256	Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
76	21	3	6 years ago	FPU/257	IEEE 754 floating point unit in Verilog
76	18	1	8 months ago	sdspi/258	SD-Card controller, using a SPI interface that is (optionally) shared
76	14	0	4 years ago	toygpu/259	A simple GPU on a TinyFPGA BX
76	11	3	3 years ago	ay-3-8910_reverse_engineered/260	The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.
76	28	2	4 years ago	ARM-LEGv8/261	Verilog Implementation of an ARM LEGv8 CPU
75	8	7	a day ago	vicii-kawari/262	Commodore 64 VIC-II 6567/6569 Replacement Project
75	11	0	5 months ago	rt/263	A Full Hardware Real-Time Ray-Tracer
74	16	3	11 years ago	ao68000/264	The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
73	21	48	9 months ago	tapasco/265	The Task Parallel System Composer (TaPaSCo)
73	11	0	6 years ago	FPGA-TX/266	FPGA based transmitter
73	4	1	6 months ago	xenowing/267	"What comes next? Super Mario 128? Actually, that's what I want to do."
73	14	0	3 years ago	MARLANN/268	Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
72	20	0	5 years ago	ECE1373_2016_hft_on_fpga/269	High Frequency Trading using Vivado HLS
72	18	0	3 years ago	BUAA_CO/270	2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
71	37	8	5 years ago	nysa-sata/271	None
71	21	4	2 years ago	basic-ecp5-pcb/272	Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
71	7	2	2 months ago	GottaGoFastRAM/273	8MB Autoconfig FastRAM for Amiga 500/1000/2000/CDTV
70	12	0	3 months ago	steel-core/274	Processor core implementing the base RV32I instruction set of the RISC-V ISA
70	8	10	10 months ago	circuitgraph/275	Tools for working with circuits as graphs in python
70	31	13	8 months ago	LSOracle/276	IDEA project source files
70	10	0	a month ago	iCE40linux/277	Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
70	20	0	6 months ago	2021_Spring_NCTU_ICLAB/278	NCTU 2021 Spring Integrated Circuit Design Laboratory
70	27	2	3 years ago	daisho/279	Test of the USB3 IP Core from Daisho on a Xilinx device
70	22	0	1 year, 8 months ago	dpll/280	A collection of phase locked loop (PLL) related projects
69	27	1	19 years ago	8051/281	8051 core
69	22	2	3 years ago	freepdk-45nm/282	ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
69	17	3	12 days ago	sha3/283	None
69	16	0	4 years ago	hyperram/284	Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
69	14	2	1 year, 10 months ago	up5k/285	Upduino v2 with the ice40 up5k FPGA demos
68	7	15	2 years ago	hrm-cpu/286	Human Resource Machine - CPU Design #HRM
68	11	2	3 years ago	Riscy-SoC/287	Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
68	27	8	2 years ago	i3c-slave-design/288	MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
68	10	0	1 year, 5 months ago	OpenAmiga500FastRamExpansion/289	4/8 MB Fast RAM Expansion for the Commodore Amiga 500
67	10	0	a month ago	OpenSpike/290	Fully opensource spiking neural network accelerator
66	9	1	5 years ago	lpc_sniffer/291	a low pin count sniffer for icestick
66	23	1	4 years ago	ARM7/292	Implemetation of pipelined ARM7TDMI processor in Verilog
66	7	2	1 year, 8 months ago	openlogicbit/293	Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
66	13	1	2 years ago	MIPS-Processor/294	5-stage pipelined 32-bit MIPS microprocessor in Verilog
66	9	0	4 months ago	core-template/295	A template for getting started with FPGA core development
66	24	0	6 months ago	drec-fpga-intro/296	Materials for "Introduction to FPGA and Verilog" at MIPT DREC
65	41	75	2 days ago	yosys-f4pga-plugins/297	Plugins for Yosys developed as part of the F4PGA project.
65	34	2	6 years ago	h.265_encoder/298	None
64	13	1	3 years ago	Speech256/299	An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
64	22	0	5 years ago	MIPS/300	A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
63	9	2	3 years ago	panologic/301	PanoLogic Zero Client G1 reverse engineering info
62	26	1	3 years ago	ethmac/302	Ethernet MAC 10/100 Mbps
62	6	0	2 years ago	wbscope/303	A wishbone controlled scope for FPGA's
62	26	3	8 months ago	Basic-SIMD-Processor-Verilog-Tutorial/304	Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
62	22	0	3 years ago	SIGMA/305	RTL implementation of Flex-DPE.
62	15	0	4 years ago	VexRiscvSoftcoreContest2018/306	None
62	38	4	5 months ago	bch_verilog/307	Verilog based BCH encoder/decoder
61	15	0	3 years ago	tiny-tpu/308	Small-scale Tensor Processing Unit built on an FPGA
61	38	3	5 years ago	digital-servo/309	NIST digital servo: an FPGA based fast digital feedback controller
61	17	0	1 year, 1 month ago	fpga-md5-cracker/310	A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.
61	19	3	10 years ago	ORGFXSoC/311	An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
61	27	0	8 months ago	CNN_for_SLR/312	A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
60	20	1	4 years ago	FPGA-Accelerator-for-AES-LeNet-VGG16/313	FPGA/AES/LeNet/VGG16
60	21	0	1 year, 6 months ago	Solutions-to-HDLbits-Verilog-sets/314	Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
60	29	0	11 years ago	dma_axi/315	AXI DMA 32 / 64 bits
60	22	3	2 years ago	verilog-math/316	Mathematical Functions in Verilog
60	21	3	5 years ago	Processor-UVM-Verification/317	System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
60	25	3	3 years ago	riscv_soc/318	Basic RISC-V Test SoC
60	38	37	7 years ago	minimig-mist/319	Minimig for the MiST board
59	4	1	3 years ago	flickerfixer/320	An open source flicker fixer for Amiga 500/2000
58	26	0	2 years ago	timetoexplore/321	Source code to accompany https://timetoexplore.net
58	14	1	2 years ago	fpga-sdft/322	sliding DFT for FPGA, targetting Lattice ICE40 1k
58	17	1	2 months ago	aib-phy-hardware/323	None
57	33	28	28 days ago	MegaCD_MiSTer/324	Mega CD for MiSTer
57	9	0	2 years ago	core_dvi_framebuffer/325	Minimal DVI / HDMI Framebuffer
57	18	3	4 months ago	wokwi-verilog-gds-test/326	None
57	12	1	10 months ago	verilog-65C02-microcode/327	65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
57	22	0	3 years ago	TPU-Tensor-Processing-Unit/328	IC implementation of TPU
57	19	0	5 years ago	caribou/329	Caribou: Distributed Smart Storage built with FPGAs
57	9	0	17 hours ago	Hazard3/330	3-stage RV32IMACZb* processor with debug
57	17	0	2 years ago	XilinxUnisimLibrary/331	Xilinx Unisim Library in Verilog
57	18	2	2 years ago	fpga-ml-accelerator/332	This repository hosts the code for an FPGA based accelerator for convolutional neural networks
57	36	3	5 years ago	prog_fpgas/333	The repository for the Verilog code examples and ISE projects that accompany the book Programming FPGAs: Getting Started with Verilog.
57	16	0	2 years ago	hardenedlinux_profiles/334	It contains hardenedlinux community documentation.
56	16	2	6 months ago	CPU/335	单周期 8指令 MIPS32CPU
56	29	0	7 years ago	stx_cookbook/336	Altera Advanced Synthesis Cookbook 11.0
56	1	0	7 days ago	ethernet/337	WIP 100BASE-TX PHY
56	27	1	5 years ago	TOE/338	TCP Offload Engine
56	6	2	6 years ago	Frix/339	IBM PC Compatible SoC for a commercially available FPGA board
56	8	47	2 years ago	rigel/340	Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
55	15	2	3 years ago	RISC-V-CPU/341	A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
55	2	0	4 years ago	soc/342	An experimental System-on-Chip with a custom compiler toolchain.
55	3	0	4 months ago	caravel_ft8_receiver/343	A fully-integrated FT8 protocol receiver on 130nm CMOS
55	4	1	2 years ago	gameboy-fpga-cartridge/344	None
54	7	0	2 years ago	sdram-controller/345	Generic FPGA SDRAM controller, originally made for AS4C4M16SA
54	18	1	3 years ago	DSP-RTL-Lib/346	RTL Verilog library for various DSP modules
54	13	6	2 years ago	icestick-lpc-tpm-sniffer/347	FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit
54	21	1	1 year, 10 months ago	opencpi/348	Open Component Portability Infrastructure
54	10	0	3 years ago	fpga-odysseus/349	FPGA Odysseus with ULX3S
54	1	1	2 months ago	openfpga-pong/350	FPGA Pong implementation, specifically for the Analogue Pocket
54	20	0	2 years ago	Image-Classification-using-CNN-on-FPGA/351	Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
54	14	0	2 years ago	trng/352	True Random Number Generator core implemented in Verilog.
54	18	13	3 years ago	alpha-release/353	Builds, flow and designs for the alpha release
54	21	1	3 years ago	Open_RegModel/354	🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
54	16	0	a month ago	Bluster/355	CPLD Replacement for A2000 Buster
54	30	0	5 years ago	Examples-in-book-write-your-own-cpu/356	《自己动手写CPU》一书附带的文件
53	11	0	5 years ago	mips-cpu/357	A MIPS CPU implemented in Verilog
53	38	1	3 years ago	AlteraDE2Labs_Verilog/358	My solutions to Alteras example labs
53	27	0	5 years ago	H264/359	H264视频解码verilog实现
53	28	0	8 months ago	NandFlashController/360	AXI Interface Nand Flash Controller (Sync mode)
53	25	13	3 hours ago	jtframe/361	Common framework for MiST(er), PocketFPGA, SiDi, NeptUNO (mc/mc2) core development. With special focus on arcade cores.
53	7	1	2 years ago	iua/362	ice40 USB Analyzer
52	10	0	3 years ago	up5k_basic/363	A small 6502 system with MS BASIC in ROM
52	11	3	10 months ago	cnnhwpe/364	None
52	44	2	3 months ago	oc-accel/365	OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
52	12	0	5 years ago	Computer-Architecture-Task-2/366	Riscv32 CPU Project
52	0	0	1 year, 6 months ago	MIPS-Microsystems/367	A computer system containing CPU, OS and Compiler under MIPS architecture.
52	37	9	20 hours ago	Template_MiSTer/368	Template with latest framework for MiSTer
52	15	0	2 years ago	first-fpga-pcb/369	FPGA dev board based on Lattice iCE40 8k
52	34	1	7 years ago	mips32r1_xum/370	A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old University of Utah XUM archive)
52	14	0	2 years ago	challenges-2020/371	Pwn2Win 2020 Challenges
51	28	1	5 years ago	fpga_design/372	这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
51	21	2	13 years ago	round_robin_arbiter/373	round robin arbiter
51	5	0	6 years ago	21FX/374	A bootloader for the SNES console
51	7	13	3 years ago	Neogeo_MiSTer_old/375	SNK NeoGeo core for the MiSTer platform
51	25	2	2 years ago	ARM9-compatible-soft-CPU-core/376	This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
51	13	0	3 years ago	core_audio/377	Audio controller (I2S, SPDIF, DAC)
51	14	0	6 years ago	sds7102/378	A port of Linux to the OWON SDS7102 scope
51	12	0	1 year, 4 months ago	FPGA-Build/379	A novel architectural design for stitching video streams in real-time on an FPGA.
51	24	0	1 year, 10 months ago	ARM_AMBA_Design/380	Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
50	18	43	16 days ago	zx-evo/381	TS-Configuration for ZX Spectrum clone named ZX-Evolution
50	11	0	2 years ago	sdr/382	A basic Soft(Gate)ware Defined Radio architecture
50	16	2	5 years ago	chiphack/383	Repository and Wiki for Chip Hack events.
50	28	0	11 years ago	DDR2_Controller/384	DDR2 memory controller written in Verilog
50	14	3	a month ago	iceZ0mb1e/385	FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
49	15	0	4 years ago	DIY_OpenMIPS/386	實作《自己動手寫CPU》書上的程式碼
49	10	6	2 years ago	74xx-liberty/387	None
49	9	0	a month ago	difuzz-rtl/388	None
49	28	3	8 years ago	beagle/389	BeagleBone HW, SW, & FPGA Development
49	13	0	4 years ago	HyperBUS/390	A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
49	3	0	4 years ago	collection-iPxs/391	Icestudio Pixel Stream collection
49	17	1	1 year, 4 months ago	uart/392	A simple implementation of a UART modem in Verilog.
49	31	6	9 years ago	Atalanta/393	Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
49	7	1	3 years ago	engine-V/394	SoftCPU/SoC engine-V
49	9	1	4 years ago	BAR-Tender/395	An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver
48	6	1	6 years ago	MAM65C02-Processor-Core/396	Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)
48	6	1	1 year, 4 months ago	SQRL_quickstart/397	Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs
48	9	0	a month ago	SiDi-FPGA/398	SiDi FPGA for retro systems.
48	28	9	1 year, 8 months ago	Parser-Verilog/399	A Standalone Structural Verilog Parser
48	10	1	1 year, 4 months ago	vga-clock/400	Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
48	18	0	5 years ago	robot-arm-v01/401	None
48	40	0	6 months ago	LimeSDR-Mini_GW/402	LimeSDR-Mini board FPGA project
48	29	2	4 years ago	GNSS_Firehose/403	Wideband front-end digitizer for GPS, GLONASS, Galileo, BeiDou
48	23	2	4 years ago	OV7670-Verilog/404	Verilog modules required to get the OV7670 camera working
47	2	0	9 months ago	Quafu/405	A small SoC with a pipeline 32-bit RISC-V CPU.
47	34	0	7 years ago	mojo-base-project/406	This is the base project for the Mojo. It should be used as the starting point for all projects.
47	3	7	3 months ago	Analogue-Amiga/407	Analogue-Amiga
47	5	6	1 year, 1 month ago	SF500/408	Spitfire 500, A low-end 14 MHz Accelerator with IDE and 4/8 MB fast RAM for the Amiga 500.
47	18	1	2 years ago	max1000-tutorial/409	Tutorial and example projects for the Arrow MAX1000 FPGA board
47	2	10	4 months ago	openfpga-arduboy/410	Arduboy for Analogue Pocket
47	14	1	2 years ago	picorv32_Xilinx/411	A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
47	33	3	9 years ago	cordic/412	An implementation of the CORDIC algorithm in Verilog.
47	17	2	2 years ago	qspiflash/413	A set of Wishbone Controlled SPI Flash Controllers
47	12	0	3 years ago	PACoGen/414	PACoGen: Posit Arithmetic Core Generator
46	37	0	1 year, 7 months ago	risc-v-core/415	This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
46	9	6	5 months ago	rj32/416	A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
46	7	1	6 months ago	spam-1/417	Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
46	11	4	1 year, 1 month ago	VirtualTap/418	Mod kit for the Virtual Boy to make it output VGA or RGB video
46	16	0	1 year, 10 months ago	sha1/419	Verilog implementation of the SHA-1 cryptgraphic hash function
45	16	1	4 years ago	openmsp430/420	The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
45	33	0	2 years ago	vsdstdcelldesign/421	This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
45	5	1	7 months ago	A500_ACCEL_RAM_IDE-Rev-2/422	Improved design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
45	24	1	2 years ago	computer-organization-lab/423	中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
45	19	0	4 years ago	de10nano_vgaHdmi_chip/424	Test for video output using the ADV7513 chip on a de10 nano board
45	6	0	1 year, 9 months ago	CNN-Accelerator-VLSI/425	Convolutional accelerator kernel, target ASIC & FPGA
44	9	0	2 years ago	MIPS48PipelineCPU/426	5 stage pipelined MIPS-32 processor
44	9	0	2 years ago	moxie-cores/427	Moxie-compatible core repository
44	15	0	4 years ago	BeagleWire/428	This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017
44	13	0	1 year, 10 months ago	core_usb_cdc/429	Basic USB-CDC device core (Verilog)
44	23	2	7 years ago	nfmac10g/430	Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
44	13	0	4 months ago	spi_mem_programmer/431	Small (Q)SPI flash memory programmer in Verilog
44	20	0	3 years ago	RISC-V-32I/432	体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
44	13	3	1 year, 9 months ago	mipi-demo/433	MIPI CSI-2 + MIPI CCS Demo
43	8	1	3 months ago	cpc_ram_expansion/434	A series of Amstrad CPC PCBs including a backplane, ROM and 512K and 1MByte RAM expansions.
43	7	5	15 days ago	zerosoc/435	Demo SoC for SiliconCompiler.
43	35	0	9 years ago	FPGA_image_processing/436	Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image
43	2	5	11 months ago	spokefpga/437	FPGA Tools and Library
43	25	0	4 months ago	jpegencode/438	JPEG Encoder Verilog
43	10	0	a day ago	xschem_sky130/439	XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
43	19	1	9 months ago	cnn_accelerator/440	【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
43	12	0	12 days ago	HDLGen/441	HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
43	5	0	5 years ago	RISC-processor/442	Simple single cycle RISC processor written in Verilog
43	25	0	4 years ago	huaweicloud-fpga/443	The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
43	19	4	11 months ago	minimig-de1/444	Minimig for the DE1 board
43	10	0	3 years ago	icestick-glitcher/445	Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit
42	10	0	1 year, 1 month ago	ReckOn/446	ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.
42	11	3	3 years ago	Posit-HDL-Arithmetic/447	Universal number Posit HDL Arithmetic Architecture generator
42	4	10	10 months ago	snark-barker-mca/448	A Sound Blaster compatible sound card for Micro Channel bus computers
42	7	0	4 years ago	tiny_usb_examples/449	Using the TinyFPGA BX USB code in user designs
42	14	0	6 years ago	FPGA_Ultrasound/450	CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.
42	10	1	1 year, 8 months ago	core_uriscv/451	Another tiny RISC-V implementation
42	38	0	1 year, 4 months ago	jtag_vpi/452	TCP/IP controlled VPI JTAG Interface.
41	6	0	1 year, 4 months ago	Computer-Organization-BUAA-2020/453	北航6系CO课 BUAA CO
41	9	1	2 years ago	core_soc/454	Basic Peripheral SoC (SPI, GPIO, Timer, UART)
41	14	0	7 years ago	yosys-bigsim/455	A collection of big designs to run post-synthesis simulations with yosys
41	23	0	12 years ago	sparc64soc/456	OpenSPARC-based SoC
40	8	0	3 years ago	ctf/457	Stuff from CTF contests
40	2	0	5 years ago	vga_to_ascii/458	Realtime VGA to ASCII Art converter
40	11	18	5 months ago	simbricks/459	Main Repository for the SimBricks Modular Full-System Simulation Framework.
40	11	0	8 years ago	vj-uart/460	Virtual JTAG UART for Altera Devices
40	9	2	6 years ago	ACC/461	Apollo CPU Core in Verilog. For learning and having fun with open FPGA
40	5	0	2 years ago	CNN-Accelerator-Implementation-based-on-Eyerissv2/462	None
40	6	0	8 years ago	gb/463	The Original Nintendo Gameboy in Verilog
40	14	0	2 years ago	LUTNet/464	None
40	8	1	2 years ago	INT_FP_MAC/465	INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
39	13	0	3 years ago	fpga_image_processing/466	IP operations in verilog (simulation and implementation on ice40)
39	18	6	1 year, 1 month ago	xfcp/467	Extensible FPGA control platform
39	32	0	3 years ago	Ethernet-design-verilog/468	Gigabit Ethernet UDP communication driver
39	8	0	3 days ago	no2bootloader/469	USB DFU bootloader gateware / firmware for FPGAs
39	23	0	7 months ago	thinpad_top/470	Project template for Artix-7 based Thinpad board
39	23	0	6 years ago	ee260_lab/471	EE 260 Winter 2017: Advanced VLSI Design
39	44	1	5 months ago	SparkRoad-V/472	None
39	10	39	3 months ago	mantle/473	mantle library
39	14	0	4 years ago	Convolution-using-systolic-arrays/474	None
39	11	2	10 days ago	airisc_core_complex/475	Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.
39	6	1	2 months ago	RISu064/476	Dual-issue RV64IM processor for fun & learning
39	14	2	5 years ago	CNN_VGG19_verilog/477	Convolution Neural Network of vgg19 model in verilog
39	13	0	3 years ago	Verilog-Adders/478	Implementing Different Adder Structures in Verilog
38	0	0	4 years ago	comparchitecture/479	Verilog and MIPS simple programs
38	8	2	3 years ago	UART/480	ARM中通过APB总线连接的UART模块
38	3	0	7 years ago	HaSKI/481	Cλash/Haskell FPGA-based SKI calculus evaluator
38	10	1	7 years ago	oc_jpegencode/482	Fork of OpenCores jpegencode with Cocotb testbench
38	1	1	1 year, 2 months ago	cxxrtl_eval/483	Experiments with Yosys cxxrtl backend
38	14	0	3 years ago	fpga-gpu/484	A basic GPU for altera FPGAs
38	29	2	3 years ago	block-nvdla-sifive/485	None
38	10	0	7 months ago	enxor-logic-analyzer/486	FPGA Logic Analyzer and GUI
38	16	1	2 years ago	Booth_Multipliers/487	Parameterized Booth Multiplier in Verilog 2001
38	8	0	3 months ago	digital-logic-design/488	This course is given in TOBB ETU for Fall 2022-2023 semester as a second grade lecture. You can find lecture notes and Verilog codes related to the course
38	25	0	11 years ago	tdc-core/489	A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
38	10	0	1 year, 7 months ago	FPGA_Book_Experiments/490	My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
38	9	0	10 years ago	dcpu16/491	Pipelined DCPU-16 Verilog Implementation
38	12	1	a month ago	jelly/492	Original FPGA platform
38	13	1	28 days ago	jt49/493	Verilog clone of YM2149
38	29	0	8 years ago	Open-Source-Network-on-Chip-Router-RTL/494	None
37	13	1	10 years ago	vSPI/495	Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
37	20	0	8 years ago	verilog-utils/496	native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
37	17	0	5 years ago	eddr3/497	mirror of https://git.elphel.com/Elphel/eddr3
37	35	7	29 days ago	Menu_MiSTer/498	None
37	8	1	a month ago	Examples/499	None
37	17	0	2 years ago	vsdmixedsignalflow/500	This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.
37	21	0	5 years ago	usb2_dev/501	USB 2.0 Device IP Core
37	11	0	1 year, 2 months ago	Cookabarra/502	a training-target implementation of rv32im, designed to be simple and easy to understand
37	19	1	2 years ago	fifo/503	Generic FIFO implementation with optional FWFT
37	3	3	2 years ago	observer/504	None
37	10	0	1 year, 10 months ago	Fixed-Floating-Point-Adder-Multiplier/505	16-bit Adder Multiplier hardware on Digilent Basys 3
37	9	0	2 years ago	usb2sniffer/506	USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
37	25	0	14 years ago	xge_mac/507	Ethernet 10GE MAC
37	9	1	a month ago	OpenPhySyn/508	EDA physical synthesis optimization kit
37	19	0	9 years ago	MIPS-Processor-in-Verilog/509	Processor repo
37	12	0	2 months ago	Systolic-array-implementation-in-RTL-for-TPU/510	IC implementation of Systolic Array for TPU
37	13	0	9 months ago	Delta-sigma-ADC-verilog/511	Delta-sigma ADC,PDM audio FPGA Implementation
36	9	0	8 years ago	aoOCS/512	The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.
36	5	1	4 months ago	zbasic/513	A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
36	4	0	6 months ago	Silixel/514	Exploring gate level simulation
36	11	0	2 years ago	RDF-2019/515	DATC RDF
36	6	0	2 years ago	Colorlight-5A-75B/516	Notes for Colorlight-5A-75B.
36	12	0	9 years ago	LVDS-7-to-1-Serializer/517	An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
36	29	1	11 months ago	DDLM/518	Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
36	41	0	5 years ago	sata3_host_controller/519	It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
36	18	20	6 years ago	RetroCade_Synth/520	RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.
36	4	1	3 years ago	icebreaker-candy/521	Eye candy from an iCEBreaker FPGA and a 64×64 LED panel
36	7	1	3 years ago	snes_dejitter/522	NES/SNES 240p de-jitter mod
36	10	0	1 year, 9 months ago	MangoMIPS32/523	A softcore microprocessor of MIPS32 architecture.
36	7	0	a month ago	clockport_pi_interface/524	Amiga clock port to Raspberry Pi interface
36	15	1	7 months ago	evoapproxlib/525	Library of approximate arithmetic circuits
36	7	0	2 years ago	CPU_start_from_0/526	从零开始设计一个CPU (Verilog)
35	20	0	6 years ago	fast/527	FAST
35	19	0	4 days ago	ysyxSoC/528	None
35	8	0	5 years ago	Verilog_Calculator_Matrix_Multiplication/529	This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
35	9	0	10 years ago	lsasim/530	Educational load/store instruction set architecture processor simulator
35	2	1	3 months ago	ddr3-controller/531	A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
35	12	5	2 years ago	verilog-uart/532	Simple 8-bit UART realization on Verilog HDL.
35	25	4	28 days ago	ZX-Spectrum_MISTer/533	None
35	13	1	2 years ago	polyphony/534	3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
35	13	0	1 year, 7 months ago	Introduction-to-Computer-Architecture-Exercises/535	计算机体系结构 2020秋季 UCAS 《计算机体系结构基础》第 2 版课后习题
35	18	1	2 years ago	Icarus_Verilog/536	This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
35	6	3	7 months ago	OpenIRV/537	Open-source thermal camera project
35	28	0	7 years ago	AES-FPGA/538	AES加密解密算法的Verilog实现
35	9	7	a month ago	riscv-formal/539	RISC-V Formal Verification Framework
35	13	0	6 years ago	4-way-set-associative-cache-verilog/540	Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
35	18	1	4 years ago	FPGA-SM3-HASH/541	Description of Chinese SM3 Hash algorithm with Verilog HDL
34	9	0	5 months ago	fpga/542	Collection of projects for various FPGA development boards
34	15	0	5 years ago	HitchHike/543	None
34	12	0	1 year, 8 months ago	fpga-bpf/544	A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark
34	17	0	2 years ago	verilog-starter-tutorials/545	Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
34	14	1	2 years ago	DA_PUF_Library/546	Defense/Attack PUF Library (DA PUF Library)
34	18	0	11 years ago	verilog-sha256/547	Implementation of the SHA256 Algorithm in Verilog
34	10	0	1 year, 8 months ago	Vision-FPGA-SoM/548	tinyVision.ai Vision & Sensor FPGA System on Module
34	1	5	3 years ago	HDL-deflate/549	FPGA implementation of deflate (de)compress RFC 1950/1951
34	4	1	1 year, 18 days ago	AMSGateArray/550	Prototype boards and verilog for development of Xilinx CPLD replacements for the Amstrad 40010 and 40007 gate array chips.
34	14	2	3 years ago	buffets/551	Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
34	18	1	5 years ago	polyphase_filter_prj/552	哈工大软件无线电课设：多相滤波器的原理、实现及其应用，从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果，含答辩PPT、学习笔记和个人总结。
34	15	0	9 years ago	fpganes/553	FPGA-based AI for Super Mario Bros. Designed for an Altera DE2
34	6	0	5 years ago	wiki/554	None
34	9	0	2 years ago	HW-Syn-Lab/555	⚙Hardware Synthesis Laboratory Using Verilog
34	15	0	4 years ago	posture_recognition_CNN/556	To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface.
33	16	3	16 years ago	can/557	CAN Protocol Controller
33	9	1	1 year, 9 months ago	HPS2FPGAmapping/558	SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
33	5	0	5 years ago	s6soc/559	CMod-S6 SoC
33	19	0	2 months ago	schoolWorks/560	Repository of NCKU class slides,exams, and homeworks
33	5	0	5 years ago	OpenFPGA/561	OpenFPGA
33	14	2	5 years ago	NoC-Verilog/562	A verilog implementation for Network-on-Chip
33	13	0	3 years ago	csirx/563	Open-source CSI-2 receiver for Xilinx UltraScale parts
33	4	0	2 years ago	CNNAF-CNN-Accelerator_init/564	CNN-Accelerator based on FPGA developed by verilog HDL.
33	1	0	3 months ago	usb_cdc/565	Full Speed USB interface for FPGA and ASIC designs
33	21	1	7 years ago	Nitro-Parts-lib-SPI/566	Verilog SPI master and slave
33	7	2	4 years ago	iCEstick-UART-Demo/567	This is a simple UART echo test for the iCEstick Evaluation Kit
33	7	0	2 years ago	interpolation/568	Digital Interpolation Techniques Applied to Digital Signal Processing
33	9	0	2 years ago	iverilog-tutorial/569	Quickstart guide on Icarus Verilog.
33	11	0	3 years ago	Uranus/570	Uranus MIPS processor by MaxXing & USTB NSCSCC team
33	4	0	3 years ago	cisco-hwic-3g-cdma/571	Reverse Engineering of the Cisco HWIC-3G-CDMA PCB
32	25	4	5 years ago	Hardware-Implementation-of-AES-Verilog/572	Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
32	0	0	7 months ago	hrt/573	Hot Reconfiguration Technology demo
32	8	0	4 years ago	LeNet_RTL/574	An LeNet RTL implement onto FPGA
32	8	0	1 year, 3 months ago	wbi2c/575	Wishbone controlled I2C controllers
32	11	0	3 years ago	verilog-divider/576	a super-simple pipelined verilog divider. flexible to define stages
32	1	1	4 months ago	LunaPnR/577	LunaPnR is a place and router for integrated circuits
32	19	1	4 years ago	GnuRadar/578	Open-source software defined radar based on the USRP 1 hardware.
32	3	16	2 years ago	QuokkaEvaluation/579	Example projects for Quokka FPGA toolkit
32	14	1	2 years ago	FAST9-Accelerator/580	FAST-9 Accelerator for Corner Detection
32	7	0	2 years ago	HDMI-to-FPGA-to-APA102-Pixels/581	Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI.
32	8	0	1 year, 6 months ago	mpsoc_example/582	None
32	21	1	6 years ago	Propeller_1_Design/583	Propeller 1 design and example files to be run on FPGA boards.
32	12	0	a month ago	chacha/584	Verilog 2001 implementation of the ChaCha stream cipher.
32	6	1	3 months ago	Caster/585	FPGA gateware for Caster EPDC
32	15	1	22 days ago	FPGA_NTP_SERVER/586	A FPGA implementation of the NTP and NTS protocols
32	10	0	7 years ago	CPU/587	Verilog实现的简单五级流水线CPU，开发平台：Nexys3
32	3	0	9 years ago	CPU32/588	Tiny MIPS for Terasic DE0
32	14	1	1 year, 5 months ago	Chisel-FFT-generator/589	FFT generator using Chisel
31	14	0	3 months ago	8bit_MicroComputer_Verilog/590	This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
31	17	0	8 years ago	yafpgatetris/591	Yet Another Tetris on FPGA Implementation
31	4	0	5 years ago	8bit-computer/592	Simple 8-bit computer build in Verilog
31	9	1	8 years ago	azpr_cpu/593	用Altera FPGA芯片自制CPU
31	6	2	3 years ago	datc_robust_design_flow/594	DATC Robust Design Flow.
31	5	2	2 months ago	xyloni/595	This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
31	10	0	2 years ago	INSIDER-System/596	An FPGA-based full-stack in-storage computing system.
31	11	1	3 years ago	SDR-Micron/597	SDR Micron USB receiver
31	7	0	2 years ago	RISC-V/598	A simple RISC-V CPU written in Verilog.
31	8	0	12 years ago	osdvu/599	None
31	13	0	6 years ago	book-examples/600	None
31	8	0	2 years ago	Computer-Experiment-on-the-principle-of-computer-composition/601	杭电计算机学院-《计算机组成原理》上机实验代码工程文件
31	19	0	3 years ago	FPGA_DOCS/602	None
31	16	0	1 year, 10 months ago	Video-and-Image-Processing-Design-Using-FPGAs/603	Video and Image Processing
31	0	0	9 months ago	DigSysDes_EGo1/604	Some code made for digital system design lessons and homework.
31	15	0	6 years ago	ethernet_10ge_mac_SV_tb/605	SystemVerilog testbench for an Ethernet 10GE MAC core
31	13	0	2 years ago	Azure-SDR/606	SW SDR
31	17	0	4 years ago	Open-CryptoNight-ASIC/607	Open source hardware implementation of classic CryptoNight
31	12	0	3 years ago	verilog-mini-demo/608	Verilog极简教程
31	15	2	8 years ago	8051/609	FPGA implementation of the 8051 Microcontroller (Verilog)
30	2	0	4 years ago	riscv-megaproject/610	A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones
30	11	0	11 years ago	Pong/611	Pong game on an FPGA in Verilog.
30	20	0	11 years ago	dma_ahb/612	AHB DMA 32 / 64 bits
30	6	0	a day ago	Bedrock/613	LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
30	6	1	4 years ago	Lichee-Tang/614	Lichee Tang FPGA board examples
30	8	9	5 months ago	OpenHBMC/615	Open-source high performance AXI4-based HyperRAM memory controller
30	22	1	4 months ago	LimeSDR-PCIe_GW/616	Altera Cyclone IV FPGA project for the PCIe LimeSDR board
30	19	0	3 years ago	x393/617	mirror of https://git.elphel.com/Elphel/x393
30	14	1	3 years ago	Verilog-FIR/618	FIR implemention with Verilog
30	9	1	5 years ago	Spartan-Mini-NES/619	An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board.
30	16	0	2 years ago	USB3_MIPI_CSI2_RX_V2_Crosslink_NX/620	MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX with Hard MIPI PHY. Gbps UVC Video Stream Over USB 3.0 with Cypress FX3, Currently WIP
30	35	2	1 year, 4 months ago	VexRiscv-verilog/621	Using VexRiscv without installing Scala
30	3	0	2 years ago	EDSAC/622	FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
30	3	3	4 years ago	time-sleuth/623	Time Sleuth - Open Source Lag Tester
30	23	0	9 years ago	RSA4096/624	4096bit RSA project, with verilog code, python test code, etc
30	23	0	9 years ago	opensketch/625	simulation and netfpga code
30	17	0	2 years ago	verilog-arbiter/626	A look ahead, round-robing parametrized arbiter written in Verilog.
30	19	1	5 years ago	Design-and-Verification-of-LDPC-Decoder/627	- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.
30	8	2	3 days ago	MiSTery/628	Atari ST/STe core for FPGAs
29	11	2	1 year, 5 months ago	NetFPGA-PLUS/629	None
29	8	3	2 months ago	rodinia/630	AGM bitstream utilities and decoded files from Supra
29	5	0	a day ago	ScoreBoard-wTimer/631	Objective of this project was to emulate a Basketball score board, with timer and two teams scores. See readme for pic and more details. Release published v1.0.5
29	4	1	2 months ago	DDR/632	A simple DDR3 memory controller
29	11	1	2 years ago	qemu-hdl-cosim/633	VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
29	2	1	4 months ago	MiSTerFPGA_YC_Encoder/634	All work releated to the YC / NTSC & PAL Encoder for MiSTerFPGA
29	5	0	2 years ago	Async-Karin/635	Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
29	1	0	10 months ago	ulx3s_examples/636	Example Verilog code for Ulx3s
29	3	1	6 years ago	RISCV_Piccolo_v1/637	Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
29	6	3	3 years ago	v-regex/638	A simple regex library for V
29	21	1	8 months ago	apio-examples/639	🌱 Apio examples
29	21	0	5 years ago	FPGA_SM4/640	FPGA implementation of Chinese SM4 encryption algorithm.
29	5	0	6 years ago	Yoshis-Nightmare/641	FPGA Based Platformer Video Game
29	8	0	2 years ago	srgh-matrix-trinity/642	XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.
29	12	3	1 year, 5 months ago	Nitro-Parts-lib-Xilinx/643	This is mainly a simulation library of xilinx primitives that are verilator compatible.
29	19	1	4 months ago	ce2020labs/644	ChipEXPO 2020 Digital Design School Labs
29	10	0	7 years ago	2-way-Set-Associative-Cache-Controller/645	Synthesizable and Parameterized Cache Controller in Verilog
29	19	0	9 years ago	rfid-verilog/646	RFID tag and tester in Verilog
28	6	5	16 days ago	public/647	None
28	10	0	8 months ago	verilog-65C02-fsm/648	None
28	7	1	19 days ago	jtopl/649	Verilog module compatible with Yamaha OPL chips
28	11	2	1 year, 3 months ago	ThymesisFlow/650	Memory Disaggregation on POWER9 with OpenCAPI 3.0 M1 & C1
28	9	1	2 years ago	nand2tetris-iverilog/651	A 16-bit Hack CPU from scratch on FPGA.
28	7	0	3 years ago	hackaday_supercon_2019_logic_noise_FPGA_workshop/652	Hackaday Supercon 2019 Logic Noise Badge Workshop
28	15	0	3 years ago	AD9361_TX_MSK/653	A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
28	7	3	8 days ago	VossII/654	The source code to the Voss II Hardware Verification Suite
28	13	1	4 years ago	trainwreck/655	Original RISC-V 1.0 implementation. Not supported.
28	8	0	1 year, 4 months ago	MIDI-Stepper-Synth-V2/656	Virginia Tech AMP Lab Version of the MIDI Stepper Synth. Uses FPGA and 32 Stepper Motors.
28	7	2	2 years ago	SoC_Automation/657	SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
28	21	3	5 years ago	Cosmos-OpenSSD/658	None
28	7	0	2 months ago	wb_intercon/659	Wishbone interconnect utilities
28	2	4	3 years ago	quark/660	Stack CPU 🚧 Work In Progress 🚧
28	12	3	1 year, 4 months ago	nica/661	An infrastructure for inline acceleration of network applications
28	3	0	2 years ago	PCI2Nano-RTL/662	An open source FPGA PCI core & 8250-Compatible PCI UART core
28	18	0	3 years ago	Zynq-7000-DPU-TRD/663	Zynq-7000 DPU TRD
28	3	0	2 years ago	nintendo-switch-i2s-to-spdif/664	I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal.
28	15	0	3 years ago	Interface-Protocol-in-Verilog/665	Interface Protocol in Verilog
28	13	1	1 year, 3 months ago	My-Digital-IC-Library/666	我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
28	21	3	7 years ago	CAN-Bus-Controller/667	An CAN bus Controller implemented in Verilog
28	9	0	2 years ago	USTC-ComputerArchitecture-2020S/668	Code for "Computer Architecture" in 2020 Spring.
27	19	0	1 year, 8 months ago	sha512/669	Verilog implementation of the SHA-512 hash function.
27	8	0	1 year, 10 months ago	fftdemo/670	A demonstration showing how several components can be compsed to build a simulated spectrogram
27	11	0	3 years ago	verilog-doc/671	All About HDL
27	10	2	1 year, 4 months ago	tonic/672	A Programmable Hardware Architecture for Network Transport Logic
27	6	0	4 months ago	learn-verilog/673	Learn Verilog
27	15	1	9 years ago	turbo8051/674	turbo 8051
27	4	0	1 year, 11 days ago	iic-audiodac-v1/675	Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
27	10	1	1 year, 11 months ago	riscv-soc-cores/676	None
27	17	0	6 years ago	FFT_Verilog/677	FFT implement by verilog_测试验证已通过
27	15	2	2 years ago	KWS-SoC/678	This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
27	12	0	14 years ago	verilog_cordic_core/679	configurable cordic core in verilog
27	16	1	4 years ago	Viterbi-Decoder-in-Verilog/680	An efficient implementation of the Viterbi decoding algorithm in Verilog
27	78	16	20 days ago	caravel_user_project_analog/681	None
27	3	0	1 year, 8 months ago	up5k_osc/682	None
27	6	0	4 years ago	redpid/683	migen + misoc + redpitaya = digital servo
27	23	7	8 years ago	MM/684	Miner Manager
27	4	0	3 days ago	100-Days-of-RTL/685	None
27	9	0	11 years ago	tinycpu/686	Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
27	2	0	3 months ago	rioschip/687	None
27	5	1	8 years ago	Y86-CPU/688	A pipeline CPU in Verilog for the Y86 instruction set.
27	3	0	2 years ago	PCI2Nano-PCB/689	An FPGA/PCI Device Reference Platform
27	10	0	12 years ago	video_stream_scaler/690	Video Stream Scaler
27	10	1	2 years ago	E203plus/691	upgrade to e203 (a risc-v core)
27	11	0	3 years ago	arm_vhdl/692	Portable FPGA project based on the ARM DesignStart bundle with ARM Cortex-M3 processor
27	19	2	10 months ago	iob-mem/693	Verilog behavioral description of various memories
27	9	0	3 years ago	Open-FPGA/694	Devotes to open source FPGA
27	0	0	2 years ago	MIPS54SP-Lifesaver/695	None
26	11	1	5 years ago	arty-glitcher/696	FPGA-based glitcher for the Digilent Arty FPGA development board.
26	12	1	3 years ago	ComputerArchitectureLab/697	This repository is used to release the Labs of Computer Architecture Course from USTC
26	7	1	3 years ago	max2-audio-dac/698	24-bit Stereo Audio DAC for Raspberry Pi
26	5	3	1 year, 3 months ago	StereoCensus/699	Verilog Implementation of the Census Transform Stereo Vision algorithm
26	10	2	2 years ago	Low-Cost-and-Programmable-CRC/700	Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
26	0	1	4 years ago	mera400f/701	MERA-400 in an FPGA
26	3	0	3 months ago	RTL-Coding/702	None
26	8	0	7 months ago	myslides/703	Collection of my presentations
26	6	0	2 years ago	serv_soc/704	SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
26	3	5	a month ago	N-GO/705	None
26	7	0	2 years ago	de10-nano-riscv/706	A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
26	13	0	4 years ago	workshops/707	❄️ 🌟 Workshops with Icestudio and the IceZUM Alhambra board
26	2	2	1 year, 6 months ago	no2muacm/708	Drop In USB CDC ACM core for iCE40 FPGA
26	15	1	3 years ago	matrix-creator-fpga/709	Reference HDL code for the MATRIX Creator's Spartan 6 FPGA
26	15	1	2 years ago	Pepino/710	None
26	8	1	1 year, 9 months ago	VGA1306/711	VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!)
26	12	0	5 months ago	ADC-lvds/712	Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
26	4	0	2 years ago	caravel_fpga250/713	FPGA250 aboard the eFabless Caravel
26	6	7	7 years ago	vector06cc/714	Вектор-06ц в ПЛИС / Vector-06c in FPGA
26	1	0	3 months ago	RISCV-CPU/715	MS108 Course Project, SJTU ACM Class.
25	7	0	4 months ago	jt89/716	sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility
25	9	1	6 years ago	ocpi/717	Semi-private RTL development upstream of OpenCPI - this is not the OpenCPI repo!
25	5	0	1 year, 28 days ago	FPGA-Edge-Detection-Project1/718	FPGA-Edge-Detection-Project1
25	13	12	2 years ago	nanorv32/719	A small 32-bit implementation of the RISC-V architecture
25	3	0	3 years ago	thunderclap-fpga-arria10/720	Thunderclap hardware for Intel Arria 10 FPGA
25	6	1	6 months ago	subservient/721	Small SERV-based SoC primarily for OpenMPW tapeout
25	10	0	4 years ago	pciebench-netfpga/722	pcie-bench code for NetFPGA/VCU709 cards
25	4	0	9 months ago	icesid/723	A C64 SID Chip recreation in FPGA
25	6	0	3 years ago	fpga-examples/724	FPGA examples for 8bitworkshop.com
25	6	0	6 years ago	MesaBusProtocol/725	Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
25	6	1	2 years ago	core_usb_fs_phy/726	USB Full Speed PHY
25	11	0	3 years ago	XCryptCore/727	Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
25	8	0	1 year, 1 month ago	DigitalLogic-Autumn2020/728	复旦大学 数字逻辑与部件设计实验 2020秋
25	5	1	4 days ago	neorv32-verilog/729	♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
25	19	1	5 years ago	nysa-verilog/730	Verilog Repository for GIT
25	16	7	1 year, 13 days ago	rp_lock-in_pid/731	Lock-in and PID application for RedPitaya enviroment
25	14	0	6 years ago	peridot/732	'PERIDOT' - Simple & Compact FPGA board
25	5	0	4 years ago	USB/733	FPGA USB 1.1 Low-Speed Implementation
25	4	0	9 months ago	menshen/734	None
25	17	0	2 years ago	x393_sata/735	mirror of https://git.elphel.com/Elphel/x393_sata
25	13	1	8 years ago	ddk-fpga/736	FPGA HDL Sources.
25	3	0	1 year, 2 months ago	ARMLEG/737	Multi-cycle pipelined ARM-LEGv8 CPU with Forwarding and Hazard Detection.
25	1	1	a month ago	video_lag_tester/738	A low cost HDMI video lag tester.
25	1	0	1 year, 4 months ago	FPGA_RealTime_and_Static_Sobel_Edge_Detection/739	Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
25	13	0	4 years ago	SHA256Hasher/740	SHA-256 IP core for ZedBoard (Zynq SoC)
25	6	0	3 months ago	NeoChips/741	Replacement "chips" for NeoGeo systems
24	7	0	2 years ago	caravel_amsat_txrx_ic/742	None
24	10	0	9 years ago	riscv-invicta/743	A simple RISC-V core, described with Verilog
24	12	0	3 years ago	CyNAPSEv11/744	The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
24	10	0	6 years ago	Make-FPGA/745	Repository of Verilog code for Make:FPGA book Chapters 2 & 3.
24	14	0	4 years ago	face_detect_open/746	A Voila-Jones face detector hardware implementation
24	14	1	10 years ago	ASIC/747	EE 287 2012 Fall
24	5	0	12 years ago	opengg/748	OpenGL-like graphics pipeline on a Xilinx FPGA
24	5	0	4 years ago	bapi-rv32i/749	A extremely size-optimized RV32I soft processor for FPGA.
24	1	0	1 year, 5 months ago	verilog-coding-standard/750	Recommended coding standard of Verilog and SystemVerilog.
24	8	0	9 months ago	General-Slow-DDR3-Interface/751	A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
24	7	1	5 years ago	iir-bandstop-filter/752	Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
24	18	1	7 years ago	Asynchronous-FIFO/753	Asynchronous fifo in verilog
24	3	0	2 years ago	EI332/754	SJTU EI332 CPU完整实验代码及报告
24	3	2	2 days ago	gateware/755	IP submodules, formatted for easier CI integration
24	7	0	11 years ago	aemb/756	Multi-threaded 32-bit embedded core family.
24	8	0	3 years ago	tinyfpga_examples/757	Verilog example programs for TinyFPGA
24	6	1	7 years ago	nes_mappers/758	NES mappers
24	9	1	8 years ago	ws2812-verilog/759	This is a Verilog module to interface with WS2812-based LED strips.
24	7	0	5 years ago	computer-systems-ucas/760	中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
24	4	1	2 years ago	legv8/761	LEGv8 CPU implementation and some tools like a LEGv8 assembler
24	10	0	2 years ago	FFT_ChipDesign/762	A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
24	14	0	9 months ago	OpenTSN2.0/763	an opensource project to enable TSN research, including distributed and centralized version.
24	21	0	2 months ago	Digital-Design/764	Verilog HDL files
24	4	0	2 years ago	3DORGB/765	RGB Project for most 3DO consoles.
24	4	0	2 years ago	mips-cpu/766	💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
24	13	1	7 years ago	i2c-master/767	An i2c master controller implemented in Verilog
24	2	0	1 year, 4 months ago	ws2812-core/768	verilog core for ws2812 leds
23	13	0	6 years ago	axi-ddr3/769	学习AXI接口，以及xilinx DDR3 IP使用
23	7	0	a month ago	FPGA-stereo-Camera-Basys3/770	Integration of two camera modules to Basys 3 FPGA
23	0	0	9 days ago	FPGA-Game-Design/771	Fireboy & Water Girl in the Forest Temple implemented on an FPGA board for UIUC's ECE385 Digital Systems Laboratory.
23	13	8	5 years ago	pars/772	None
23	9	0	3 years ago	3x3_matrix_Systolic_Array_multiplier/773	3×3脉动阵列乘法器
23	2	0	1 year, 1 month ago	NoobsCpu-8bit/774	A simple 8bit CPU.
23	10	2	1 year, 11 months ago	microshift_compression/775	Microshift Compression: An Efficient Image Compression Algorithm for Hardware
23	12	0	7 years ago	Hardware_circular_buffer_controller/776	This is a circular buffer controller used in FPGA.
23	8	1	5 years ago	JPEG-Decoder/777	Verilog Code for a JPEG Decoder
23	1	0	6 months ago	ucisc/778	None
23	11	0	2 years ago	00_Image_Rotate/779	视频旋转（2019FPGA大赛）
23	3	0	29 days ago	dbgbus/780	A collection of debugging busses developed and presented at zipcpu.com
23	2	0	3 years ago	enigmaFPGA/781	Enigma in FPGA
23	0	0	9 months ago	DSTB/782	David's ST Booster
23	1	0	5 days ago	eth10g/783	10Gb Ethernet Switch
23	4	0	4 years ago	verifla/784	Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
23	23	0	5 years ago	SIMD-architecture/785	Overall multi-core SIMD microarchitecture
23	8	2	3 months ago	tinytapeout-mpw7/786	TinyTapeout-01 submission repo
23	9	0	4 years ago	Computer-Organization-and-Architecture-LAB/787	Solution to COA LAB Assgn, IIT Kharagpur
23	20	2	2 years ago	blake2/788	Hardware implementation of the blake2 hash function
23	7	0	5 months ago	Butterfly_Acc/789	The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"
23	2	0	6 years ago	QuickSilverNEO/790	None
23	10	0	1 year, 10 months ago	vivado-ip-cores/791	IP Cores that can be used within Vivado
23	1	0	2 years ago	Hardware_Design/792	None
23	10	3	3 years ago	s7_mini_fpga/793	Example designs for the Spartan7 "S7 Mini" FPGA board
23	10	0	1 year, 4 months ago	core_spiflash/794	SPI-Flash XIP Interface (Verilog)
23	17	1	5 years ago	c64-dodgypla/795	Commodore 64 PLA replacement
23	0	0	5 months ago	openfpga-dominos/796	FPGA implementation of Arcade Dominos (Atari, 1977) for Analogue Pocket.
23	6	0	4 years ago	MIPS-Verilog/797	MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.
23	10	1	8 years ago	apbi2c/798	APB to I2C
23	10	0	5 years ago	Centaur/799	Centaur, a framework for hybrid CPU-FPGA databases
23	7	3	2 years ago	UPduino-v2.1/800	UPduino
23	7	3	2 years ago	UPduino-v2.1/801	UPduino
23	1	0	2 years ago	Life_MiSTer/802	Conway's Game of Life in FPGA
23	6	1	2 years ago	litex_vexriscv_smp_test/803	VexRiscv-SMP integration test with LiteX.
23	1	0	9 months ago	c128-verilog/804	Verilog code for C128 custom chips
23	15	0	3 years ago	digital_lab/805	Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty
23	6	1	2 years ago	tcam/806	TCAM ( Ternary Content-Addressable Memory) on Verilog
23	9	1	10 months ago	HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine/807	HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
23	5	0	19 days ago	notary/808	Notary: A Device for Secure Transaction Approval 📟
22	2	0	1 year, 11 months ago	SpGEMM/809	None
22	6	4	4 years ago	fLaCPGA/810	Implementation of fLaC encoder/decoder for FPGA
22	2	0	1 year, 6 months ago	TJ-FPGA_MP3/811	同济大学数字逻辑课程期末大作业
22	7	4	2 years ago	32-Bit-Floating-Point-Adder/812	Verilog Implementation of 32-bit Floating Point Adder
22	4	0	10 months ago	cpld-6502/813	6502 CPU in 4 small CPLDs
22	7	0	6 years ago	PCIE_AXI_BRIDGE/814	Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
22	8	0	3 years ago	RePLIA/815	FPGA Based lock in amplifier
22	7	0	10 years ago	mcs-4/816	4004 CPU and MCS-4 family chips
22	4	0	9 months ago	Dadda-Multiplier-using-CSA/817	Dadda multiplier(88, 1616, 32*32) in Verilog HDL.
22	6	1	5 years ago	Verilog-VGA-game/818	A simple game written in Verilog HDL language and display on the VGA screen.
22	9	1	9 years ago	fpgaminer-vanitygen/819	Open Source Bitcoin Vanity Address Generation on FPGAs
22	2	0	a month ago	gameduino-fpga-mods/820	Mods of the FPGA code from @jamesbowman's Gameduino file repository
22	10	0	3 years ago	DigitalAlarmClock/821	njtech digital design. a fpga digital alarm system with Nexys A7 100T
22	6	0	7 years ago	CoCo3FPGA/822	FPGA implementation of the TRS-80 Color Computer 3 in Verilog, by Gary Becker et al.
22	6	1	4 years ago	anlogic-picorv32/823	Optimized picorv32 core for anlogic FPGA
22	21	1	3 years ago	FPGA_CryptoNight_V7/824	FPGA CryptoNight V7 Minner
22	4	0	1 year, 11 months ago	sub-25-ns-nasdaq-itch-fpga-parser/825	None
22	12	1	7 years ago	AHB_Bus_Matrix/826	None
22	7	0	11 months ago	CortexM0_SoC_Task/827	Step by step tutorial for building CortexM0 SoC
22	9	7	7 years ago	pifo-hardware/828	None
22	1	0	3 years ago	BusPirateUltraHDL/829	Verilog for the Bus Pirate Ultra FPGA
22	6	0	1 year, 9 months ago	core_usb_bridge/830	USB -> AXI Debug Bridge
22	20	0	2 years ago	Practical-UVM-IEEE-Edition/831	This is the repository for the IEEE version of the book
22	6	0	5 years ago	Autonomous-Drone-Design/832	Design real-time image processing, object recognition and PID control for Autonomous Drone.
22	17	2	5 years ago	up5k-demos/833	ice40 UltraPlus demos
22	20	12	a month ago	COFFE/834	None
22	15	0	6 years ago	AXI_BFM/835	AXI4 BFM in Verilog
22	12	2	4 years ago	Zeus/836	NVDLA small config implementation on Zynq ZCU104 (evaluation)
22	11	2	1 year, 9 months ago	alice5/837	SPIR-V fragment shader GPU core based on RISC-V
22	6	1	1 year, 4 months ago	SortingNetwork/838	Implement a bitonic sorting network on FPGA
22	14	0	5 years ago	fpga_cmos_design/839	这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西
22	7	0	6 months ago	RiftCore/840	RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
22	7	0	1 year, 8 months ago	Physical-Design-with-OpenLANE-using-SKY130-PDK/841	This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified
22	9	1	1 year, 2 months ago	usb-de2-fpga/842	Hardware interface for USB controller on DE2 FPGA Platform
22	19	1	3 years ago	gemac/843	Gigabit MAC + UDP/TCP/IP offload Engine
22	9	1	2 years ago	DRUM/844	The Verilog source code for DRUM approximate multiplier.
22	5	28	1 year, 2 months ago	rapcores/845	Robotic Application Processor
21	4	0	11 years ago	pdfparser/846	None
21	13	0	2 years ago	verilog-osx/847	Barerbones OSX based Verilog simulation toolchain.
21	3	0	4 years ago	flapga-mario/848	FlaPGA Mario - A flappy-bird like video game implemented in Verilog for Basys3
21	7	1	1 year, 11 months ago	k1801/849	1801 series ULA reverse engineering
21	3	1	7 months ago	Home-Brew-Computer/850	SystemOT, yet another home brew cpu.
21	21	0	4 years ago	2FSK-2PSK-2DPSK-QPSK-code-and-decode/851	用Verilog语言编写，实现2FSK，2PSK, 2DPSK, QPSK调制解调
21	9	1	1 year, 4 months ago	zuma-fpga/852	Fine Grain FPGA Overlay Architecture and Tools
21	13	9	1 year, 1 month ago	Archie_MiSTer/853	Acorn Archimedes for MiSTer
21	3	0	1 year, 2 months ago	libfpga/854	Reusable Verilog 2005 components for FPGA designs
21	4	2	4 years ago	recon/855	The RECON project creates library for Nios II Microcontroller System and Tool chain. The library includes a collection of hardware configurations and Arduino-style software APIs.
21	3	0	1 year, 10 months ago	core_axi_cache/856	128KB AXI cache (32-bit in, 256-bit out)
21	2	0	4 years ago	fpga_1943/857	Verilog re-implementation of the famous CAPCOM arcade game
21	12	0	10 years ago	ovs-hw/858	An open source hardware engine for Open vSwitch on FPGA
21	7	2	8 years ago	Modular-Exponentiation/859	Verilog Implementation of modular exponentiation using Montgomery multiplication
21	12	1	6 months ago	iFlow/860	None
21	11	1	8 years ago	neural-hardware/861	Verilog library for implementing neural networks.
21	3	0	3 years ago	VerilogHDL-Codes/862	Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
21	3	0	1 year, 8 months ago	SmolDVI/863	Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs
21	3	0	1 year, 6 months ago	xiaohaizi_cpu/864	None
21	7	0	4 years ago	OV7670_NEXYS4_Verilog/865	This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog
21	7	1	2 years ago	core_usb_uart/866	USB serial device (CDC-ACM)
21	10	1	19 years ago	jtag/867	JTAG Test Access Port (TAP)
21	7	0	5 months ago	aes/868	Advanced encryption standard implementation in verilog.
21	15	1	4 years ago	FPGA_rtime_HDR_video/869	We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
21	7	0	1 year, 11 months ago	GNN-ARCH/870	[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
21	4	0	1 year, 2 months ago	nano-cpu32k/871	Superscalar out-of-order RISC core (with Cache& MMU) and SoC, supporting GNU toolchain & Linux 4.20 kernel, having been verified on Xilinx Kintex-7 FPGA.
21	3	1	2 years ago	UltiMem64/872	Commodore 64 Internal RAM Expansion with integrated MMU
21	4	0	3 months ago	Fpga-accelerator-demos/873	some interesting demos for starters
21	16	10	2 years ago	UHD-Fairwaves/874	Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.
21	11	0	3 years ago	A-Single-Path-Delay-32-Point-FFT-Processor/875	A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
21	1	0	4 years ago	gameboy-sound-chip/876	None
21	12	0	2 years ago	Reindeer_Step/877	Reindeer Soft CPU for Step CYC10 FPGA board
21	6	45	8 months ago	TART/878	Transient Array Radio Telescope
21	6	0	3 years ago	Digital_Front_End_Verilog/879	None
21	4	0	2 years ago	riscv_sbc/880	A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
21	8	0	3 years ago	up5k_vga/881	A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA
21	6	9	3 months ago	a2o/882	The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
21	3	0	7 years ago	verilog_tutorials_BB/883	verilog tutorials for iCE40HX8K Breakout Board
21	2	0	6 years ago	RiverRaidFPGA/884	River Raid game on FPGA
21	3	1	4 years ago	fpga-virtual-graf/885	None
21	3	0	6 months ago	STEPFPGA-MXO2Core/886	The codes accompanied with STEPFPGA tutorial book
20	11	0	4 years ago	wb_sdram_ctrl/887	SDRAM controller with multiple wishbone slave ports
20	3	0	5 years ago	fpga-sram/888	mystorm sram test
20	6	1	5 years ago	UPDuino-OV7670-Camera/889	Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module
20	2	1	1 year, 5 months ago	risc8/890	Mostly AVR compatible FPGA soft-core
20	3	0	1 year, 4 months ago	FPGA_OV7670_Camera_Interface/891	Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
20	18	0	2 years ago	FPGA_DevKit_HX1006A/892	None
20	2	4	4 months ago	Lighter/893	An automatic clock gating utility
20	5	1	6 years ago	Menu_MIST/894	Dummy FPGA core to display menu at startup
20	1	0	5 years ago	VerilogCommon/895	A repo of basic Verilog/SystemVerilog modules useful in other circuits.
20	5	0	3 years ago	systolic-array-matrix-multiplier/896	A systolic array matrix multiplier
20	4	1	1 year, 8 months ago	ecp5_jtag/897	Use ECP5 JTAG port to interact with user design
20	9	0	1 year, 2 months ago	VSDBabySoC/898	VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
20	5	0	7 years ago	cpus-pdp8/899	FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source
20	28	4	9 months ago	i2c/900	I2C controller core
20	5	0	3 years ago	noop-lo/901	A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
20	14	0	1 year, 8 days ago	Pmod-I2S2/902	None
20	8	6	1 year, 9 months ago	shapool-core/903	FPGA core for SHA256d mining targeting Lattice iCE40 devices.
20	7	0	1 year, 10 months ago	ps-fpga/904	The PS-FPGA project (top level)
20	7	0	1 year, 4 months ago	tf1230/905	Terriblefire TF1230
20	9	0	9 months ago	DSP_with_FPGAs_ed4/906	DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
20	21	0	5 years ago	OFDM_802_11/907	IEEE 802.11 OFDM-based transceiver system
20	4	2	7 years ago	icestickPWM/908	Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo)
20	9	0	2 years ago	2dconv-FPGA/909	A 2D convolution hardware implementation written in Verilog
20	5	0	20 years ago	embedded_risc/910	Embedded 32-bit RISC uProcessor with SDRAM Controller
20	16	0	4 years ago	System-Bus-Design-Verilog/911	This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
20	5	0	15 days ago	tangnano9k-series-examples/912	Examples for the Lushay Labs tang nano 9k series
20	4	6	3 years ago	fluent10g/913	Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
20	6	8	2 months ago	scarv-cpu/914	SCARV: a side-channel hardened RISC-V platform
20	10	1	4 years ago	uvm-basics/915	my UVM training projects
20	10	12	3 months ago	globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/916	7 track standard cells for GF180MCU provided by GlobalFoundries.
20	10	0	1 year, 9 months ago	eFPGA---RTL-to-GDS-with-SKY130/917	This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
20	2	1	7 years ago	icestick-vga-test/918	Test of ICEstick PLL usage with Yosys/Arachne-PNR/Icetools
20	16	0	4 years ago	gameduino/919	My own version of the @JamesBowman's Gameduino file repository
20	13	0	4 years ago	32-bit-MIPS-Processor/920	A 32-bit MIPS processor used Altera Quartus II with Verilog.
20	6	0	3 years ago	HDLBits_Practice_verilog/921	This is a practice of verilog coding
20	7	0	3 years ago	cdsAsync/922	cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
20	11	0	6 years ago	HDC-Language-Recognition/923	Hyperdimensional computing for language recognition: Matlab and RTL implementations
20	11	1	8 years ago	i2s/924	i2s core, with support for both transmit and receive
20	1	0	1 year, 5 months ago	Verilaptor/925	None
20	16	1	5 years ago	PUF-lab/926	FPGA implementation of a physical unclonable function for authentication
20	6	0	2 years ago	bitcoin_mining/927	Simple test fpga bitcoin miner
20	4	2	2 years ago	raiden/928	Raiden project
20	1	0	5 years ago	UART2NAND/929	Interface for exposing raw NAND i/o over UART to enable pc-side modification.
20	9	0	3 years ago	ad7606-driver-verilog/930	AD7606 driver verilog
20	5	0	6 months ago	xilinx-risc-v/931	Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.
19	4	0	10 years ago	verilog-vga-controller/932	A very simple VGA controller written in verilog
19	2	0	1 year, 9 months ago	FPGA_network/933	None
19	10	0	4 years ago	SoC-Design-DDR3-Controller/934	DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
19	15	3	2 years ago	MemTest_MiSTer/935	None
19	15	2	5 years ago	HLS_Legup/936	None
19	2	1	9 months ago	bugu-computer/937	💻 build own computer by fpga.
19	7	0	a month ago	my-verilog-examples/938	A place to keep my synthesizable SystemVerilog code snippets and examples.
19	2	0	1 year, 3 months ago	systolic-array/939	verilog实现TPU中的脉动阵列计算卷积的module
19	9	0	2 months ago	SparrowRV/940	An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
19	5	0	6 years ago	icestick/941	Simple demo for Lattice iCEstick board as seen on Hackaday
19	9	0	7 years ago	i2c/942	I2C Master and Slave
19	17	1	2 months ago	OpenHPSDR-Firmware/943	This is the verilog code for the various FPGA in the OpenHPSDR Radios
19	8	0	9 years ago	OpenProjects/944	None
19	4	0	1 year, 11 months ago	parametric-ntt/945	Parametric NTT/INTT Hardware Generator
19	11	1	1 year, 3 months ago	Radix-2-FFT/946	Verilog code for a circuit implementation of Radix-2 FFT
19	4	0	7 years ago	orgexp/947	Computer Organization Experiment, Shi Qingsong, Zhejiang University.
19	4	0	4 years ago	Flappy-Bird/948	FPGA program :VGA-GAME
19	6	4	3 years ago	yosys-bench/949	Benchmarks for Yosys development
19	10	0	4 years ago	FIFO_-asynchronous/950	异步FIFO的内部实现
19	13	0	1 year, 1 month ago	BLASYS/951	An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
19	1	0	9 months ago	BubbleDrive8/952	Konami Bubble System Bubble Memory Cartridge FBM-#101 Emulator
19	1	0	3 years ago	spi_tb/953	CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys
19	1	0	3 years ago	wbfmtx/954	A wishbone controlled FM transmitter hack
19	8	1	6 years ago	dvi_lvds/955	DVI to LVDS Verilog converter
19	14	15	5 months ago	sancus-core/956	Minimal OpenMSP430 hardware extensions for isolation and attestation
19	8	0	3 years ago	aq_mipi_csi2rx_ultrascaleplus/957	None
19	14	32	4 months ago	caravel_mgmt_soc_litex/958	https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
19	2	0	7 years ago	BCOpenMIPS/959	跟着《自己动手写 CPU》书上写的 OpenMIPS CPU。
19	7	0	1 year, 5 months ago	sta_basics_course/960	Introductory course into static timing analysis (STA).
19	9	0	1 year, 10 days ago	M65C02A/961	Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001)
19	7	0	6 years ago	gng/962	Gaussian noise generator Verilog IP core
19	3	0	6 years ago	OpenMIPS/963	OpenMIPS——《自己动手写CPU》处理器部分
19	13	1	6 years ago	lisnoc/964	LIS Network-on-Chip Implementation
19	6	0	3 years ago	yoloRISC/965	A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
19	17	0	4 years ago	CurriculumDesign-PrinciplesOfComputerOrganization/966	华中科技大学计算机15级计算机组成原理课程设计，分别用logisim和Verilog实现简单CPU
19	7	1	3 years ago	net2axis/967	Verilog network module. Models network traffic from pcap to AXI-Stream
19	4	0	2 years ago	hello-verilog/968	Hello Verilog by Mac + VSCode
19	10	1	5 years ago	FPGA-Mnist/969	Hand written number classification done in hardware (De1-SoC board) using neural networks
19	0	0	7 months ago	dnachips/970	None
19	0	1	6 months ago	arcade-digdug/971	Namco Dig Dug Compatible Gateware IP Core
19	6	0	4 years ago	tinyfpga-bx-game-soc/972	A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games
19	6	0	1 year, 3 months ago	RISC-V-TensorCore/973	Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
18	7	0	9 years ago	80211scrambler/974	Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.
18	14	0	3 years ago	matrix-voice-fpga/975	HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one
18	2	0	3 years ago	Arduissimo/976	Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
18	0	1	2 years ago	TurboMaster/977	Reverse Engineering of the Schnedler Systems 4MHz TurboMaster accelerator cartridge for the Commodore 64
18	12	0	7 years ago	Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM/978	Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
18	0	0	2 years ago	lemoncore/979	Simple RISC-V processor for FPGAs 🍋 🤖
18	4	0	4 years ago	HUST-Verilog-Labs/980	HUST Verilog Labs 2018 and Digital logic labs 2018
18	4	1	5 years ago	handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/981	None
18	3	0	8 years ago	parallel-processor-design/982	Super scalar Processor design
18	6	0	3 years ago	Jaguar_MiSTer_new/983	None
18	1	0	1 year, 11 months ago	biggateboy/984	WIP Big FPGA Gameboy
18	7	0	2 years ago	h264_decoder/985	None
18	9	1	9 months ago	getting-started-with-verilog/986	Verilog modules for beginners
18	8	7	6 years ago	spi/987	spi memory controller
18	9	0	4 years ago	FPGA_SYNC_ASYNC_FIFO/988	FPGA 同步FIFO与异步FIFO
18	8	0	7 years ago	Multiported-RAM/989	Modular Multi-ported SRAM-based Memory
18	4	9	10 years ago	hdl_devel/990	A new CASPER toolflow based on an HDL primitives library
18	4	1	4 years ago	fpga-uart-tx-rx/991	Basic UART TX/RX module for FPGA
18	6	0	3 years ago	pipeline-mips-verilog/992	A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
18	3	1	3 months ago	riscv_cpu/993	a simple riscv cpu
18	3	0	7 years ago	FPGA/994	computer hardware system including ps2/vga with tank war game in verilog and mips
18	9	6	6 years ago	polaris/995	RISC-V RV64IS-compatible processor for the Kestrel-3
18	6	0	1 year, 10 months ago	ethernet-fmc-processorless/996	Example designs for using Ethernet FMC without a processor (ie. state machine based)
18	2	0	2 years ago	ice40_power/997	Power analysis of the ICE40UP5K-SG48 devices
18	4	1	7 years ago	i2c-eeprom/998	Controller for i2c EEPROM chip in Verilog for Mojo FPGA board
18	5	1	5 years ago	fpga-wpa-psk-bruteforcer/999	WPA-PSK cracking for FPGA devices
18	0	0	3 years ago	risc-v/1000	RISC-VのCPU作った