diff --git a/src/flash/nand/davinci.c b/src/flash/nand/davinci.c
index 84f8e3480..946f9cfea 100644
--- a/src/flash/nand/davinci.c
+++ b/src/flash/nand/davinci.c
@@ -606,6 +606,7 @@ static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
davinci_write_block_data(nand, oob, 16);
oob += 16;
oob_size -= 16;
+ (void) oob_size;
} while (data_size);
diff --git a/src/flash/nor/dsp5680xx_flash.c b/src/flash/nor/dsp5680xx_flash.c
index 5e8eec30f..858b66981 100644
--- a/src/flash/nor/dsp5680xx_flash.c
+++ b/src/flash/nor/dsp5680xx_flash.c
@@ -45,14 +45,11 @@
static int dsp5680xx_build_sector_list(struct flash_bank *bank)
{
- uint32_t offset = HFM_FLASH_BASE_ADDR;
-
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
for (unsigned int i = 0; i < bank->num_sectors; ++i) {
bank->sectors[i].offset = i * HFM_SECTOR_SIZE;
bank->sectors[i].size = HFM_SECTOR_SIZE;
- offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = -1;
}
diff --git a/src/flash/nor/wcharm.c b/src/flash/nor/wcharm.c
index 72c3bb327..25a2c1956 100644
--- a/src/flash/nor/wcharm.c
+++ b/src/flash/nor/wcharm.c
@@ -13,7 +13,7 @@
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see . *
***************************************************************************/
-
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -74,12 +74,12 @@
#define FLASH_OBL_LAUNCH (1 << 13) /* except ch32f1x series */
-#define FLASH_PAGE_PROGRAM 0x00010000
-#define FLASH_PAGE_ERASE 0x00020000
-#define FLASH_STD_PAGE_ERASE 0x00000002
-#define FLASH_STD_PAGE_PRG 0x00000001
-#define FLASH_BUF_LOAD 0x00040000
-#define FLASH_BUF_RTS 0x00080000
+#define FLASH_PAGE_PROGRAM 0x00010000
+#define FLASH_PAGE_ERASE 0x00020000
+#define FLASH_STD_PAGE_ERASE 0x00000002
+#define FLASH_STD_PAGE_PRG 0x00000001
+#define FLASH_BUF_LOAD 0x00040000
+#define FLASH_BUF_RTS 0x00080000
@@ -141,8 +141,8 @@ static int ch32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
static int ch32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t address, uint32_t count);
extern int wlink_armcheckprotect(void);
-extern void wlink_sendchip(config);
-
+extern void wlink_sendchip(uint8_t config);
+
/* flash bank ch32x 0 0
@@ -222,8 +222,8 @@ static int ch32x_wait_status_busy(struct flash_bank *bank, int timeout)
static int ch32x_check_operation_supported(struct flash_bank *bank)
{
-
-
+
+
struct ch32x_flash_bank *ch32x_info = bank->driver_priv;
/* if we have a dual flash bank device then
@@ -238,8 +238,8 @@ static int ch32x_check_operation_supported(struct flash_bank *bank)
static int ch32x_read_options(struct flash_bank *bank)
{
-
-
+
+
struct ch32x_flash_bank *ch32x_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t option_bytes;
@@ -278,8 +278,8 @@ static int ch32x_read_options(struct flash_bank *bank)
static int ch32x_erase_options(struct flash_bank *bank)
{
-
-
+
+
struct ch32x_flash_bank *ch32x_info = bank->driver_priv;
struct target *target = bank->target;
@@ -324,8 +324,8 @@ static int ch32x_erase_options(struct flash_bank *bank)
static int ch32x_write_options(struct flash_bank *bank)
{
-
-
+
+
struct ch32x_flash_bank *ch32x_info = NULL;
struct target *target = bank->target;
@@ -379,7 +379,7 @@ static int ch32x_write_options(struct flash_bank *bank)
static int ch32x_protect_check(struct flash_bank *bank)
{
-
+
struct target *target = bank->target;
uint32_t protection;
@@ -395,29 +395,30 @@ static int ch32x_protect_check(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- for (int i = 0; i < bank->num_prot_blocks; i++)
+ for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
return ERROR_OK;
}
-static int ch32x_erase(struct flash_bank *bank, int first, int last)
-{
- if(armchip)
- {
- if(noloadflag)
- return ERROR_OK;
-
- int ret=wlink_armerase();
-
+static int ch32x_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
+{
+ // TODO: This function doesn't erase anything on !arm. That's probably bad.
+ if (armchip) {
+ if (noloadflag) {
+ return ERROR_OK;
+ }
+
+ int ret = wlink_armerase();
return ret;
-
- }
+
+ }
+ return ERROR_OK;
}
-static int ch32x_protect(struct flash_bank *bank, int set, int first, int last)
+static int ch32x_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
{
-
+
struct target *target = bank->target;
struct ch32x_flash_bank *ch32x_info = bank->driver_priv;
@@ -436,7 +437,7 @@ static int ch32x_protect(struct flash_bank *bank, int set, int first, int last)
return retval;
}
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
if (set)
ch32x_info->option_bytes.protection &= ~(1 << i);
else
@@ -455,13 +456,16 @@ static int ch32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
static int ch32x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
- if(armchip)
- {
- if(noloadflag)
- return ERROR_OK;
- int ret=wlink_armwrite(buffer,bank->base + offset,count);
- return ret;
- }
+ // TODO: This doesn't write anything for !arm. Is that intended?
+ if (armchip) {
+ if (noloadflag) {
+ return ERROR_OK;
+ }
+ int ret=wlink_armwrite(buffer,bank->base + offset,count);
+ return ret;
+ }
+
+ return ERROR_OK;
}
@@ -469,15 +473,14 @@ static int ch32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
{
/* This check the device CPUID core register to detect
* the M0 from the M3 devices. */
-
+
struct target *target = bank->target;
- uint32_t cpuid, device_id_register = 0;
uint32_t testid=0;
uint32_t tmp,tmp1,tmp2=0;
uint8_t user_cfg,config;
target_read_u8(target, 0x1ffff802, &user_cfg);
config=user_cfg>>6;
- target_read_u32(target, 0x1ffff884, &testid);
+ target_read_u32(target, 0x1ffff884, &testid);
if(((testid>>16)==0x2000)||((testid>>16)==0x1000)||((testid>>16)==0x3000)){
target_read_u32(target, 0x1ffff7e8, &tmp);
target_read_u32(target, 0x1ffff8a0, &tmp1);
@@ -489,15 +492,15 @@ static int ch32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
wlink_sendchip(config);
return ERROR_OK;
}
-
+
}
target_read_u32(target, 0xe000edfc, &testid);
-
+
target_read_u32(target, 0xe000edf0, &testid);
-
+
target_read_u32(target, 0x1ffff704, &testid);
-
- if(((testid>>20)==0x203)||((testid>>20)==0x205)||((testid>>20)==0x207)||((testid>>20)==0x208)){
+
+ if(((testid>>20)==0x203)||((testid>>20)==0x205)||((testid>>20)==0x207)||((testid>>20)==0x208)){
armchip=2;
*device_id=0x20000410;
wlink_sendchip(config);
@@ -508,11 +511,15 @@ static int ch32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
}
static int ch32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
-{
+{
struct target *target = bank->target;
- uint32_t cpuid, flash_size_reg;
- uint32_t temp;
- int retval = target_read_u32(target, 0x1ffff7e0, flash_size_in_kb);
+ // FIXME: this is almost certainly an actual bug and I'm applying pain killer
+ // to it.
+ // target_read_u32 reads 32 bits and stores it in the pointee of the final arg.
+ // The final argument here is a uint16_t as it is in the caller. I'm going to
+ // change this to read 16 bits, but this could cause synchronization issues.
+ // Orig: int retval = target_read_u32(target, 0x1ffff7e0, flash_size_in_kb);
+ int retval = target_read_u16(target, 0x1ffff7e0, flash_size_in_kb);
if (retval != ERROR_OK)
return retval;
@@ -520,28 +527,26 @@ static int ch32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in
}
static int ch32x_probe(struct flash_bank *bank)
-{
+{
struct ch32x_flash_bank *ch32x_info = bank->driver_priv;
uint16_t flash_size_in_kb;
uint16_t max_flash_size_in_kb;
uint32_t device_id;
int page_size;
uint32_t base_address = 0x08000000;
- uint32_t rid=0;
ch32x_info->probed = 0;
ch32x_info->register_base = FLASH_REG_BASE_B0;
ch32x_info->user_data_offset = 10;
ch32x_info->option_offset = 0;
/* default factory read protection level 0 */
- ch32x_info->default_rdp = 0xA5;
-
+ ch32x_info->default_rdp = 0xA5;
+
int retval = ch32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
return retval;
-
+
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
- rid=device_id & 0xfff ;
/* set page size, protection granularity and max flash size depending on family */
switch (device_id & 0xfff) {
case 0x410: /* medium density */
@@ -549,7 +554,7 @@ static int ch32x_probe(struct flash_bank *bank)
ch32x_info->ppage_size = 4;
max_flash_size_in_kb = 512;
break;
-
+
default:
LOG_WARNING("Cannot identify target as a ch32 family.");
return ERROR_FAIL;
@@ -632,7 +637,7 @@ static int ch32x_probe(struct flash_bank *bank)
static int ch32x_auto_probe(struct flash_bank *bank)
{
-
+
struct ch32x_flash_bank *ch32x_info = bank->driver_priv;
if (ch32x_info->probed)
return ERROR_OK;
@@ -646,7 +651,7 @@ COMMAND_HANDLER(ch32x_handle_part_id_command)
}
#endif
-static int get_ch32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_ch32x_info(struct flash_bank *bank, struct command_invocation *buf_size)
{
@@ -945,7 +950,7 @@ COMMAND_HANDLER(ch32x_handle_options_load_command)
static int ch32x_mass_erase(struct flash_bank *bank)
{
-
+
struct target *target = bank->target;
if (target->state != TARGET_HALTED) {
@@ -983,8 +988,6 @@ static int ch32x_mass_erase(struct flash_bank *bank)
COMMAND_HANDLER(ch32x_handle_mass_erase_command)
{
- int i;
-
if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -996,7 +999,7 @@ COMMAND_HANDLER(ch32x_handle_mass_erase_command)
retval = ch32x_mass_erase(bank);
if (retval == ERROR_OK) {
/* set all sectors as erased */
- for (i = 0; i < bank->num_sectors; i++)
+ for (unsigned i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_erased = 1;
command_print(CMD, "ch32x mass erase complete");
diff --git a/src/flash/nor/wchriscv.c b/src/flash/nor/wchriscv.c
index d5f7a16a5..4d68e3aa5 100644
--- a/src/flash/nor/wchriscv.c
+++ b/src/flash/nor/wchriscv.c
@@ -23,7 +23,7 @@
#include
extern int wlink_erase(void);
extern unsigned char riscvchip;
-extern int wlink_reset();
+extern int wlink_reset(void);
extern void wlink_getromram(uint32_t *rom,uint32_t *ram);
extern int wlink_write(const uint8_t *buffer, uint32_t offset, uint32_t count);
extern int noloadflag;
@@ -68,11 +68,12 @@ FLASH_BANK_COMMAND_HANDLER(ch32vx_flash_bank_command)
return ERROR_OK;
}
-static int ch32vx_erase(struct flash_bank *bank, int first, int last)
-{
-
- if(noloadflag)
+static int ch32vx_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
+{
+
+ if (noloadflag){
return ERROR_OK;
+ }
wlink_reset();
int ret = wlink_erase();
target_halt(bank->target);
@@ -85,13 +86,13 @@ static int ch32vx_erase(struct flash_bank *bank, int first, int last)
static int ch32vx_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
-
+
if(noloadflag)
return ERROR_OK;
-
+
int ret = wlink_write(buffer, offset, count);
if((riscvchip==0x02)||(riscvchip==0x03))
- wlink_reset();
+ wlink_reset();
return ret;
}
@@ -128,7 +129,6 @@ static int ch32vx_probe(struct flash_bank *bank)
uint32_t ram=0;
int page_size;
uint32_t base_address = 0x00000000;
- uint32_t rid = 0;
ch32vx_info->probed = 0;
/* read ch32 device id register */
int retval = ch32vx_get_device_id(bank, &device_id);
@@ -140,12 +140,12 @@ static int ch32vx_probe(struct flash_bank *bank)
ch32vx_info->ppage_size = 4;
/* get flash size from target. */
retval = ch32vx_get_flash_size(bank, &flash_size_in_kb);
- if(flash_size_in_kb)
+ if (flash_size_in_kb)
LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
else
flash_size_in_kb=delfault_max_flash_size;
if((riscvchip==0x05)||(riscvchip==0x06)||(riscvchip==0x03))
- {
+ {
wlink_getromram(&rom,&ram);
if((rom != 0)&&(ram !=0))
LOG_INFO("ROM %d kbytes RAM %d kbytes" ,rom,ram);
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index bc77bc12c..f5124f9c4 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -313,7 +313,7 @@ static int cmsis_dap_open(void)
cmsis_dap_handle = dap;
wlink_armversion(dap);
-
+
return ERROR_OK;
}
diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c
index cf262a401..92ac8d1e2 100644
--- a/src/jtag/drivers/cmsis_dap_usb_bulk.c
+++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c
@@ -31,7 +31,7 @@
* along with this program. If not, see . *
***************************************************************************/
-#ifdef HAVE_CONFIG_H
+#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -105,7 +105,7 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
struct libusb_device_handle *dev_handle = NULL;
err = libusb_open(dev, &dev_handle);
-
+
if (err) {
/* It's to be expected that most USB devices can't be opened
* so only report an error if it was explicitly selected
@@ -119,7 +119,7 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
}
continue;
}
-
+
/* Match serial number */
bool serial_match = false;
@@ -329,7 +329,7 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
LOG_INFO("Using CMSIS-DAPv2 interface with VID:PID=0x%04x:0x%04x, serial=%s",
dev_desc.idVendor, dev_desc.idProduct, dev_serial);
-
+
int current_config;
err = libusb_get_configuration(dev_handle, ¤t_config);
if (err) {
@@ -369,7 +369,7 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
dap->bdata->ep_out = ep_out;
dap->bdata->ep_in = ep_in;
dap->bdata->interface = interface_num;
-
+
dap->packet_buffer = malloc(dap->packet_buffer_size);
if (!dap->packet_buffer) {
LOG_ERROR("unable to allocate memory");
@@ -478,7 +478,7 @@ static const uint32_t flash_code1[] = {
0x46086108, 0xF0406900, 0x61080040, 0xF64AE003, 0x496420AA, 0x48606008, 0xF00068C0, 0x28000001,
0x485DD1F5, 0xF0206900, 0x495B0004, 0x20006108, 0xB5084770, 0x20004601, 0x48579000, 0xF0406900,
0x4A550002, 0x20016110, 0xBF009000, 0x61414852, 0xF0406900, 0x4A500040, 0xE0036110, 0x20AAF64A,
- 0x60104A50, 0x68C0484C, 0x0001F000, 0xD1F52800, 0x0000F89D, 0xB2C01E40, 0x28009000, 0x4846D1E6,
+ 0x60104A50, 0x68C0484C, 0x0001F000, 0xD1F52800, 0x0000F89D, 0xB2C01E40, 0x28009000, 0x4846D1E6,
0xF0206900, 0x4A440002, 0x20006110, 0xB5F0BD08, 0x460D4604, 0x46232608, 0x60086828, 0x40024842,
0x2200F442, 0x6102483C, 0x483BBF00, 0xF00068C0, 0x28000001, 0xF422D1F9, 0xBF002200, 0x6018C901,
0x6058C901, 0x6098C901, 0x60D8C901, 0x2280F442, 0x61024831, 0xBF003310, 0x68C0482F, 0x0001F000,
@@ -486,9 +486,9 @@ static const uint32_t flash_code1[] = {
0x0240F022, 0x4824BF00, 0xF00068C0, 0x28000001, 0x4821D1F9, 0xF00068C0, 0xB1600014, 0x68C0481E,
0x0014F040, 0x60F84F1C, 0x20FFF240, 0x46384002, 0x20016102, 0x2000BDF0, 0xE92DE7FC, 0x460641F8,
0x4615460F, 0x0800F04F, 0xF1079600, 0xF3C0007F, 0x481118C7, 0xF4446904, 0x61043480, 0x4622BF00,
- 0x98004629, 0xFF93F7FF, 0x2001B110, 0x81F8E8BD, 0x30809800, 0x35809000, 0x0001F1A8, 0xF1B0B2C0,
+ 0x98004629, 0xFF93F7FF, 0x2001B110, 0x81F8E8BD, 0x30809800, 0x35809000, 0x0001F1A8, 0xF1B0B2C0,
0xD1EC0800, 0x20FFF240, 0x48034004, 0x20006104, 0x0000E7EC, 0x00000004, 0x40022000, 0x45670123,
- 0xCDEF89AB, 0x40003000, 0x000102FF, 0x00000000, 0x00000000,
+ 0xCDEF89AB, 0x40003000, 0x000102FF, 0x00000000, 0x00000000,
};
uint32_t program_code1[] = {
@@ -556,8 +556,8 @@ void wlink_sendchip(uint8_t config)
buffer_code[1]=0x11;
buffer_code[2]=0x01;
libusb_bulk_transfer(wlink_dev_handle, 0x02,buffer_code,4,&transferred,timeout);
- libusb_bulk_transfer(wlink_dev_handle, 0x83,buffer_rcode,sizeof(buffer_rcode),&transferred,timeout);
- chip_type=((unsigned int)buffer_rcode[19]) + (((unsigned int)buffer_rcode[18])<<8) + (((unsigned int)buffer_rcode[17])<<16) +(((unsigned int) buffer_rcode[16])<<24);
+ libusb_bulk_transfer(wlink_dev_handle, 0x83,buffer_rcode,sizeof(buffer_rcode),&transferred,timeout);
+ chip_type=((unsigned int)buffer_rcode[19]) + (((unsigned int)buffer_rcode[18])<<8) + (((unsigned int)buffer_rcode[17])<<16) +(((unsigned int) buffer_rcode[16])<<24);
bool type_A=false;
bool type_B=false;
if(chip_type==0x20700418 ||chip_type==0x20300414 ||chip_type==0x20310414 )
@@ -625,10 +625,10 @@ void wlink_sendchip(uint8_t config)
if((rom!=0) && (ram!=0))
LOG_INFO("ROM %d kbytes RAM %d kbytes" ,rom,ram);
-
+
}
void wlink_armversion(struct cmsis_dap *dap){
-
+
int transferred = 0;
unsigned char txbuf[4]={0x81,0x0d,0x1,0x1};
unsigned char rxbuf[20];
@@ -653,7 +653,7 @@ void wlink_armversion(struct cmsis_dap *dap){
wlink_name="WCH-LinkB mod:ARM";
break;
default:
- LOG_ERROR("unknow WCH-LINK ");
+ LOG_ERROR("unknow WCH-LINK ");
break;
}
LOG_INFO("%s version %d.%d ",wlink_name, rxbuf[3], rxbuf[4]);
@@ -668,7 +668,7 @@ int wlink_armcheckprotect(void)
if (armchip == 1)
buffer_clk[3] = 0x04;
if (armchip == 2)
- buffer_clk[3] = 0x08;
+ buffer_clk[3] = 0x08;
libusb_bulk_transfer(wlink_dev_handle, 0x02,buffer_clk,sizeof(buffer_code),&transferred,timeout);
libusb_bulk_transfer(wlink_dev_handle, 0x83,buffer_rcode,sizeof(buffer_rcode),&transferred,timeout);
// hid_write(wlink_dev_handle, buffer_clk, 65);
@@ -686,6 +686,7 @@ int wlink_armcheckprotect(void)
}
return ERROR_OK;
}
+ return 0;
}
int wlink_armerase(void)
{
@@ -693,7 +694,7 @@ int wlink_armerase(void)
int transferred=0;
uint8_t buffer_rcode[4];
uint32_t *comprogram = NULL;
- uint32_t *comflash = NULL;
+ const uint32_t *comflash = NULL;
if (armchip == 1)
{
comprogram = program_code1;
@@ -705,8 +706,6 @@ int wlink_armerase(void)
comprogram = program_code2;
comflash = flash_code2;
}
- uint8_t i = 0;
- uint8_t *flashcode = (uint8_t *)comflash;
int h = *(comprogram + 10);
@@ -748,7 +747,7 @@ int wlink_armerase(void)
int wlink_armwrite(const uint8_t *buffer, uint32_t offset, uint32_t count)
{
int transferred = 0;
- uint8_t *addr = &offset;
+ uint8_t *addr = (uint8_t *) &offset;
uint8_t flash_write[] = {0x81, 0x02, 0x01, 0x02};
uint8_t buffer_rcode[4];
uint8_t i = 0;
@@ -765,11 +764,11 @@ int wlink_armwrite(const uint8_t *buffer, uint32_t offset, uint32_t count)
}
uint8_t address[] = { 0x81, 0x01, 0x08, *(addr + 3), *(addr + 2), *(addr + 1), *addr,(count >> 24) & 0xff, (count >> 16) & 0xff, (count >> 8) & 0xff, count & 0xff};
- // hid_write(wlink_dev_handle, address, 65);
+ // hid_write(wlink_dev_handle, address, 65);
// hid_read_timeout(wlink_dev_handle, buffer_rcode, 65, beytime);
// hid_write(wlink_dev_handle, countsize, 65);
- // hid_read_timeout(wlink_dev_handle, buffer_rcode, 65, beytime);
- // hid_write(wlink_dev_handle, flash_write, 65);
+ // hid_read_timeout(wlink_dev_handle, buffer_rcode, 65, beytime);
+ // hid_write(wlink_dev_handle, flash_write, 65);
// int retval = hid_read_timeout(wlink_dev_handle, buffer_rcode, 65, beytime);
libusb_bulk_transfer(wlink_dev_handle, 0x02,address,sizeof(address),&transferred,timeout);
libusb_bulk_transfer(wlink_dev_handle, 0x83,buffer_rcode,sizeof(buffer_rcode),&transferred,timeout);
@@ -813,6 +812,7 @@ void wlink_armquitreset(struct cmsis_dap *dap)
// hid_read(wlink_dev_handle, buffer_rcode, 65);
libusb_bulk_transfer(dap->bdata->dev_handle, 0x02,resetbuffer,sizeof(resetbuffer),&transferred,timeout);
int ret=libusb_bulk_transfer(dap->bdata->dev_handle, 0x83,buffer_rcode,sizeof(buffer_rcode),&transferred,timeout);
+ (void) ret;
}
diff --git a/src/jtag/drivers/wlink.c b/src/jtag/drivers/wlink.c
index 92a456d14..61222aae6 100644
--- a/src/jtag/drivers/wlink.c
+++ b/src/jtag/drivers/wlink.c
@@ -14,7 +14,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*/
-
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -67,15 +67,15 @@ pCH375WriteEndP pWriteData;
#include
#include
#include
-int gIndex = 0;
+uint32_t gIndex = 0;
static const uint16_t wlink_vids[] = {0x1a86, 0};
static const uint16_t wlink_pids[] = {0x8010, 0};
-struct jtag_libusb_device_handle *wfd = NULL;
+//struct jtag_libusb_device_handle *wfd = NULL;
+struct libusb_device_handle *wfd = NULL;
int pWriteData(int dev, int endpoint, unsigned char *buf, unsigned long *length)
{
int ret,pr;
- length = (int *)length;
- ret =jtag_libusb_bulk_write(wfd, endpoint, buf, *length, 3000,&pr);
+ ret =jtag_libusb_bulk_write(wfd, endpoint, (char*) buf, *length, 3000,&pr);
if(ret==ERROR_OK)
return 1;
else
@@ -84,16 +84,15 @@ int pWriteData(int dev, int endpoint, unsigned char *buf, unsigned long *length)
int pReadData(int dev, int endpoint, unsigned char *buf, unsigned long *length)
{
int ret,pr;
- length = (int *)length;
if (endpoint == 1)
{
- ret=jtag_libusb_bulk_read(wfd, 0x81, buf, *length, 3000,&pr);
+ ret = jtag_libusb_bulk_read(wfd, 0x81, (char*) buf, *length, 3000,&pr);
}
else
{
- ret=jtag_libusb_bulk_read(wfd, 0x82, buf, *length, 3000,&pr);
+ ret = jtag_libusb_bulk_read(wfd, 0x82, (char*) buf, *length, 3000,&pr);
}
- if(ret==ERROR_OK)
+ if (ret == ERROR_OK)
return 1;
else
return ret;
@@ -109,37 +108,37 @@ unsigned long chipiaddr;
unsigned long pagesize;
unsigned long ramaddr;
bool wchwlink;
-int noloadflag=0;
+int noloadflag=0;
uint8_t flash_op103[ ] ={
- 0x93, 0x77, 0x15, 0x00, 0x41, 0x11, 0x99, 0xCF, 0xB7, 0x06, 0x67, 0x45, 0xB7, 0x27, 0x02, 0x40,
- 0x93, 0x86, 0x36, 0x12, 0x37, 0x97, 0xEF, 0xCD, 0xD4, 0xC3, 0x13, 0x07, 0xB7, 0x9A, 0xD8, 0xC3,
- 0xD4, 0xD3, 0xD8, 0xD3, 0x93, 0x77, 0x25, 0x00, 0x9D, 0xC7, 0xB7, 0x27, 0x02, 0x40, 0x98, 0x4B,
- 0xAD, 0x66, 0x37, 0x38, 0x00, 0x40, 0x13, 0x67, 0x47, 0x00, 0x98, 0xCB, 0x98, 0x4B, 0x93, 0x86,
- 0xA6, 0xAA, 0x13, 0x67, 0x07, 0x04, 0x98, 0xCB, 0xD8, 0x47, 0x05, 0x8B, 0x63, 0x1F, 0x07, 0x10,
- 0x98, 0x4B, 0x6D, 0x9B, 0x98, 0xCB, 0x93, 0x77, 0x45, 0x00, 0xA9, 0xCB, 0x93, 0x07, 0xF6, 0x07,
- 0x9D, 0x83, 0x2E, 0xC0, 0x2D, 0x68, 0x81, 0x76, 0x3E, 0xC4, 0xB7, 0x08, 0x02, 0x00, 0xB7, 0x27,
- 0x02, 0x40, 0x37, 0x33, 0x00, 0x40, 0x13, 0x08, 0xA8, 0xAA, 0xFD, 0x16, 0x98, 0x4B, 0x33, 0x67,
- 0x17, 0x01, 0x98, 0xCB, 0x02, 0x47, 0xD8, 0xCB, 0x98, 0x4B, 0x13, 0x67, 0x07, 0x04, 0x98, 0xCB,
- 0xD8, 0x47, 0x05, 0x8B, 0x71, 0xEF, 0x98, 0x4B, 0x75, 0x8F, 0x98, 0xCB, 0x02, 0x47, 0x13, 0x07,
- 0x07, 0x08, 0x3A, 0xC0, 0x22, 0x47, 0x7D, 0x17, 0x3A, 0xC4, 0x69, 0xFB, 0x93, 0x77, 0x85, 0x00,
- 0xED, 0xC3, 0x93, 0x07, 0xF6, 0x07, 0x2E, 0xC0, 0x9D, 0x83, 0x37, 0x27, 0x02, 0x40, 0x3E, 0xC4,
- 0x1C, 0x4B, 0xC1, 0x66, 0x37, 0x08, 0x08, 0x00, 0xD5, 0x8F, 0x1C, 0xCB, 0xA1, 0x48, 0x37, 0x17,
- 0x00, 0x20, 0xB7, 0x27, 0x02, 0x40, 0x37, 0x03, 0x04, 0x00, 0x94, 0x4B, 0xB3, 0xE6, 0x06, 0x01,
- 0x94, 0xCB, 0xD4, 0x47, 0x85, 0x8A, 0xF5, 0xFE, 0x82, 0x46, 0x3A, 0x8E, 0x36, 0xC2, 0x46, 0xC6,
- 0x92, 0x46, 0x83, 0x2E, 0x07, 0x00, 0x41, 0x07, 0x23, 0xA0, 0xD6, 0x01, 0x92, 0x46, 0x83, 0x2E,
- 0x47, 0xFF, 0x23, 0xA2, 0xD6, 0x01, 0x92, 0x46, 0x83, 0x2E, 0x87, 0xFF, 0x23, 0xA4, 0xD6, 0x01,
- 0x92, 0x46, 0x03, 0x2E, 0xCE, 0x00, 0x23, 0xA6, 0xC6, 0x01, 0x94, 0x4B, 0xB3, 0xE6, 0x66, 0x00,
- 0x94, 0xCB, 0xD4, 0x47, 0x85, 0x8A, 0xF5, 0xFE, 0x92, 0x46, 0x3A, 0x8E, 0xC1, 0x06, 0x36, 0xC2,
- 0xB2, 0x46, 0xFD, 0x16, 0x36, 0xC6, 0xCD, 0xFE, 0x82, 0x46, 0xD4, 0xCB, 0x94, 0x4B, 0x93, 0xE6,
- 0x06, 0x04, 0x94, 0xCB, 0xD4, 0x47, 0x85, 0x8A, 0xF5, 0xFE, 0xD4, 0x47, 0xD1, 0x8A, 0x85, 0xC6,
- 0xD8, 0x47, 0xB7, 0x06, 0xF3, 0xFF, 0xFD, 0x16, 0x13, 0x67, 0x47, 0x01, 0xD8, 0xC7, 0x98, 0x4B,
- 0x21, 0x45, 0x75, 0x8F, 0x98, 0xCB, 0x41, 0x01, 0x02, 0x90, 0x23, 0x20, 0xD8, 0x00, 0xE9, 0xBD,
- 0x23, 0x20, 0x03, 0x01, 0x31, 0xBF, 0x82, 0x46, 0x93, 0x86, 0x06, 0x08, 0x36, 0xC0, 0xA2, 0x46,
- 0xFD, 0x16, 0x36, 0xC4, 0xB9, 0xFA, 0x98, 0x4B, 0xB7, 0x06, 0xF3, 0xFF, 0xFD, 0x16, 0x75, 0x8F,
- 0x98, 0xCB, 0x41, 0x89, 0x15, 0xC9, 0x2E, 0xC0, 0x0D, 0x06, 0x02, 0xC4, 0x09, 0x82, 0x32, 0xC6,
- 0xB7, 0x17, 0x00, 0x20, 0x98, 0x43, 0x13, 0x86, 0x47, 0x00, 0xA2, 0x47, 0x82, 0x46, 0x8A, 0x07,
- 0xB6, 0x97, 0x9C, 0x43, 0x63, 0x1C, 0xF7, 0x00, 0xA2, 0x47, 0x85, 0x07, 0x3E, 0xC4, 0xA2, 0x46,
- 0x32, 0x47, 0xB2, 0x87, 0xE3, 0xE0, 0xE6, 0xFE, 0x01, 0x45, 0x71, 0xBF, 0x41, 0x45, 0x61, 0xBF,
+ 0x93, 0x77, 0x15, 0x00, 0x41, 0x11, 0x99, 0xCF, 0xB7, 0x06, 0x67, 0x45, 0xB7, 0x27, 0x02, 0x40,
+ 0x93, 0x86, 0x36, 0x12, 0x37, 0x97, 0xEF, 0xCD, 0xD4, 0xC3, 0x13, 0x07, 0xB7, 0x9A, 0xD8, 0xC3,
+ 0xD4, 0xD3, 0xD8, 0xD3, 0x93, 0x77, 0x25, 0x00, 0x9D, 0xC7, 0xB7, 0x27, 0x02, 0x40, 0x98, 0x4B,
+ 0xAD, 0x66, 0x37, 0x38, 0x00, 0x40, 0x13, 0x67, 0x47, 0x00, 0x98, 0xCB, 0x98, 0x4B, 0x93, 0x86,
+ 0xA6, 0xAA, 0x13, 0x67, 0x07, 0x04, 0x98, 0xCB, 0xD8, 0x47, 0x05, 0x8B, 0x63, 0x1F, 0x07, 0x10,
+ 0x98, 0x4B, 0x6D, 0x9B, 0x98, 0xCB, 0x93, 0x77, 0x45, 0x00, 0xA9, 0xCB, 0x93, 0x07, 0xF6, 0x07,
+ 0x9D, 0x83, 0x2E, 0xC0, 0x2D, 0x68, 0x81, 0x76, 0x3E, 0xC4, 0xB7, 0x08, 0x02, 0x00, 0xB7, 0x27,
+ 0x02, 0x40, 0x37, 0x33, 0x00, 0x40, 0x13, 0x08, 0xA8, 0xAA, 0xFD, 0x16, 0x98, 0x4B, 0x33, 0x67,
+ 0x17, 0x01, 0x98, 0xCB, 0x02, 0x47, 0xD8, 0xCB, 0x98, 0x4B, 0x13, 0x67, 0x07, 0x04, 0x98, 0xCB,
+ 0xD8, 0x47, 0x05, 0x8B, 0x71, 0xEF, 0x98, 0x4B, 0x75, 0x8F, 0x98, 0xCB, 0x02, 0x47, 0x13, 0x07,
+ 0x07, 0x08, 0x3A, 0xC0, 0x22, 0x47, 0x7D, 0x17, 0x3A, 0xC4, 0x69, 0xFB, 0x93, 0x77, 0x85, 0x00,
+ 0xED, 0xC3, 0x93, 0x07, 0xF6, 0x07, 0x2E, 0xC0, 0x9D, 0x83, 0x37, 0x27, 0x02, 0x40, 0x3E, 0xC4,
+ 0x1C, 0x4B, 0xC1, 0x66, 0x37, 0x08, 0x08, 0x00, 0xD5, 0x8F, 0x1C, 0xCB, 0xA1, 0x48, 0x37, 0x17,
+ 0x00, 0x20, 0xB7, 0x27, 0x02, 0x40, 0x37, 0x03, 0x04, 0x00, 0x94, 0x4B, 0xB3, 0xE6, 0x06, 0x01,
+ 0x94, 0xCB, 0xD4, 0x47, 0x85, 0x8A, 0xF5, 0xFE, 0x82, 0x46, 0x3A, 0x8E, 0x36, 0xC2, 0x46, 0xC6,
+ 0x92, 0x46, 0x83, 0x2E, 0x07, 0x00, 0x41, 0x07, 0x23, 0xA0, 0xD6, 0x01, 0x92, 0x46, 0x83, 0x2E,
+ 0x47, 0xFF, 0x23, 0xA2, 0xD6, 0x01, 0x92, 0x46, 0x83, 0x2E, 0x87, 0xFF, 0x23, 0xA4, 0xD6, 0x01,
+ 0x92, 0x46, 0x03, 0x2E, 0xCE, 0x00, 0x23, 0xA6, 0xC6, 0x01, 0x94, 0x4B, 0xB3, 0xE6, 0x66, 0x00,
+ 0x94, 0xCB, 0xD4, 0x47, 0x85, 0x8A, 0xF5, 0xFE, 0x92, 0x46, 0x3A, 0x8E, 0xC1, 0x06, 0x36, 0xC2,
+ 0xB2, 0x46, 0xFD, 0x16, 0x36, 0xC6, 0xCD, 0xFE, 0x82, 0x46, 0xD4, 0xCB, 0x94, 0x4B, 0x93, 0xE6,
+ 0x06, 0x04, 0x94, 0xCB, 0xD4, 0x47, 0x85, 0x8A, 0xF5, 0xFE, 0xD4, 0x47, 0xD1, 0x8A, 0x85, 0xC6,
+ 0xD8, 0x47, 0xB7, 0x06, 0xF3, 0xFF, 0xFD, 0x16, 0x13, 0x67, 0x47, 0x01, 0xD8, 0xC7, 0x98, 0x4B,
+ 0x21, 0x45, 0x75, 0x8F, 0x98, 0xCB, 0x41, 0x01, 0x02, 0x90, 0x23, 0x20, 0xD8, 0x00, 0xE9, 0xBD,
+ 0x23, 0x20, 0x03, 0x01, 0x31, 0xBF, 0x82, 0x46, 0x93, 0x86, 0x06, 0x08, 0x36, 0xC0, 0xA2, 0x46,
+ 0xFD, 0x16, 0x36, 0xC4, 0xB9, 0xFA, 0x98, 0x4B, 0xB7, 0x06, 0xF3, 0xFF, 0xFD, 0x16, 0x75, 0x8F,
+ 0x98, 0xCB, 0x41, 0x89, 0x15, 0xC9, 0x2E, 0xC0, 0x0D, 0x06, 0x02, 0xC4, 0x09, 0x82, 0x32, 0xC6,
+ 0xB7, 0x17, 0x00, 0x20, 0x98, 0x43, 0x13, 0x86, 0x47, 0x00, 0xA2, 0x47, 0x82, 0x46, 0x8A, 0x07,
+ 0xB6, 0x97, 0x9C, 0x43, 0x63, 0x1C, 0xF7, 0x00, 0xA2, 0x47, 0x85, 0x07, 0x3E, 0xC4, 0xA2, 0x46,
+ 0x32, 0x47, 0xB2, 0x87, 0xE3, 0xE0, 0xE6, 0xFE, 0x01, 0x45, 0x71, 0xBF, 0x41, 0x45, 0x61, 0xBF,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -223,72 +222,72 @@ uint8_t flash_op569[ ] ={
0x01,0x45,0xc1,0xb7,
};
uint8_t flash_op573[ ] ={
- 0x79, 0x71, 0x22, 0xD4, 0x26, 0xD2, 0x5A, 0xC8, 0x06, 0xD6, 0x4A, 0xD0, 0x4E, 0xCE, 0x52, 0xCC,
- 0x56, 0xCA, 0x5E, 0xC6, 0x93, 0x77, 0x15, 0x00, 0x2A, 0x84, 0x2E, 0x8B, 0xB2, 0x84, 0x9D, 0xEF,
- 0x93, 0x77, 0x24, 0x00, 0x99, 0xCB, 0xB7, 0x86, 0x07, 0x00, 0x01, 0x46, 0x81, 0x45, 0x05, 0x45,
- 0x9D, 0x22, 0x93, 0x77, 0xF5, 0x0F, 0x09, 0x45, 0x9D, 0xEB, 0x93, 0x77, 0x44, 0x00, 0x91, 0xCB,
- 0x85, 0x66, 0x01, 0x46, 0xDA, 0x85, 0x05, 0x45, 0xB9, 0x22, 0x93, 0x77, 0xF5, 0x0F, 0x11, 0x45,
- 0x99, 0xEF, 0x93, 0x77, 0x84, 0x01, 0x9D, 0xE7, 0x01, 0x45, 0x11, 0xA8, 0x81, 0x46, 0x01, 0x46,
- 0x81, 0x45, 0x21, 0x45, 0x0D, 0x2A, 0x93, 0x77, 0xF5, 0x0F, 0x05, 0x45, 0xD5, 0xDB, 0xB2, 0x50,
- 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xF2, 0x49, 0x62, 0x4A, 0xD2, 0x4A, 0x42, 0x4B, 0xB2, 0x4B,
- 0x45, 0x61, 0x02, 0x90, 0x93, 0x84, 0xF4, 0x0F, 0x93, 0x7B, 0x84, 0x00, 0xA1, 0x80, 0x01, 0x49,
- 0xB7, 0x5A, 0x00, 0x20, 0x41, 0x88, 0x93, 0x19, 0x89, 0x00, 0x33, 0x8A, 0x69, 0x01, 0x63, 0x9F,
- 0x0B, 0x00, 0x0D, 0xC8, 0x93, 0x06, 0x00, 0x10, 0x33, 0x86, 0x59, 0x01, 0xD2, 0x85, 0x0D, 0x45,
- 0xDD, 0x20, 0x13, 0x75, 0xF5, 0x0F, 0x19, 0xCD, 0x41, 0x45, 0x55, 0xBF, 0x93, 0x06, 0x00, 0x10,
- 0x33, 0x86, 0x59, 0x01, 0xD2, 0x85, 0x09, 0x45, 0xF9, 0x20, 0x13, 0x75, 0xF5, 0x0F, 0x71, 0xD9,
- 0x21, 0x45, 0x71, 0xBF, 0x05, 0x09, 0xE3, 0x10, 0x99, 0xFC, 0xBD, 0xBF, 0x23, 0x03, 0x04, 0x80,
- 0x95, 0x47, 0x23, 0x03, 0xF4, 0x80, 0x23, 0x02, 0xA4, 0x80, 0x82, 0x80, 0x83, 0x07, 0x64, 0x80,
- 0xE3, 0xCE, 0x07, 0xFE, 0x23, 0x03, 0x04, 0x80, 0x82, 0x80, 0x83, 0x07, 0x64, 0x80, 0xE3, 0xCE,
- 0x07, 0xFE, 0x03, 0x45, 0x44, 0x80, 0x82, 0x80, 0x83, 0x07, 0x64, 0x80, 0xE3, 0xCE, 0x07, 0xFE,
- 0x23, 0x02, 0xA4, 0x80, 0x82, 0x80, 0x41, 0x11, 0x26, 0xC4, 0x4A, 0xC2, 0x4E, 0xC0, 0x06, 0xC6,
- 0x13, 0x77, 0xF5, 0x0B, 0xAD, 0x47, 0xAA, 0x89, 0x2E, 0x89, 0x95, 0x44, 0x63, 0x06, 0xF7, 0x00,
- 0x19, 0x45, 0x6D, 0x37, 0x65, 0x3F, 0x8D, 0x44, 0x4E, 0x85, 0x4D, 0x37, 0xFD, 0x59, 0xFD, 0x14,
- 0x63, 0x98, 0x34, 0x01, 0xB2, 0x40, 0xA2, 0x44, 0x12, 0x49, 0x82, 0x49, 0x41, 0x01, 0x82, 0x80,
- 0x13, 0x55, 0x09, 0x01, 0x13, 0x75, 0xF5, 0x0F, 0x45, 0x3F, 0x22, 0x09, 0xCD, 0xB7, 0x01, 0x11,
- 0x26, 0xCC, 0x06, 0xCE, 0xB7, 0x04, 0x08, 0x00, 0x51, 0x37, 0x15, 0x45, 0x85, 0x3F, 0x71, 0x37,
- 0x69, 0x37, 0x2A, 0xC6, 0xA5, 0x3F, 0x32, 0x45, 0x93, 0x77, 0x15, 0x00, 0x89, 0xEB, 0x13, 0x65,
- 0x15, 0x00, 0x13, 0x75, 0xF5, 0x0F, 0xF2, 0x40, 0xE2, 0x44, 0x05, 0x61, 0x82, 0x80, 0xFD, 0x14,
- 0xE9, 0xFC, 0x01, 0x45, 0xCD, 0xBF, 0x39, 0x71, 0x26, 0xDC, 0x4A, 0xDA, 0x4E, 0xD8, 0x52, 0xD6,
- 0x56, 0xD4, 0x5A, 0xD2, 0x5E, 0xD0, 0x06, 0xDE, 0x62, 0xCE, 0x66, 0xCC, 0xB7, 0xE7, 0x00, 0xE0,
- 0x7D, 0x57, 0x83, 0xAA, 0x07, 0x00, 0x22, 0xC6, 0x03, 0xAA, 0x47, 0x00, 0x23, 0xA0, 0xE7, 0x18,
- 0x23, 0xA2, 0xE7, 0x18, 0xB7, 0x17, 0x00, 0x40, 0x13, 0x07, 0x70, 0x05, 0x23, 0x80, 0xE7, 0x04,
- 0x13, 0x07, 0x80, 0xFA, 0x23, 0x80, 0xE7, 0x04, 0x83, 0xC7, 0x47, 0x04, 0x13, 0x09, 0x75, 0xFF,
- 0xB6, 0x84, 0xE2, 0x07, 0x13, 0x79, 0xF9, 0x0F, 0x85, 0x46, 0xAA, 0x89, 0xAE, 0x8B, 0x32, 0x8B,
- 0x37, 0x24, 0x00, 0x40, 0xE1, 0x87, 0x01, 0x57, 0x63, 0xFA, 0x26, 0x01, 0x63, 0x08, 0xD5, 0x00,
- 0x89, 0x46, 0x13, 0x07, 0x00, 0x02, 0x63, 0x13, 0xD5, 0x00, 0x01, 0x57, 0xD9, 0x8F, 0x93, 0xF7,
- 0xF7, 0x0F, 0xB7, 0x1C, 0x00, 0x40, 0x23, 0x82, 0xFC, 0x04, 0x11, 0x47, 0x23, 0x03, 0xE4, 0x80,
- 0x13, 0x05, 0xF0, 0x0F, 0x65, 0x3D, 0x09, 0x4C, 0xD1, 0x35, 0x63, 0x69, 0x2C, 0x11, 0xB7, 0x07,
- 0x07, 0x00, 0xBE, 0x9B, 0x37, 0x87, 0x07, 0x00, 0x79, 0x55, 0x63, 0xFE, 0xEB, 0x02, 0xB3, 0x87,
- 0x9B, 0x00, 0x63, 0x6A, 0xF7, 0x02, 0xA9, 0x47, 0x63, 0x99, 0xF9, 0x06, 0x89, 0xE4, 0x81, 0x44,
- 0x71, 0x3D, 0x26, 0x85, 0x0D, 0xA0, 0xDE, 0x85, 0x09, 0x45, 0x75, 0x3D, 0x05, 0x0B, 0x03, 0x45,
- 0xFB, 0xFF, 0xFD, 0x14, 0x85, 0x0B, 0x4D, 0x35, 0x81, 0xC4, 0x93, 0xF7, 0xFB, 0x0F, 0xFD, 0xF7,
- 0xFD, 0x35, 0x69, 0xFD, 0x7D, 0x55, 0xB7, 0x17, 0x00, 0x40, 0x13, 0x07, 0x70, 0x05, 0x23, 0x80,
- 0xE7, 0x04, 0x13, 0x07, 0x80, 0xFA, 0x23, 0x80, 0xE7, 0x04, 0x03, 0xC7, 0x47, 0x04, 0x41, 0x8B,
- 0x23, 0x82, 0xE7, 0x04, 0xF2, 0x50, 0xB7, 0xE7, 0x00, 0xE0, 0x23, 0xA0, 0x57, 0x11, 0x23, 0xA2,
- 0x47, 0x11, 0xE2, 0x54, 0x32, 0x44, 0x52, 0x59, 0xC2, 0x59, 0x32, 0x5A, 0xA2, 0x5A, 0x12, 0x5B,
- 0x82, 0x5B, 0x72, 0x4C, 0xE2, 0x4C, 0x21, 0x61, 0x82, 0x80, 0xA5, 0x47, 0x63, 0x95, 0xF9, 0x06,
- 0x85, 0x69, 0x13, 0x09, 0xF0, 0x0F, 0xB3, 0x06, 0x99, 0x00, 0xB3, 0xF4, 0x2B, 0x01, 0xB6, 0x94,
- 0x13, 0x49, 0xF9, 0xFF, 0xB3, 0x74, 0x99, 0x00, 0x41, 0x6B, 0x33, 0x79, 0x79, 0x01, 0x85, 0x6B,
- 0x93, 0x87, 0xF9, 0xFF, 0xB3, 0xF7, 0x27, 0x01, 0x99, 0xE3, 0x63, 0xFC, 0x34, 0x01, 0x93, 0xD9,
- 0x49, 0x00, 0xC1, 0x47, 0xE3, 0xE6, 0x37, 0xFF, 0x99, 0xBF, 0x05, 0x69, 0xC1, 0x69, 0x7D, 0x19,
- 0xD9, 0xB7, 0x13, 0x05, 0x80, 0x0D, 0x63, 0x88, 0x69, 0x01, 0x13, 0x05, 0x00, 0x02, 0x63, 0x84,
- 0x79, 0x01, 0x13, 0x05, 0x10, 0x08, 0xCA, 0x85, 0xFD, 0x3B, 0x91, 0x35, 0x21, 0xDD, 0x4E, 0x99,
- 0xB3, 0x84, 0x34, 0x41, 0xD9, 0xB7, 0xDE, 0x85, 0x2D, 0x45, 0xF5, 0x33, 0xDA, 0x94, 0xE3, 0x00,
- 0x9B, 0xF2, 0x05, 0x0B, 0xD9, 0x33, 0xA3, 0x0F, 0xAB, 0xFE, 0xD5, 0xBF, 0x93, 0x87, 0xF9, 0xFF,
- 0x93, 0xF7, 0xF7, 0x0F, 0x63, 0x6C, 0xFC, 0x08, 0x03, 0xC7, 0x5C, 0x04, 0xB7, 0x07, 0x08, 0x00,
- 0x13, 0x77, 0x07, 0x02, 0x19, 0xE3, 0xB7, 0x87, 0x07, 0x00, 0x79, 0x55, 0xE3, 0xFD, 0xFB, 0xF0,
- 0x33, 0x87, 0x9B, 0x00, 0xE3, 0xE9, 0xE7, 0xF0, 0x89, 0x47, 0x63, 0x90, 0xF9, 0x04, 0x89, 0x80,
- 0x55, 0x49, 0xE3, 0x8E, 0x04, 0xEC, 0xDE, 0x85, 0x09, 0x45, 0x71, 0x3B, 0x11, 0x0B, 0x03, 0x27,
- 0xCB, 0xFF, 0x91, 0x47, 0x23, 0x20, 0xE4, 0x80, 0x03, 0x07, 0x64, 0x80, 0xE3, 0x4E, 0x07, 0xFE,
- 0x23, 0x03, 0x24, 0x81, 0xFD, 0x17, 0xED, 0xFB, 0xFD, 0x14, 0x91, 0x0B, 0x81, 0xC4, 0x93, 0xF7,
- 0xFB, 0x0F, 0xE9, 0xFF, 0x6D, 0x3B, 0x71, 0xF5, 0xF1, 0xB5, 0x85, 0x47, 0xE3, 0x87, 0xF9, 0xF4,
- 0xDE, 0x85, 0x2D, 0x45, 0x8D, 0x33, 0x13, 0x89, 0xF4, 0xFF, 0xE3, 0x8A, 0x04, 0xE8, 0x35, 0x3B,
- 0x93, 0x77, 0x39, 0x00, 0x91, 0xEB, 0x83, 0x26, 0x04, 0x80, 0x03, 0x27, 0x0B, 0x00, 0x93, 0x07,
- 0x4B, 0x00, 0xE3, 0x9F, 0xE6, 0xE6, 0x3E, 0x8B, 0xCA, 0x84, 0xF1, 0xBF, 0xA1, 0x47, 0x63, 0x92,
- 0xF9, 0x04, 0xB5, 0x3B, 0x81, 0x44, 0x63, 0x8D, 0x0B, 0x00, 0x8D, 0x47, 0x93, 0x04, 0xC0, 0x03,
- 0x63, 0x88, 0xFB, 0x00, 0x93, 0x04, 0x00, 0x05, 0x63, 0x84, 0x8B, 0x01, 0x93, 0x04, 0x40, 0x04,
- 0x13, 0x75, 0xC5, 0x07, 0xE3, 0x05, 0x95, 0xE4, 0x19, 0x45, 0xC9, 0x39, 0xC5, 0x31, 0x05, 0x45,
- 0xF1, 0x31, 0x26, 0x85, 0xD5, 0x39, 0x09, 0x45, 0xC5, 0x39, 0x91, 0x33, 0xE3, 0x19, 0x05, 0xE2,
+ 0x79, 0x71, 0x22, 0xD4, 0x26, 0xD2, 0x5A, 0xC8, 0x06, 0xD6, 0x4A, 0xD0, 0x4E, 0xCE, 0x52, 0xCC,
+ 0x56, 0xCA, 0x5E, 0xC6, 0x93, 0x77, 0x15, 0x00, 0x2A, 0x84, 0x2E, 0x8B, 0xB2, 0x84, 0x9D, 0xEF,
+ 0x93, 0x77, 0x24, 0x00, 0x99, 0xCB, 0xB7, 0x86, 0x07, 0x00, 0x01, 0x46, 0x81, 0x45, 0x05, 0x45,
+ 0x9D, 0x22, 0x93, 0x77, 0xF5, 0x0F, 0x09, 0x45, 0x9D, 0xEB, 0x93, 0x77, 0x44, 0x00, 0x91, 0xCB,
+ 0x85, 0x66, 0x01, 0x46, 0xDA, 0x85, 0x05, 0x45, 0xB9, 0x22, 0x93, 0x77, 0xF5, 0x0F, 0x11, 0x45,
+ 0x99, 0xEF, 0x93, 0x77, 0x84, 0x01, 0x9D, 0xE7, 0x01, 0x45, 0x11, 0xA8, 0x81, 0x46, 0x01, 0x46,
+ 0x81, 0x45, 0x21, 0x45, 0x0D, 0x2A, 0x93, 0x77, 0xF5, 0x0F, 0x05, 0x45, 0xD5, 0xDB, 0xB2, 0x50,
+ 0x22, 0x54, 0x92, 0x54, 0x02, 0x59, 0xF2, 0x49, 0x62, 0x4A, 0xD2, 0x4A, 0x42, 0x4B, 0xB2, 0x4B,
+ 0x45, 0x61, 0x02, 0x90, 0x93, 0x84, 0xF4, 0x0F, 0x93, 0x7B, 0x84, 0x00, 0xA1, 0x80, 0x01, 0x49,
+ 0xB7, 0x5A, 0x00, 0x20, 0x41, 0x88, 0x93, 0x19, 0x89, 0x00, 0x33, 0x8A, 0x69, 0x01, 0x63, 0x9F,
+ 0x0B, 0x00, 0x0D, 0xC8, 0x93, 0x06, 0x00, 0x10, 0x33, 0x86, 0x59, 0x01, 0xD2, 0x85, 0x0D, 0x45,
+ 0xDD, 0x20, 0x13, 0x75, 0xF5, 0x0F, 0x19, 0xCD, 0x41, 0x45, 0x55, 0xBF, 0x93, 0x06, 0x00, 0x10,
+ 0x33, 0x86, 0x59, 0x01, 0xD2, 0x85, 0x09, 0x45, 0xF9, 0x20, 0x13, 0x75, 0xF5, 0x0F, 0x71, 0xD9,
+ 0x21, 0x45, 0x71, 0xBF, 0x05, 0x09, 0xE3, 0x10, 0x99, 0xFC, 0xBD, 0xBF, 0x23, 0x03, 0x04, 0x80,
+ 0x95, 0x47, 0x23, 0x03, 0xF4, 0x80, 0x23, 0x02, 0xA4, 0x80, 0x82, 0x80, 0x83, 0x07, 0x64, 0x80,
+ 0xE3, 0xCE, 0x07, 0xFE, 0x23, 0x03, 0x04, 0x80, 0x82, 0x80, 0x83, 0x07, 0x64, 0x80, 0xE3, 0xCE,
+ 0x07, 0xFE, 0x03, 0x45, 0x44, 0x80, 0x82, 0x80, 0x83, 0x07, 0x64, 0x80, 0xE3, 0xCE, 0x07, 0xFE,
+ 0x23, 0x02, 0xA4, 0x80, 0x82, 0x80, 0x41, 0x11, 0x26, 0xC4, 0x4A, 0xC2, 0x4E, 0xC0, 0x06, 0xC6,
+ 0x13, 0x77, 0xF5, 0x0B, 0xAD, 0x47, 0xAA, 0x89, 0x2E, 0x89, 0x95, 0x44, 0x63, 0x06, 0xF7, 0x00,
+ 0x19, 0x45, 0x6D, 0x37, 0x65, 0x3F, 0x8D, 0x44, 0x4E, 0x85, 0x4D, 0x37, 0xFD, 0x59, 0xFD, 0x14,
+ 0x63, 0x98, 0x34, 0x01, 0xB2, 0x40, 0xA2, 0x44, 0x12, 0x49, 0x82, 0x49, 0x41, 0x01, 0x82, 0x80,
+ 0x13, 0x55, 0x09, 0x01, 0x13, 0x75, 0xF5, 0x0F, 0x45, 0x3F, 0x22, 0x09, 0xCD, 0xB7, 0x01, 0x11,
+ 0x26, 0xCC, 0x06, 0xCE, 0xB7, 0x04, 0x08, 0x00, 0x51, 0x37, 0x15, 0x45, 0x85, 0x3F, 0x71, 0x37,
+ 0x69, 0x37, 0x2A, 0xC6, 0xA5, 0x3F, 0x32, 0x45, 0x93, 0x77, 0x15, 0x00, 0x89, 0xEB, 0x13, 0x65,
+ 0x15, 0x00, 0x13, 0x75, 0xF5, 0x0F, 0xF2, 0x40, 0xE2, 0x44, 0x05, 0x61, 0x82, 0x80, 0xFD, 0x14,
+ 0xE9, 0xFC, 0x01, 0x45, 0xCD, 0xBF, 0x39, 0x71, 0x26, 0xDC, 0x4A, 0xDA, 0x4E, 0xD8, 0x52, 0xD6,
+ 0x56, 0xD4, 0x5A, 0xD2, 0x5E, 0xD0, 0x06, 0xDE, 0x62, 0xCE, 0x66, 0xCC, 0xB7, 0xE7, 0x00, 0xE0,
+ 0x7D, 0x57, 0x83, 0xAA, 0x07, 0x00, 0x22, 0xC6, 0x03, 0xAA, 0x47, 0x00, 0x23, 0xA0, 0xE7, 0x18,
+ 0x23, 0xA2, 0xE7, 0x18, 0xB7, 0x17, 0x00, 0x40, 0x13, 0x07, 0x70, 0x05, 0x23, 0x80, 0xE7, 0x04,
+ 0x13, 0x07, 0x80, 0xFA, 0x23, 0x80, 0xE7, 0x04, 0x83, 0xC7, 0x47, 0x04, 0x13, 0x09, 0x75, 0xFF,
+ 0xB6, 0x84, 0xE2, 0x07, 0x13, 0x79, 0xF9, 0x0F, 0x85, 0x46, 0xAA, 0x89, 0xAE, 0x8B, 0x32, 0x8B,
+ 0x37, 0x24, 0x00, 0x40, 0xE1, 0x87, 0x01, 0x57, 0x63, 0xFA, 0x26, 0x01, 0x63, 0x08, 0xD5, 0x00,
+ 0x89, 0x46, 0x13, 0x07, 0x00, 0x02, 0x63, 0x13, 0xD5, 0x00, 0x01, 0x57, 0xD9, 0x8F, 0x93, 0xF7,
+ 0xF7, 0x0F, 0xB7, 0x1C, 0x00, 0x40, 0x23, 0x82, 0xFC, 0x04, 0x11, 0x47, 0x23, 0x03, 0xE4, 0x80,
+ 0x13, 0x05, 0xF0, 0x0F, 0x65, 0x3D, 0x09, 0x4C, 0xD1, 0x35, 0x63, 0x69, 0x2C, 0x11, 0xB7, 0x07,
+ 0x07, 0x00, 0xBE, 0x9B, 0x37, 0x87, 0x07, 0x00, 0x79, 0x55, 0x63, 0xFE, 0xEB, 0x02, 0xB3, 0x87,
+ 0x9B, 0x00, 0x63, 0x6A, 0xF7, 0x02, 0xA9, 0x47, 0x63, 0x99, 0xF9, 0x06, 0x89, 0xE4, 0x81, 0x44,
+ 0x71, 0x3D, 0x26, 0x85, 0x0D, 0xA0, 0xDE, 0x85, 0x09, 0x45, 0x75, 0x3D, 0x05, 0x0B, 0x03, 0x45,
+ 0xFB, 0xFF, 0xFD, 0x14, 0x85, 0x0B, 0x4D, 0x35, 0x81, 0xC4, 0x93, 0xF7, 0xFB, 0x0F, 0xFD, 0xF7,
+ 0xFD, 0x35, 0x69, 0xFD, 0x7D, 0x55, 0xB7, 0x17, 0x00, 0x40, 0x13, 0x07, 0x70, 0x05, 0x23, 0x80,
+ 0xE7, 0x04, 0x13, 0x07, 0x80, 0xFA, 0x23, 0x80, 0xE7, 0x04, 0x03, 0xC7, 0x47, 0x04, 0x41, 0x8B,
+ 0x23, 0x82, 0xE7, 0x04, 0xF2, 0x50, 0xB7, 0xE7, 0x00, 0xE0, 0x23, 0xA0, 0x57, 0x11, 0x23, 0xA2,
+ 0x47, 0x11, 0xE2, 0x54, 0x32, 0x44, 0x52, 0x59, 0xC2, 0x59, 0x32, 0x5A, 0xA2, 0x5A, 0x12, 0x5B,
+ 0x82, 0x5B, 0x72, 0x4C, 0xE2, 0x4C, 0x21, 0x61, 0x82, 0x80, 0xA5, 0x47, 0x63, 0x95, 0xF9, 0x06,
+ 0x85, 0x69, 0x13, 0x09, 0xF0, 0x0F, 0xB3, 0x06, 0x99, 0x00, 0xB3, 0xF4, 0x2B, 0x01, 0xB6, 0x94,
+ 0x13, 0x49, 0xF9, 0xFF, 0xB3, 0x74, 0x99, 0x00, 0x41, 0x6B, 0x33, 0x79, 0x79, 0x01, 0x85, 0x6B,
+ 0x93, 0x87, 0xF9, 0xFF, 0xB3, 0xF7, 0x27, 0x01, 0x99, 0xE3, 0x63, 0xFC, 0x34, 0x01, 0x93, 0xD9,
+ 0x49, 0x00, 0xC1, 0x47, 0xE3, 0xE6, 0x37, 0xFF, 0x99, 0xBF, 0x05, 0x69, 0xC1, 0x69, 0x7D, 0x19,
+ 0xD9, 0xB7, 0x13, 0x05, 0x80, 0x0D, 0x63, 0x88, 0x69, 0x01, 0x13, 0x05, 0x00, 0x02, 0x63, 0x84,
+ 0x79, 0x01, 0x13, 0x05, 0x10, 0x08, 0xCA, 0x85, 0xFD, 0x3B, 0x91, 0x35, 0x21, 0xDD, 0x4E, 0x99,
+ 0xB3, 0x84, 0x34, 0x41, 0xD9, 0xB7, 0xDE, 0x85, 0x2D, 0x45, 0xF5, 0x33, 0xDA, 0x94, 0xE3, 0x00,
+ 0x9B, 0xF2, 0x05, 0x0B, 0xD9, 0x33, 0xA3, 0x0F, 0xAB, 0xFE, 0xD5, 0xBF, 0x93, 0x87, 0xF9, 0xFF,
+ 0x93, 0xF7, 0xF7, 0x0F, 0x63, 0x6C, 0xFC, 0x08, 0x03, 0xC7, 0x5C, 0x04, 0xB7, 0x07, 0x08, 0x00,
+ 0x13, 0x77, 0x07, 0x02, 0x19, 0xE3, 0xB7, 0x87, 0x07, 0x00, 0x79, 0x55, 0xE3, 0xFD, 0xFB, 0xF0,
+ 0x33, 0x87, 0x9B, 0x00, 0xE3, 0xE9, 0xE7, 0xF0, 0x89, 0x47, 0x63, 0x90, 0xF9, 0x04, 0x89, 0x80,
+ 0x55, 0x49, 0xE3, 0x8E, 0x04, 0xEC, 0xDE, 0x85, 0x09, 0x45, 0x71, 0x3B, 0x11, 0x0B, 0x03, 0x27,
+ 0xCB, 0xFF, 0x91, 0x47, 0x23, 0x20, 0xE4, 0x80, 0x03, 0x07, 0x64, 0x80, 0xE3, 0x4E, 0x07, 0xFE,
+ 0x23, 0x03, 0x24, 0x81, 0xFD, 0x17, 0xED, 0xFB, 0xFD, 0x14, 0x91, 0x0B, 0x81, 0xC4, 0x93, 0xF7,
+ 0xFB, 0x0F, 0xE9, 0xFF, 0x6D, 0x3B, 0x71, 0xF5, 0xF1, 0xB5, 0x85, 0x47, 0xE3, 0x87, 0xF9, 0xF4,
+ 0xDE, 0x85, 0x2D, 0x45, 0x8D, 0x33, 0x13, 0x89, 0xF4, 0xFF, 0xE3, 0x8A, 0x04, 0xE8, 0x35, 0x3B,
+ 0x93, 0x77, 0x39, 0x00, 0x91, 0xEB, 0x83, 0x26, 0x04, 0x80, 0x03, 0x27, 0x0B, 0x00, 0x93, 0x07,
+ 0x4B, 0x00, 0xE3, 0x9F, 0xE6, 0xE6, 0x3E, 0x8B, 0xCA, 0x84, 0xF1, 0xBF, 0xA1, 0x47, 0x63, 0x92,
+ 0xF9, 0x04, 0xB5, 0x3B, 0x81, 0x44, 0x63, 0x8D, 0x0B, 0x00, 0x8D, 0x47, 0x93, 0x04, 0xC0, 0x03,
+ 0x63, 0x88, 0xFB, 0x00, 0x93, 0x04, 0x00, 0x05, 0x63, 0x84, 0x8B, 0x01, 0x93, 0x04, 0x40, 0x04,
+ 0x13, 0x75, 0xC5, 0x07, 0xE3, 0x05, 0x95, 0xE4, 0x19, 0x45, 0xC9, 0x39, 0xC5, 0x31, 0x05, 0x45,
+ 0xF1, 0x31, 0x26, 0x85, 0xD5, 0x39, 0x09, 0x45, 0xC5, 0x39, 0x91, 0x33, 0xE3, 0x19, 0x05, 0xE2,
0x91, 0xBD, 0xE3, 0x86, 0x09, 0xE2, 0xF1, 0x54, 0x25, 0xB5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -305,41 +304,41 @@ uint8_t flash_op573[ ] ={
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
};
uint8_t flash_op307[ ] ={
- 0x93, 0x77, 0x15, 0x00, 0x41, 0x11, 0x99, 0xcf, 0xb7, 0x06, 0x67, 0x45, 0xb7, 0x27, 0x02, 0x40,
- 0x93, 0x86, 0x36, 0x12, 0x37, 0x97, 0xef, 0xcd, 0xd4, 0xc3, 0x13, 0x07, 0xb7, 0x9a, 0xd8, 0xc3,
- 0xd4, 0xd3, 0xd8, 0xd3, 0x93, 0x77, 0x25, 0x00, 0x95, 0xc7, 0xb7, 0x27, 0x02, 0x40, 0x98, 0x4b,
- 0xad, 0x66, 0x37, 0x38, 0x00, 0x40, 0x13, 0x67, 0x47, 0x00, 0x98, 0xcb, 0x98, 0x4b, 0x93, 0x86,
- 0xa6, 0xaa, 0x13, 0x67, 0x07, 0x04, 0x98, 0xcb, 0xd8, 0x47, 0x05, 0x8b, 0x61, 0xeb, 0x98, 0x4b,
- 0x6d, 0x9b, 0x98, 0xcb, 0x93, 0x77, 0x45, 0x00, 0xa9, 0xcb, 0x93, 0x07, 0xf6, 0x0f, 0xa1, 0x83,
- 0x2e, 0xc0, 0x2d, 0x68, 0x81, 0x76, 0x3e, 0xc4, 0xb7, 0x08, 0x02, 0x00, 0xb7, 0x27, 0x02, 0x40,
- 0x37, 0x33, 0x00, 0x40, 0x13, 0x08, 0xa8, 0xaa, 0xfd, 0x16, 0x98, 0x4b, 0x33, 0x67, 0x17, 0x01,
- 0x98, 0xcb, 0x02, 0x47, 0xd8, 0xcb, 0x98, 0x4b, 0x13, 0x67, 0x07, 0x04, 0x98, 0xcb, 0xd8, 0x47,
- 0x05, 0x8b, 0x41, 0xeb, 0x98, 0x4b, 0x75, 0x8f, 0x98, 0xcb, 0x02, 0x47, 0x13, 0x07, 0x07, 0x10,
- 0x3a, 0xc0, 0x22, 0x47, 0x7d, 0x17, 0x3a, 0xc4, 0x69, 0xfb, 0x93, 0x77, 0x85, 0x00, 0xd5, 0xcb,
- 0x93, 0x07, 0xf6, 0x0f, 0x2e, 0xc0, 0xa1, 0x83, 0x3e, 0xc4, 0x37, 0x27, 0x02, 0x40, 0x1c, 0x4b,
- 0xc1, 0x66, 0x41, 0x68, 0xd5, 0x8f, 0x1c, 0xcb, 0xb7, 0x16, 0x00, 0x20, 0xb7, 0x27, 0x02, 0x40,
- 0x93, 0x08, 0x00, 0x04, 0x37, 0x03, 0x20, 0x00, 0x98, 0x4b, 0x33, 0x67, 0x07, 0x01, 0x98, 0xcb,
- 0xd8, 0x47, 0x05, 0x8b, 0x75, 0xff, 0x02, 0x47, 0x3a, 0xc2, 0x46, 0xc6, 0x32, 0x47, 0x0d, 0xef,
- 0x98, 0x4b, 0x33, 0x67, 0x67, 0x00, 0x98, 0xcb, 0xd8, 0x47, 0x05, 0x8b, 0x75, 0xff, 0xd8, 0x47,
- 0x41, 0x8b, 0x39, 0xc3, 0xd8, 0x47, 0xc1, 0x76, 0xfd, 0x16, 0x13, 0x67, 0x07, 0x01, 0xd8, 0xc7,
- 0x98, 0x4b, 0x21, 0x45, 0x75, 0x8f, 0x98, 0xcb, 0x41, 0x01, 0x02, 0x90, 0x23, 0x20, 0xd8, 0x00,
- 0x25, 0xb7, 0x23, 0x20, 0x03, 0x01, 0xa5, 0xb7, 0x12, 0x47, 0x13, 0x8e, 0x46, 0x00, 0x94, 0x42,
- 0x14, 0xc3, 0x12, 0x47, 0x11, 0x07, 0x3a, 0xc2, 0x32, 0x47, 0x7d, 0x17, 0x3a, 0xc6, 0xd8, 0x47,
- 0x09, 0x8b, 0x75, 0xff, 0xf2, 0x86, 0x5d, 0xb7, 0x02, 0x47, 0x13, 0x07, 0x07, 0x10, 0x3a, 0xc0,
- 0x22, 0x47, 0x7d, 0x17, 0x3a, 0xc4, 0x49, 0xf3, 0x98, 0x4b, 0xc1, 0x76, 0xfd, 0x16, 0x75, 0x8f,
- 0x98, 0xcb, 0x41, 0x89, 0x15, 0xc9, 0x2e, 0xc0, 0x0d, 0x06, 0x02, 0xc4, 0x09, 0x82, 0x32, 0xc6,
- 0xb7, 0x17, 0x00, 0x20, 0x98, 0x43, 0x13, 0x86, 0x47, 0x00, 0xa2, 0x47, 0x82, 0x46, 0x8a, 0x07,
- 0xb6, 0x97, 0x9c, 0x43, 0x63, 0x1c, 0xf7, 0x00, 0xa2, 0x47, 0x85, 0x07, 0x3e, 0xc4, 0xa2, 0x46,
- 0x32, 0x47, 0xb2, 0x87, 0xe3, 0xe0, 0xe6, 0xfe, 0x01, 0x45, 0xbd, 0xbf, 0x41, 0x45, 0xad, 0xbf,
+ 0x93, 0x77, 0x15, 0x00, 0x41, 0x11, 0x99, 0xcf, 0xb7, 0x06, 0x67, 0x45, 0xb7, 0x27, 0x02, 0x40,
+ 0x93, 0x86, 0x36, 0x12, 0x37, 0x97, 0xef, 0xcd, 0xd4, 0xc3, 0x13, 0x07, 0xb7, 0x9a, 0xd8, 0xc3,
+ 0xd4, 0xd3, 0xd8, 0xd3, 0x93, 0x77, 0x25, 0x00, 0x95, 0xc7, 0xb7, 0x27, 0x02, 0x40, 0x98, 0x4b,
+ 0xad, 0x66, 0x37, 0x38, 0x00, 0x40, 0x13, 0x67, 0x47, 0x00, 0x98, 0xcb, 0x98, 0x4b, 0x93, 0x86,
+ 0xa6, 0xaa, 0x13, 0x67, 0x07, 0x04, 0x98, 0xcb, 0xd8, 0x47, 0x05, 0x8b, 0x61, 0xeb, 0x98, 0x4b,
+ 0x6d, 0x9b, 0x98, 0xcb, 0x93, 0x77, 0x45, 0x00, 0xa9, 0xcb, 0x93, 0x07, 0xf6, 0x0f, 0xa1, 0x83,
+ 0x2e, 0xc0, 0x2d, 0x68, 0x81, 0x76, 0x3e, 0xc4, 0xb7, 0x08, 0x02, 0x00, 0xb7, 0x27, 0x02, 0x40,
+ 0x37, 0x33, 0x00, 0x40, 0x13, 0x08, 0xa8, 0xaa, 0xfd, 0x16, 0x98, 0x4b, 0x33, 0x67, 0x17, 0x01,
+ 0x98, 0xcb, 0x02, 0x47, 0xd8, 0xcb, 0x98, 0x4b, 0x13, 0x67, 0x07, 0x04, 0x98, 0xcb, 0xd8, 0x47,
+ 0x05, 0x8b, 0x41, 0xeb, 0x98, 0x4b, 0x75, 0x8f, 0x98, 0xcb, 0x02, 0x47, 0x13, 0x07, 0x07, 0x10,
+ 0x3a, 0xc0, 0x22, 0x47, 0x7d, 0x17, 0x3a, 0xc4, 0x69, 0xfb, 0x93, 0x77, 0x85, 0x00, 0xd5, 0xcb,
+ 0x93, 0x07, 0xf6, 0x0f, 0x2e, 0xc0, 0xa1, 0x83, 0x3e, 0xc4, 0x37, 0x27, 0x02, 0x40, 0x1c, 0x4b,
+ 0xc1, 0x66, 0x41, 0x68, 0xd5, 0x8f, 0x1c, 0xcb, 0xb7, 0x16, 0x00, 0x20, 0xb7, 0x27, 0x02, 0x40,
+ 0x93, 0x08, 0x00, 0x04, 0x37, 0x03, 0x20, 0x00, 0x98, 0x4b, 0x33, 0x67, 0x07, 0x01, 0x98, 0xcb,
+ 0xd8, 0x47, 0x05, 0x8b, 0x75, 0xff, 0x02, 0x47, 0x3a, 0xc2, 0x46, 0xc6, 0x32, 0x47, 0x0d, 0xef,
+ 0x98, 0x4b, 0x33, 0x67, 0x67, 0x00, 0x98, 0xcb, 0xd8, 0x47, 0x05, 0x8b, 0x75, 0xff, 0xd8, 0x47,
+ 0x41, 0x8b, 0x39, 0xc3, 0xd8, 0x47, 0xc1, 0x76, 0xfd, 0x16, 0x13, 0x67, 0x07, 0x01, 0xd8, 0xc7,
+ 0x98, 0x4b, 0x21, 0x45, 0x75, 0x8f, 0x98, 0xcb, 0x41, 0x01, 0x02, 0x90, 0x23, 0x20, 0xd8, 0x00,
+ 0x25, 0xb7, 0x23, 0x20, 0x03, 0x01, 0xa5, 0xb7, 0x12, 0x47, 0x13, 0x8e, 0x46, 0x00, 0x94, 0x42,
+ 0x14, 0xc3, 0x12, 0x47, 0x11, 0x07, 0x3a, 0xc2, 0x32, 0x47, 0x7d, 0x17, 0x3a, 0xc6, 0xd8, 0x47,
+ 0x09, 0x8b, 0x75, 0xff, 0xf2, 0x86, 0x5d, 0xb7, 0x02, 0x47, 0x13, 0x07, 0x07, 0x10, 0x3a, 0xc0,
+ 0x22, 0x47, 0x7d, 0x17, 0x3a, 0xc4, 0x49, 0xf3, 0x98, 0x4b, 0xc1, 0x76, 0xfd, 0x16, 0x75, 0x8f,
+ 0x98, 0xcb, 0x41, 0x89, 0x15, 0xc9, 0x2e, 0xc0, 0x0d, 0x06, 0x02, 0xc4, 0x09, 0x82, 0x32, 0xc6,
+ 0xb7, 0x17, 0x00, 0x20, 0x98, 0x43, 0x13, 0x86, 0x47, 0x00, 0xa2, 0x47, 0x82, 0x46, 0x8a, 0x07,
+ 0xb6, 0x97, 0x9c, 0x43, 0x63, 0x1c, 0xf7, 0x00, 0xa2, 0x47, 0x85, 0x07, 0x3e, 0xc4, 0xa2, 0x46,
+ 0x32, 0x47, 0xb2, 0x87, 0xe3, 0xe0, 0xe6, 0xfe, 0x01, 0x45, 0xbd, 0xbf, 0x41, 0x45, 0xad, 0xbf,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
};
void wlink_getromram(uint32_t *rom,uint32_t *ram){
-
+
unsigned char txbuf[4];
unsigned char rxbuf[4];
unsigned long len = 4;
@@ -353,7 +352,7 @@ void wlink_getromram(uint32_t *rom,uint32_t *ram){
pWriteData(0, 1, txbuf, &len);
len = 4;
pReadData(0, 1, rxbuf, &len);
-
+
if(chip_type==0x30700518 ||chip_type==0x30710518 ||chip_type==0x30730518 ||chip_type==0x30300514 ||chip_type==0x30310514)
type_A=true;
if(chip_type==0x30720518||chip_type==0x30740518)
@@ -397,7 +396,7 @@ void wlink_getromram(uint32_t *rom,uint32_t *ram){
}
else if(riscvchip==3){
*rom=64;
- *ram=64;
+ *ram=64;
}else{
*rom=0;
*ram=0;
@@ -448,9 +447,9 @@ void wlink_getromram(uint32_t *rom,uint32_t *ram){
}
}
-void readmcause();
-unsigned char DMI_OP(
- unsigned long iIndex,
+void readmcause(void);
+unsigned char DMI_OP(
+ unsigned long iIndex,
unsigned char iAddr,
unsigned long iData,
unsigned char iOP,
@@ -473,16 +472,16 @@ unsigned char DMI_OP(
Txbuf[7] = (unsigned char)(iData);
Txbuf[8] = iOP;
retrytime = 0;
-RETRY:
+/* RETRY: */
len = 9;
if (pWriteData(gIndex, 1, Txbuf, &len))
{
memset(Rxbuf, 0, sizeof(Rxbuf));
len = 9;
-
+
if (pReadData(gIndex, 1, Rxbuf, &len))
{
-
+
*oAddr = Rxbuf[3];
if (oData)
{
@@ -493,7 +492,7 @@ unsigned char DMI_OP(
*(pData + 3) = Rxbuf[4];
}
*oOP = Rxbuf[8];
-
+
retrytime++;
if (Rxbuf[8] == 2 && Rxbuf[6] == 3)
@@ -507,14 +506,14 @@ unsigned char DMI_OP(
return false;
}
-int wlink_reset()
+int wlink_reset(void)
{
unsigned char txbuf[4];
unsigned char rxbuf[4];
unsigned long len = 4;
txbuf[0] = 0x81;
txbuf[1] = 0x0b;
- txbuf[2] = 0x01;
+ txbuf[2] = 0x01;
txbuf[3] = 0x03;
unsigned char oAddr;
unsigned long oData;
@@ -558,7 +557,7 @@ int wlink_quitreset(void)
}
int wlink_ready_write(uint32_t address,uint32_t count)
{
-
+
unsigned char txbuf[24];
unsigned char rxbuf[24];
unsigned long len = 4;
@@ -684,8 +683,6 @@ unsigned char WriteNonFullPage(unsigned long iaddr,
unsigned char Txbuf[pagesize];
unsigned char Rxbuf[pagesize];
unsigned long len;
- unsigned char *pData;
- unsigned char retrytime;
unsigned char i = 0;
Txbuf[0] = 0x81;
Txbuf[1] = 0x0A;
@@ -696,7 +693,6 @@ unsigned char WriteNonFullPage(unsigned long iaddr,
Txbuf[5] = (unsigned char)(iaddr >> 8);
Txbuf[6] = (unsigned char)(iaddr);
Txbuf[7] = (unsigned char)ilen;
- retrytime = 0;
len = 8;
if ((riscvchip == 0x03) || (riscvchip == 0x02))
{
@@ -774,8 +770,8 @@ unsigned char WriteNonFullPage(unsigned long iaddr,
return 1;
}
}
- return 0;
}
+ return 0;
}
int wlink_verify(unsigned long length, unsigned char *buffer)
{
@@ -1138,7 +1134,7 @@ int wlink_erase(void)
ret=pReadData(0, 1, rxbuf, &len);
return ret;
}
-void readmcause()
+void readmcause(void)
{
unsigned char oAddr;
unsigned long oData;
@@ -1161,12 +1157,10 @@ int wlink_execute_queue(void)
}
int wlink_init(void)
-{
+{
unsigned char txbuf[4];
unsigned char rxbuf[20];
- char * wlink_name=NULL;
- uint64_t old_dpc_value, new_dpc_value, t6_new, t6_old;
- uint32_t dmcontrol;
+ char * wlink_name = NULL;
txbuf[0] = 0x81;
txbuf[1] = 0x0d;
txbuf[2] = 0x01;
@@ -1211,8 +1205,7 @@ int wlink_init(void)
pSetTimeout(gIndex, 5000, 5000);
}
}
-#else if
-
+#else
if (jtag_libusb_open(wlink_vids, wlink_pids, &wfd, NULL) != ERROR_OK)
{
LOG_ERROR("open failed");
@@ -1246,7 +1239,7 @@ int wlink_init(void)
wlink_name="WCH-LinkB mod:RV";
break;
default:
- LOG_ERROR("unknow WCH-LINK ");
+ LOG_ERROR("unknow WCH-LINK ");
break;
}
LOG_INFO("%s version %d.%d ",wlink_name, rxbuf[3], rxbuf[4]);
@@ -1269,7 +1262,7 @@ int wlink_init(void)
{
riscvchip = 0x01;
chipiaddr = 0x08000000;
- pagesize = 128;
+ pagesize = 128;
txbuf[0] = 0x81;
txbuf[1] = 0x06;
txbuf[2] = 0x01;
@@ -1280,7 +1273,7 @@ int wlink_init(void)
pReadData(0, 1, rxbuf, &len);
if(rxbuf[2]==rxbuf[3]==1){
LOG_ERROR("Read-Protect Status Currently Enabled");
- return ERROR_FAIL;
+ return ERROR_FAIL;
}
txbuf[0] = 0x81;
txbuf[1] = 0x0d;
@@ -1290,25 +1283,24 @@ int wlink_init(void)
pWriteData(0, 1, txbuf, &len);
len = 4;
if(pReadData(0, 1, rxbuf, &len)){
- uint64_t old_dpc_value, new_dpc_value, t6_new, t6_old;
- uint32_t dmcontrol;
uint32_t addr = 4;
unsigned char oAddr;
unsigned long oData;
unsigned char oOP;
- unsigned char iAddr;
+ unsigned char iAddr = 0; /* Wasn't initialized ?!? */
unsigned char Txbuf[52] = {0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00,
0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00,
0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00,
- 0x73, 0x00, 0x10, 0x00};
+ 0x73, 0x00, 0x10, 0x00};
DMI_OP(0, 0x20, 0x0002a283, 2, &oAddr, &oData, &oOP);
DMI_OP(0, 0x21, 0x00100073, 2, &oAddr, &oData, &oOP);
DMI_OP(0, 0x04, 0, 2, &oAddr, &oData, &oOP);
DMI_OP(0, 0x17, 0x00271005, 2, &oAddr, &oData, &oOP);
DMI_OP(0, 0x17, 0x00221005, 2, &oAddr, &oData, &oOP);
DMI_OP(0, 0x04, iAddr, 1, &oAddr, &oData, &oOP);
- WriteNonFullPage(addr, Txbuf, sizeof(Txbuf));
+ WriteNonFullPage(addr, Txbuf, sizeof(Txbuf));
int ret = DMI_OP(0, 0x04, 0x00000020, 2, &oAddr, &oData, &oOP);
+ (void) ret;
usleep(1000);
DMI_OP(0, 0x17, 0x0023101F, 2, &oAddr, &oData, &oOP);
usleep(1000);
@@ -1344,7 +1336,7 @@ int wlink_init(void)
txbuf[1] = 0x0d;
txbuf[2] = 0x01;
txbuf[3] = 0x04;
-
+
len=4;
pWriteData(0, 1, txbuf, &len);
len = 4;
@@ -1374,7 +1366,7 @@ int wlink_init(void)
break;
}
- case 5:{
+ case 5:{
riscvchip = 0x05;
chipiaddr = 0x08000000;
pagesize = 256;
@@ -1393,7 +1385,7 @@ int wlink_init(void)
pReadData(0, 1, rxbuf, &len);
if(rxbuf[2]==rxbuf[3]==1){
LOG_ERROR("Read-Protect Status Currently Enabled");
- return ERROR_FAIL;
+ return ERROR_FAIL;
}
break;
}
@@ -1417,11 +1409,11 @@ int wlink_init(void)
pReadData(0, 1, rxbuf, &len);
if(rxbuf[2]==rxbuf[3]==1){
LOG_ERROR("Read-Protect Status Currently Enabled");
- return ERROR_FAIL;
+ return ERROR_FAIL;
}
break;
}
- case 7: //
+ case 7: //
{
riscvchip = 0x02;
chipiaddr = 0x00000000;
@@ -1466,7 +1458,7 @@ int wlink_quit(void)
FreeLibrary(hModule);
hModule = 0;
}
-#else if
+#else
jtag_libusb_close(wfd);
#endif
return ERROR_OK;
@@ -1488,7 +1480,7 @@ void wlink_disabledebug(void)
len = 4;
pReadData(0, 1, rxbuf, &len);
}
-
+
}
int wlink_write(const uint8_t *buffer, uint32_t offset, uint32_t count)
{
@@ -1499,7 +1491,7 @@ int wlink_write(const uint8_t *buffer, uint32_t offset, uint32_t count)
memset(buf_bin,0xff,4 * 1024);
if (binlength <= 4096)
{
- for (int i = 0; i < count; i++)
+ for (unsigned int i = 0; i < count; i++)
{
buf_bin[i] = *(buffer + i);
}
@@ -1611,7 +1603,7 @@ static const struct command_registration wlink_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
static struct jtag_interface wlink_interface = {
-
+
.supported = DEBUG_CAP_TMS_SEQ,
.execute_queue = wlink_execute_queue,
};
diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index 3741e2dd0..83aa9aa16 100644
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -272,9 +272,9 @@ static int freertos_read_struct_value(
{
uint8_t buf[size_bytes];
int retval = target_read_buffer(target, base_address + offset, size_bytes, buf);
-
+
*value = buf_get_u64(buf, 0, size_bytes * 8);
-
+
return retval;
}
@@ -416,10 +416,10 @@ static void freertos_compute_offsets(struct rtos *rtos)
struct freertos_thread_entry *thread_entry_list_find_by_tcb(
struct list_head *list, target_addr_t tcb)
{
-
+
struct freertos_thread_entry *t;
list_for_each_entry(t, list, list) {
-
+
if (t->tcb == tcb)
return t;
}
@@ -544,10 +544,10 @@ static int freertos_update_threads(struct rtos *rtos)
LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu64,
rtos->symbols[FREERTOS_VAL_UX_TOP_USED_PRIORITY].address,
top_used_priority);
-
+
}
if (top_used_priority > FREERTOS_MAX_PRIORITIES) {
-
+
LOG_ERROR("FreeRTOS top used priority is unreasonably big, not proceeding: %" PRIu64,
top_used_priority);
return ERROR_FAIL;
@@ -638,7 +638,7 @@ static int freertos_update_threads(struct rtos *rtos)
thread_entry_list_find_by_tcb(&freertos->thread_entry_list, tcb);
if (!value) {
-
+
struct freertos_thread_entry *new_value = calloc(1, sizeof(struct freertos_thread_entry));
new_value->tcb = tcb;
/* threadid can't be 0. */
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index be253f1d5..2670b1b1e 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -38,6 +38,7 @@
#include "config.h"
#endif
+
#include
#include
#include
@@ -51,6 +52,7 @@
#include
#include "rtos/rtos.h"
#include "target/smp.h"
+#include /* for struct cmsis_dap */
/**
* @file
@@ -1731,7 +1733,7 @@ static int gdb_breakpoint_watchpoint_packet(struct connection *connection,
p=p->next;
}
if(len>2)
- type=0;
+ type=0;
}
if(riscvchip==1||riscvchip==2||riscvchip==3 ||((uint16_t)chip_type) ==0x0510){
type=0;
@@ -3164,7 +3166,7 @@ static int gdb_v_packet(struct connection *connection,
}else if(armchip){
wlink_armquitreset(cmsis_dap_handle);
}
- }
+ }
if (strncmp(packet, "vCont", 5) == 0) {
bool handled;
@@ -3201,7 +3203,7 @@ static int gdb_v_packet(struct connection *connection,
unsigned long length;
if(wchwlink){
// if(riscvchip==1||riscvchip==6)
- // {
+ // {
gdb_put_packet(connection, "OK", 2);
return ERROR_OK;
// }
@@ -3437,7 +3439,7 @@ static int gdb_input_inner(struct connection *connection)
/* terminate with zero */
gdb_packet_buffer[packet_size] = '\0';
- // if(1){
+ // if(1){
// char buf[64];
// unsigned offset = 0;
// int i = 0;
@@ -3586,7 +3588,7 @@ static int gdb_input_inner(struct connection *connection)
if (retval != ERROR_OK)
return retval;
break;
- case 'k':
+ case 'k':
if (gdb_con->extended_protocol) {
gdb_con->attached = false;
break;
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 6f5a75854..f18b0ed3e 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -31,33 +31,33 @@
#define RVFNIC_CTRLR 0xE000E048
#define NVIC_KEY 0xBEEF0000
-extern unsigned char DMI_OP(
- unsigned long iIndex,
- unsigned char iAddr,
- unsigned long iData,
- unsigned char iOP,
- unsigned char* oAddr,
- unsigned long* oData,
- unsigned char* oOP );
+extern unsigned char DMI_OP(
+ unsigned long iIndex,
+ unsigned char iAddr,
+ unsigned long iData,
+ unsigned char iOP,
+ unsigned char *oAddr,
+ unsigned long *oData,
+ unsigned char *oOP);
extern unsigned char WriteNonFullPage(unsigned long iaddr,
- unsigned char* ibuff,
- unsigned long ilen);
+ unsigned char *ibuff,
+ unsigned long ilen);
static int execute_fence(struct target *target);
extern unsigned char riscvchip;
extern unsigned long pagesize;
extern int server_quit(void);
extern unsigned long ramaddr;
-uint32_t flashaddr=0;
+uint32_t flashaddr;
extern bool wchwlink;
static int riscv013_on_step_or_resume(struct target *target, bool step);
static int riscv013_step_or_resume_current_hart(struct target *target,
- bool step, bool use_hasel);
+ bool step, bool use_hasel);
static void riscv013_clear_abstract_error(struct target *target);
/* Implementations of the functions in riscv_info_t. */
static int riscv013_get_register(struct target *target,
- riscv_reg_t *value, int rid);
+ riscv_reg_t *value, int rid);
static int riscv013_set_register(struct target *target, int regid, uint64_t value);
static int riscv013_select_current_hart(struct target *target);
static int riscv013_halt_prep(struct target *target);
@@ -70,9 +70,9 @@ static int riscv013_resume_prep(struct target *target);
static bool riscv013_is_halted(struct target *target);
static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
static int riscv013_write_debug_buffer(struct target *target, unsigned index,
- riscv_insn_t d);
+ riscv_insn_t d);
static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned
- index);
+ index);
static int riscv013_execute_debug_buffer(struct target *target);
static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a);
@@ -80,17 +80,17 @@ static int riscv013_dmi_write_u64_bits(struct target *target);
static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf);
static int register_read_direct(struct target *target, uint64_t *value, uint32_t number);
static int register_write_direct(struct target *target, unsigned number,
- uint64_t value);
+ uint64_t value);
static int read_memory(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
static int write_memory(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer);
+ uint32_t size, uint32_t count, const uint8_t *buffer);
static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address,
- uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
+ uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t *write_data,
- uint32_t write_size, uint32_t sbcs);
+ uint32_t write_size, uint32_t sbcs);
void read_memory_sba_simple(struct target *target, target_addr_t addr,
- uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs);
+ uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs);
/**
* Since almost everything can be accomplish by scanning the dbus register, all
@@ -100,14 +100,15 @@ void read_memory_sba_simple(struct target *target, target_addr_t addr,
*/
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
-#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+#define set_field(reg, mask, \
+ val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
-#define CSR_DCSR_CAUSE_SWBP 1
-#define CSR_DCSR_CAUSE_TRIGGER 2
-#define CSR_DCSR_CAUSE_DEBUGINT 3
-#define CSR_DCSR_CAUSE_STEP 4
-#define CSR_DCSR_CAUSE_HALT 5
-#define CSR_DCSR_CAUSE_GROUP 6
+#define CSR_DCSR_CAUSE_SWBP 1
+#define CSR_DCSR_CAUSE_TRIGGER 2
+#define CSR_DCSR_CAUSE_DEBUGINT 3
+#define CSR_DCSR_CAUSE_STEP 4
+#define CSR_DCSR_CAUSE_HALT 5
+#define CSR_DCSR_CAUSE_GROUP 6
#define RISCV013_INFO(r) riscv013_info_t *r = get_info(target)
@@ -132,23 +133,12 @@ typedef enum slot {
/*** Debug Bus registers. ***/
-#define CMDERR_NONE 0
-#define CMDERR_BUSY 1
-#define CMDERR_NOT_SUPPORTED 2
-#define CMDERR_EXCEPTION 3
-#define CMDERR_HALT_RESUME 4
-#define CMDERR_OTHER 7
-
-/*** Info about the core being debugged. ***/
-
-struct trigger {
- uint64_t address;
- uint32_t length;
- uint64_t mask;
- uint64_t value;
- bool read, write, execute;
- int unique_id;
-};
+#define CMDERR_NONE 0
+#define CMDERR_BUSY 1
+#define CMDERR_NOT_SUPPORTED 2
+#define CMDERR_EXCEPTION 3
+#define CMDERR_HALT_RESUME 4
+#define CMDERR_OTHER 7
typedef enum {
YNM_MAYBE,
@@ -240,8 +230,8 @@ typedef struct {
/* DM that provides access to this target. */
dm013_info_t *dm;
uint32_t flash_start_addr;
- uint32_t flash_len;
- uint32_t flash_offset;
+ uint32_t flash_len;
+ uint32_t flash_offset;
uint8_t flash_data[256];
} riscv013_info_t;
@@ -256,99 +246,71 @@ static riscv013_info_t *get_info(const struct target *target)
assert(info->version_specific);
return (riscv013_info_t *) info->version_specific;
}
-static int flush_flash_data(struct target *target)
+static void flush_flash_data(struct target *target)
{
- uint64_t regs[31];
- uint64_t s0;
- uint64_t ra;
- uint64_t sp;
- uint64_t gp;
- uint64_t tp;
+ uint64_t s1;
uint64_t a0;
+ uint64_t a1;
+ uint64_t a2;
+ uint64_t a3;
uint64_t a4;
- uint64_t a5;
- uint64_t a6;
- uint64_t a7;
- uint64_t s2;
- uint64_t s3;
- uint64_t s4;
- uint64_t s5;
- uint64_t s6;
- uint64_t s7;
- uint64_t s8;
- uint64_t s9;
- uint64_t s10;
- uint64_t s11;
- uint64_t t4;
- uint64_t t5;
- uint64_t t6;
- uint64_t t0;
- uint64_t t1;
- uint64_t t2;
- uint64_t t3;
- uint64_t s1;
- uint64_t a1;
- uint64_t a2;
- uint64_t a3;
RISCV013_INFO(info);
- //write
- if(info->flash_len)
- {
- execute_fence(target);
- register_read_direct(target, &a0, GDB_REGNO_A0);
- // register_read_direct(target, &s0, GDB_REGNO_S0);
- // register_read_direct(target, &ra, GDB_REGNO_RA);
- // register_read_direct(target, &sp, GDB_REGNO_SP);
- // register_read_direct(target, &gp, GDB_REGNO_GP);
- // register_read_direct(target, &t0, GDB_REGNO_T0);
- // register_read_direct(target, &t1, GDB_REGNO_T1);
- // register_read_direct(target, &t2, GDB_REGNO_T2);
- // register_read_direct(target, &t3, GDB_REGNO_T3);
- register_read_direct(target, &s1, GDB_REGNO_S1);
+ /* write */
+ if (info->flash_len) {
+ execute_fence(target);
+ register_read_direct(target, &a0, GDB_REGNO_A0);
+ /* register_read_direct(target, &s0, GDB_REGNO_S0); */
+ /* register_read_direct(target, &ra, GDB_REGNO_RA); */
+ /* register_read_direct(target, &sp, GDB_REGNO_SP); */
+ /* register_read_direct(target, &gp, GDB_REGNO_GP); */
+ /* register_read_direct(target, &t0, GDB_REGNO_T0); */
+ /* register_read_direct(target, &t1, GDB_REGNO_T1); */
+ /* register_read_direct(target, &t2, GDB_REGNO_T2); */
+ /* register_read_direct(target, &t3, GDB_REGNO_T3); */
+ register_read_direct(target, &s1, GDB_REGNO_S1);
register_read_direct(target, &a1, GDB_REGNO_A1);
register_read_direct(target, &a2, GDB_REGNO_A2);
register_read_direct(target, &a3, GDB_REGNO_A3);
- register_read_direct(target, &a4, GDB_REGNO_A4);
- WriteNonFullPage(info->flash_start_addr,info->flash_data,info->flash_len);
- register_write_direct(target, GDB_REGNO_A0, a0);
- // register_write_direct(target, GDB_REGNO_S0, s0);
- // register_write_direct(target, GDB_REGNO_RA, ra);
- // register_write_direct(target, GDB_REGNO_SP, sp);
- // register_write_direct(target, GDB_REGNO_GP, gp);
- // register_write_direct(target, GDB_REGNO_T0, t0);
- // register_write_direct(target, GDB_REGNO_T1, t1);
- // register_write_direct(target, GDB_REGNO_T2, t2);
- // register_write_direct(target, GDB_REGNO_T3, t3);
+ register_read_direct(target, &a4, GDB_REGNO_A4);
+ WriteNonFullPage(info->flash_start_addr,info->flash_data,info->flash_len);
+ register_write_direct(target, GDB_REGNO_A0, a0);
+ /* register_write_direct(target, GDB_REGNO_S0, s0); */
+ /* register_write_direct(target, GDB_REGNO_RA, ra); */
+ /* register_write_direct(target, GDB_REGNO_SP, sp); */
+ /* register_write_direct(target, GDB_REGNO_GP, gp); */
+ /* register_write_direct(target, GDB_REGNO_T0, t0); */
+ /* register_write_direct(target, GDB_REGNO_T1, t1); */
+ /* register_write_direct(target, GDB_REGNO_T2, t2); */
+ /* register_write_direct(target, GDB_REGNO_T3, t3); */
register_write_direct(target, GDB_REGNO_S1, s1);
register_write_direct(target, GDB_REGNO_A1, a1);
register_write_direct(target, GDB_REGNO_A2, a2);
register_write_direct(target, GDB_REGNO_A3, a3);
- register_write_direct(target, GDB_REGNO_A4, a4);
- info->flash_start_addr = 0;
- info->flash_len = 0;
- info->flash_offset = 0;
- memset(info->flash_data,0,sizeof(info->flash_data));
+ register_write_direct(target, GDB_REGNO_A4, a4);
+ info->flash_start_addr = 0;
+ info->flash_len = 0;
+ info->flash_offset = 0;
+ memset(info->flash_data, 0, 0, sizeof(info->flash_data));
}
}
int write_flash_data(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
uint32_t total_len;
- uint32_t start_address,temp,temp1;
- uint8_t * start_buffer;
- RISCV013_INFO(info);
+ uint32_t start_address;
+ const uint8_t *start_buffer;
+ RISCV013_INFO(info);
start_address = address;
start_buffer = buffer;
total_len = size*count;
- info->flash_start_addr = start_address;
+ info->flash_start_addr = start_address;
info->flash_len = total_len;
- info->flash_offset = total_len;
- memcpy(info->flash_data,start_buffer,total_len);
- if(total_len <=4)
- {
- flush_flash_data(target);
- return 0;
- }
+ info->flash_offset = total_len;
+ memcpy(info->flash_data,start_buffer,total_len);
+ if (total_len <= 4) {
+ flush_flash_data(target);
+ return 0;
+ }
return 0;
}
@@ -487,9 +449,8 @@ static void decode_dmi(char *text, unsigned address, unsigned data)
if (mask & (mask >> 1)) {
/* If the field is more than 1 bit wide. */
sprintf(text, "%s=%d", description[i].name, value);
- } else {
+ } else
strcpy(text, description[i].name);
- }
text += strlen(text);
}
}
@@ -515,10 +476,10 @@ static void dump_field(int idle, const struct scan_field *field)
unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
log_printf_lf(LOG_LVL_DEBUG,
- __FILE__, __LINE__, "scan",
- "%db %s %08x @%02x -> %s %08x @%02x; %di",
- field->num_bits, op_string[out_op], out_data, out_address,
- status_string[in_op], in_data, in_address, idle);
+ __FILE__, __LINE__, "scan",
+ "%db %s %08x @%02x -> %s %08x @%02x; %di",
+ field->num_bits, op_string[out_op], out_data, out_address,
+ status_string[in_op], in_data, in_address, idle);
char out_text[500];
char in_text[500];
@@ -526,7 +487,7 @@ static void dump_field(int idle, const struct scan_field *field)
decode_dmi(in_text, in_address, in_data);
if (in_text[0] || out_text[0]) {
log_printf_lf(LOG_LVL_DEBUG, __FILE__, __LINE__, "scan", "%s -> %s",
- out_text, in_text);
+ out_text, in_text);
}
}
@@ -569,9 +530,8 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
}
uint32_t in = buf_get_u32(field.in_value, 0, 32);
- if(wchwlink){
- buf_set_u32(&in, 0, 32, 0x00000071);
- }
+ if (wchwlink)
+ buf_set_u32((uint8_t *)&in, 0, 32, 0x00000071);
LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
return in;
@@ -582,24 +542,24 @@ static void increase_dmi_busy_delay(struct target *target)
riscv013_info_t *info = get_info(target);
info->dmi_busy_delay += info->dmi_busy_delay / 10 + 1;
LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
- info->dtmcs_idle, info->dmi_busy_delay,
- info->ac_busy_delay);
+ info->dtmcs_idle, info->dmi_busy_delay,
+ info->ac_busy_delay);
dtmcontrol_scan(target, DTM_DTMCS_DMIRESET);
}
-static int wlink_dmi_op_timeout(struct target *target, uint32_t *data_in,
- bool *dmi_busy_encountered, int dmi_op, uint32_t address,
- uint32_t data_out, int timeout_sec, bool exec, bool ensure_success)
+static int wlink_dmi_op_timeout(struct target *target, unsigned long *data_in,
+ bool *dmi_busy_encountered, int dmi_op, uint32_t address,
+ uint32_t data_out, int timeout_sec, bool exec, bool ensure_success)
{
dmi_status_t status;
uint32_t address_in;
- uint8_t recvOP;
- uint32_t recvData;
+ uint8_t recvOP;
+ unsigned long recvData;
if (dmi_busy_encountered)
*dmi_busy_encountered = false;
-
- jtag_execute_queue();
-
+
+ jtag_execute_queue();
+
const char *op_name;
switch (dmi_op) {
case DMI_OP_NOP:
@@ -617,33 +577,44 @@ static int wlink_dmi_op_timeout(struct target *target, uint32_t *data_in,
}
time_t start = time(NULL);
- int result=0;
+ int result = 0;
/* This first loop performs the request. Note that if for some reason this
* stays busy, it is actually due to the previous access. */
while (1) {
- if(dmi_op == DMI_OP_READ)
- {
- result=DMI_OP(0, (unsigned char )address, 0, (unsigned char )dmi_op, &address_in, data_in,&recvOP);
- if(!result){
- LOG_ERROR("failed %s at 0x%x, status=%d", op_name, address, status);
- LOG_ERROR("Maybe the device has been removed");
- server_quit();
- return ERROR_FAIL;
- }
- }else{
- DMI_OP(0, (unsigned char )address, data_out, (unsigned char )dmi_op, &address_in, &recvData,&recvOP);
- }
+ if (dmi_op == DMI_OP_READ) {
+ result =
+ DMI_OP(0, (unsigned char) address, 0, (unsigned char) dmi_op,
+ (unsigned char *) &address_in, data_in, &recvOP);
+ if (!result) {
+ LOG_ERROR("failed %s at 0x%x, status=%d", op_name, address, status);
+ LOG_ERROR("Maybe the device has been removed");
+ server_quit();
+ return ERROR_FAIL;
+ }
+ } else
+ DMI_OP(0,
+ (unsigned char )address,
+ data_out,
+ (unsigned char )dmi_op,
+ (unsigned char *)&address_in,
+ &recvData,
+ &recvOP);
status = recvOP;
if (status == DMI_STATUS_BUSY) {
increase_dmi_busy_delay(target);
if (dmi_busy_encountered)
*dmi_busy_encountered = true;
- DMI_OP(0, (unsigned char )DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR, (unsigned char )DMI_OP_WRITE, &address_in, &recvData,&recvOP);
- } else if (status == DMI_STATUS_SUCCESS) {
+ DMI_OP(0,
+ (unsigned char)DM_ABSTRACTCS,
+ DM_ABSTRACTCS_CMDERR,
+ (unsigned char)DMI_OP_WRITE,
+ (unsigned char *)&address_in,
+ &recvData,
+ &recvOP);
+ } else if (status == DMI_STATUS_SUCCESS)
break;
- } else {
+ else
return ERROR_FAIL;
- }
if (time(NULL) - start > timeout_sec)
return ERROR_TIMEOUT_REACHED;
}
@@ -659,8 +630,8 @@ static int wlink_dmi_op_timeout(struct target *target, uint32_t *data_in,
* run-test/idle cycles may be required.
*/
static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
- uint32_t *data_in, dmi_op_t op, uint32_t address_out, uint32_t data_out,
- bool exec)
+ uint32_t *data_in, dmi_op_t op, uint32_t address_out, uint32_t data_out,
+ bool exec)
{
riscv013_info_t *info = get_info(target);
RISCV_INFO(r);
@@ -698,9 +669,9 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
the jtag_execute_queue() call. Heap or static fields in this case doesn't seem
the best fit. Declaring stack based field values in a subsidiary function call wouldn't
work. */
- if (bscan_tunnel_ir_width != 0) {
+ if (bscan_tunnel_ir_width != 0)
riscv_add_bscan_tunneled_scan(target, &field, &bscan_ctxt);
- } else {
+ else {
/* Assume dbus is already selected. */
jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
}
@@ -721,7 +692,8 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
}
if (bscan_tunnel_ir_width != 0) {
- /* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and DM TAP */
+ /* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and
+ * DM TAP */
buffer_shr(in, num_bytes, 1);
}
@@ -751,16 +723,27 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
* DMI operation succeeded.
*/
static int dmi_op_timeout(struct target *target, uint32_t *data_in,
- bool *dmi_busy_encountered, int dmi_op, uint32_t address,
- uint32_t data_out, int timeout_sec, bool exec, bool ensure_success)
+ bool *dmi_busy_encountered, int dmi_op, uint32_t address,
+ uint32_t data_out, int timeout_sec, bool exec, bool ensure_success)
{
- int ret=1;
- if(wchwlink){
- ret=wlink_dmi_op_timeout(target,data_in,dmi_busy_encountered,dmi_op,address,data_out,timeout_sec,exec,ensure_success);
- }
- if(ret==ERROR_OK){
+ int ret = 1;
+ if (wchwlink) {
+ /* FIXME: This is where the code pays the price for all the willy-nilly */
+ /* casting between long*'s (which are 64-bit aligned) and uint32_t*'s */
+ /* which are 32-bit aligned. Overall, this whole module needs a rethinkg */
+ /* of data types. If you have to cast five arguments of a six argument */
+ /* method, or case one speicifc argument on EVERY call, you're living wrong. */
+ /* This code is living wrong. */
+ union {
+ unsigned long *l;
+ uint32_t *u32;
+ } as_long;
+ as_long.u32 = data_in;
+ ret = wlink_dmi_op_timeout(target, as_long.l, dmi_busy_encountered,
+ dmi_op, address, data_out, timeout_sec, exec, ensure_success);
+ }
+ if (ret == ERROR_OK)
return ret;
- }
select_dmi(target);
dmi_status_t status;
@@ -797,9 +780,9 @@ static int dmi_op_timeout(struct target *target, uint32_t *data_in,
increase_dmi_busy_delay(target);
if (dmi_busy_encountered)
*dmi_busy_encountered = true;
- } else if (status == DMI_STATUS_SUCCESS) {
+ } else if (status == DMI_STATUS_SUCCESS)
break;
- } else {
+ else {
LOG_ERROR("failed %s at 0x%x, status=%d", op_name, address, status);
return ERROR_FAIL;
}
@@ -817,21 +800,28 @@ static int dmi_op_timeout(struct target *target, uint32_t *data_in,
* Note that NOP can result in a 'busy' result as well, but that would be
* noticed on the next DMI access we do. */
while (1) {
- status = dmi_scan(target, &address_in, data_in, DMI_OP_NOP, address, 0,
+ status = dmi_scan(target,
+ (unsigned int *)&address_in,
+ data_in,
+ DMI_OP_NOP,
+ address,
+ 0,
false);
if (status == DMI_STATUS_BUSY) {
increase_dmi_busy_delay(target);
if (dmi_busy_encountered)
*dmi_busy_encountered = true;
- } else if (status == DMI_STATUS_SUCCESS) {
+ } else if (status == DMI_STATUS_SUCCESS)
break;
- } else {
+ else {
if (data_in) {
LOG_ERROR("Failed %s (NOP) at 0x%x; value=0x%x, status=%d",
- op_name, address, *data_in, status);
+ op_name, address, *data_in, status);
} else {
- LOG_ERROR("Failed %s (NOP) at 0x%x; status=%d", op_name, address,
- status);
+ LOG_ERROR("Failed %s (NOP) at 0x%x; status=%d",
+ op_name,
+ address,
+ status);
}
return ERROR_FAIL;
}
@@ -844,16 +834,16 @@ static int dmi_op_timeout(struct target *target, uint32_t *data_in,
}
static int dmi_op(struct target *target, uint32_t *data_in,
- bool *dmi_busy_encountered, int dmi_op, uint32_t address,
- uint32_t data_out, bool exec, bool ensure_success)
+ bool *dmi_busy_encountered, int dmi_op, uint32_t address,
+ uint32_t data_out, bool exec, bool ensure_success)
{
int result = dmi_op_timeout(target, data_in, dmi_busy_encountered, dmi_op,
address, data_out, riscv_command_timeout_sec, exec, ensure_success);
if (result == ERROR_TIMEOUT_REACHED) {
LOG_ERROR("[%s] DMI operation didn't complete in %d seconds. The target is "
- "either really slow or broken. You could increase the "
- "timeout with riscv set_command_timeout_sec.",
- target_name(target), riscv_command_timeout_sec);
+ "either really slow or broken. You could increase the "
+ "timeout with riscv set_command_timeout_sec.",
+ target_name(target), riscv_command_timeout_sec);
return ERROR_FAIL;
}
return result;
@@ -869,19 +859,19 @@ static int dmi_read_exec(struct target *target, uint32_t *value, uint32_t addres
return dmi_op(target, value, NULL, DMI_OP_READ, address, 0, true, true);
}
-static int dmi_write(struct target *target, uint32_t address, uint32_t value)
+static int dmi_write(struct target *target, uint32_t address, uint32_t value)
{
return dmi_op(target, NULL, NULL, DMI_OP_WRITE, address, value, false, true);
}
static int dmi_write_exec(struct target *target, uint32_t address,
- uint32_t value, bool ensure_success)
+ uint32_t value, bool ensure_success)
{
return dmi_op(target, NULL, NULL, DMI_OP_WRITE, address, value, true, ensure_success);
}
int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus,
- bool authenticated, unsigned timeout_sec)
+ bool authenticated, unsigned timeout_sec)
{
int result = dmi_op_timeout(target, dmstatus, NULL, DMI_OP_READ,
DM_DMSTATUS, 0, timeout_sec, false, true);
@@ -889,22 +879,22 @@ int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus,
return result;
int dmstatus_version = get_field(*dmstatus, DM_DMSTATUS_VERSION);
if (dmstatus_version != 2 && dmstatus_version != 3) {
-
+
LOG_ERROR("OpenOCD only supports Debug Module version 2 (0.13) and 3 (1.0), not "
- "%d (dmstatus=0x%x). This error might be caused by a JTAG "
- "signal issue. Try reducing the JTAG clock speed.",
- get_field(*dmstatus, DM_DMSTATUS_VERSION), *dmstatus);
+ "%d (dmstatus=0x%x). This error might be caused by a JTAG "
+ "signal issue. Try reducing the JTAG clock speed.",
+ get_field(*dmstatus, DM_DMSTATUS_VERSION), *dmstatus);
} else if (authenticated && !get_field(*dmstatus, DM_DMSTATUS_AUTHENTICATED)) {
LOG_ERROR("Debugger is not authenticated to target Debug Module. "
- "(dmstatus=0x%x). Use `riscv authdata_read` and "
- "`riscv authdata_write` commands to authenticate.", *dmstatus);
+ "(dmstatus=0x%x). Use `riscv authdata_read` and "
+ "`riscv authdata_write` commands to authenticate.", *dmstatus);
return ERROR_FAIL;
}
return ERROR_OK;
}
int dmstatus_read(struct target *target, uint32_t *dmstatus,
- bool authenticated)
+ bool authenticated)
{
return dmstatus_read_timeout(target, dmstatus, authenticated,
riscv_command_timeout_sec);
@@ -915,8 +905,8 @@ static void increase_ac_busy_delay(struct target *target)
riscv013_info_t *info = get_info(target);
info->ac_busy_delay += info->ac_busy_delay / 10 + 1;
LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
- info->dtmcs_idle, info->dmi_busy_delay,
- info->ac_busy_delay);
+ info->dtmcs_idle, info->dmi_busy_delay,
+ info->ac_busy_delay);
}
uint32_t abstract_register_size(unsigned width)
@@ -956,16 +946,17 @@ static int wait_for_idle(struct target *target, uint32_t *abstractcs)
"halt/resume",
"reserved",
"reserved",
- "other" };
+ "other"
+ };
LOG_ERROR("Abstract command ended in error '%s' (abstractcs=0x%x)",
- errors[info->cmderr], *abstractcs);
+ errors[info->cmderr], *abstractcs);
}
LOG_ERROR("Timed out after %ds waiting for busy to go low (abstractcs=0x%x). "
- "Increase the timeout with riscv set_command_timeout_sec.",
- riscv_command_timeout_sec,
- *abstractcs);
+ "Increase the timeout with riscv set_command_timeout_sec.",
+ riscv_command_timeout_sec,
+ *abstractcs);
return ERROR_FAIL;
}
}
@@ -978,13 +969,17 @@ static int execute_abstract_command(struct target *target, uint32_t command)
switch (get_field(command, DM_COMMAND_CMDTYPE)) {
case 0:
LOG_DEBUG("command=0x%x; access register, size=%d, postexec=%d, "
- "transfer=%d, write=%d, regno=0x%x",
- command,
- 8 << get_field(command, AC_ACCESS_REGISTER_AARSIZE),
- get_field(command, AC_ACCESS_REGISTER_POSTEXEC),
- get_field(command, AC_ACCESS_REGISTER_TRANSFER),
- get_field(command, AC_ACCESS_REGISTER_WRITE),
- get_field(command, AC_ACCESS_REGISTER_REGNO));
+ "transfer=%d, write=%d, regno=0x%x",
+ command,
+ 8 << get_field(command, AC_ACCESS_REGISTER_AARSIZE),
+ get_field(command,
+ AC_ACCESS_REGISTER_POSTEXEC),
+ get_field(command,
+ AC_ACCESS_REGISTER_TRANSFER),
+ get_field(command,
+ AC_ACCESS_REGISTER_WRITE),
+ get_field(command,
+ AC_ACCESS_REGISTER_REGNO));
break;
default:
LOG_DEBUG("command=0x%x", command);
@@ -1010,7 +1005,7 @@ static int execute_abstract_command(struct target *target, uint32_t command)
}
static riscv_reg_t read_abstract_arg(struct target *target, unsigned index,
- unsigned size_bits)
+ unsigned size_bits)
{
riscv_reg_t value = 0;
uint32_t v;
@@ -1022,7 +1017,7 @@ static riscv_reg_t read_abstract_arg(struct target *target, unsigned index,
case 64:
dmi_read(target, &v, DM_DATA0 + offset + 1);
value |= ((uint64_t) v) << 32;
- /* falls through */
+ /* falls through */
case 32:
dmi_read(target, &v, DM_DATA0 + offset);
value |= v;
@@ -1031,7 +1026,7 @@ static riscv_reg_t read_abstract_arg(struct target *target, unsigned index,
}
static int write_abstract_arg(struct target *target, unsigned index,
- riscv_reg_t value, unsigned size_bits)
+ riscv_reg_t value, unsigned size_bits)
{
unsigned offset = index * size_bits / 32;
switch (size_bits) {
@@ -1040,7 +1035,7 @@ static int write_abstract_arg(struct target *target, unsigned index,
return ERROR_FAIL;
case 64:
dmi_write(target, DM_DATA0 + offset + 1, value >> 32);
- /* falls through */
+ /* falls through */
case 32:
dmi_write(target, DM_DATA0 + offset, value);
}
@@ -1051,7 +1046,7 @@ static int write_abstract_arg(struct target *target, unsigned index,
* @par size in bits
*/
static uint32_t access_register_command(struct target *target, uint32_t number,
- unsigned size, uint32_t flags)
+ unsigned size, uint32_t flags)
{
uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
switch (size) {
@@ -1063,7 +1058,7 @@ static uint32_t access_register_command(struct target *target, uint32_t number,
break;
default:
LOG_ERROR("[%s] %d-bit register %s not supported.",
- target_name(target), size, gdb_regno_name(number));
+ target_name(target), size, gdb_regno_name(number));
assert(0);
}
@@ -1083,9 +1078,8 @@ static uint32_t access_register_command(struct target *target, uint32_t number,
assert(reg_info);
command = set_field(command, AC_ACCESS_REGISTER_REGNO,
0xc000 + reg_info->custom_number);
- } else {
+ } else
assert(0);
- }
command |= flags;
@@ -1093,15 +1087,15 @@ static uint32_t access_register_command(struct target *target, uint32_t number,
}
static int register_read_abstract(struct target *target, uint64_t *value,
- uint32_t number, unsigned size)
+ uint32_t number, unsigned size)
{
RISCV013_INFO(info);
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
- !info->abstract_read_fpr_supported)
+ !info->abstract_read_fpr_supported)
return ERROR_FAIL;
if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095 &&
- !info->abstract_read_csr_supported)
+ !info->abstract_read_csr_supported)
return ERROR_FAIL;
/* The spec doesn't define abstract register numbers for vector registers. */
if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31)
@@ -1131,15 +1125,15 @@ static int register_read_abstract(struct target *target, uint64_t *value,
}
static int register_write_abstract(struct target *target, uint32_t number,
- uint64_t value, unsigned size)
+ uint64_t value, unsigned size)
{
RISCV013_INFO(info);
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
- !info->abstract_write_fpr_supported)
+ !info->abstract_write_fpr_supported)
return ERROR_FAIL;
if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095 &&
- !info->abstract_write_csr_supported)
+ !info->abstract_write_csr_supported)
return ERROR_FAIL;
uint32_t command = access_register_command(target, number, size,
@@ -1193,13 +1187,13 @@ static uint32_t abstract_memory_size(unsigned width)
* Creates a memory access abstract command.
*/
static uint32_t access_memory_command(struct target *target, bool virtual,
- unsigned width, bool postincrement, bool write)
+ unsigned width, bool postincrement, bool write)
{
uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
command |= abstract_memory_size(width);
command = set_field(command, AC_ACCESS_MEMORY_AAMPOSTINCREMENT,
- postincrement);
+ postincrement);
command = set_field(command, AC_ACCESS_MEMORY_WRITE, write);
return command;
@@ -1248,12 +1242,12 @@ static int examine_progbuf(struct target *target)
return ERROR_FAIL;
if (written == (uint32_t) info->progbuf_address) {
LOG_INFO("progbuf is writable at 0x%" PRIx64,
- info->progbuf_address);
+ info->progbuf_address);
info->progbuf_writable = YNM_YES;
} else {
LOG_INFO("progbuf is not writeable at 0x%" PRIx64,
- info->progbuf_address);
+ info->progbuf_address);
info->progbuf_writable = YNM_NO;
}
@@ -1263,48 +1257,47 @@ static int examine_progbuf(struct target *target)
static int is_fpu_reg(uint32_t gdb_regno)
{
return (gdb_regno >= GDB_REGNO_FPR0 && gdb_regno <= GDB_REGNO_FPR31) ||
- (gdb_regno == GDB_REGNO_CSR0 + CSR_FFLAGS) ||
- (gdb_regno == GDB_REGNO_CSR0 + CSR_FRM) ||
- (gdb_regno == GDB_REGNO_CSR0 + CSR_FCSR);
+ (gdb_regno == GDB_REGNO_CSR0 + CSR_FFLAGS) ||
+ (gdb_regno == GDB_REGNO_CSR0 + CSR_FRM) ||
+ (gdb_regno == GDB_REGNO_CSR0 + CSR_FCSR);
}
static int is_vector_reg(uint32_t gdb_regno)
{
return (gdb_regno >= GDB_REGNO_V0 && gdb_regno <= GDB_REGNO_V31) ||
- gdb_regno == GDB_REGNO_VSTART ||
- gdb_regno == GDB_REGNO_VXSAT ||
- gdb_regno == GDB_REGNO_VXRM ||
- gdb_regno == GDB_REGNO_VL ||
- gdb_regno == GDB_REGNO_VTYPE ||
- gdb_regno == GDB_REGNO_VLENB;
+ gdb_regno == GDB_REGNO_VSTART ||
+ gdb_regno == GDB_REGNO_VXSAT ||
+ gdb_regno == GDB_REGNO_VXRM ||
+ gdb_regno == GDB_REGNO_VL ||
+ gdb_regno == GDB_REGNO_VTYPE ||
+ gdb_regno == GDB_REGNO_VLENB;
}
static int prep_for_register_access(struct target *target, uint64_t *mstatus,
- int regno)
+ int regno)
{
if (is_fpu_reg(regno) || is_vector_reg(regno)) {
if (register_read_direct(target, mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
return ERROR_FAIL;
if (is_fpu_reg(regno) && (*mstatus & MSTATUS_FS) == 0) {
if (register_write_direct(target, GDB_REGNO_MSTATUS,
- set_field(*mstatus, MSTATUS_FS, 1)) != ERROR_OK)
+ set_field(*mstatus, MSTATUS_FS, 1)) != ERROR_OK)
return ERROR_FAIL;
} else if (is_vector_reg(regno) && (*mstatus & MSTATUS_VS) == 0) {
if (register_write_direct(target, GDB_REGNO_MSTATUS,
- set_field(*mstatus, MSTATUS_VS, 1)) != ERROR_OK)
+ set_field(*mstatus, MSTATUS_VS, 1)) != ERROR_OK)
return ERROR_FAIL;
}
- } else {
+ } else
*mstatus = 0;
- }
return ERROR_OK;
}
static int cleanup_after_register_access(struct target *target,
- uint64_t mstatus, int regno)
+ uint64_t mstatus, int regno)
{
if ((is_fpu_reg(regno) && (mstatus & MSTATUS_FS) == 0) ||
- (is_vector_reg(regno) && (mstatus & MSTATUS_VS) == 0))
+ (is_vector_reg(regno) && (mstatus & MSTATUS_VS) == 0))
if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus) != ERROR_OK)
return ERROR_FAIL;
return ERROR_OK;
@@ -1330,9 +1323,9 @@ typedef struct {
* Find some scratch memory to be used with the given program.
*/
static int scratch_reserve(struct target *target,
- scratch_mem_t *scratch,
- struct riscv_program *program,
- unsigned size_bytes)
+ scratch_mem_t *scratch,
+ struct riscv_program *program,
+ unsigned size_bytes)
{
riscv_addr_t alignment = 1;
while (alignment < size_bytes)
@@ -1352,7 +1345,7 @@ static int scratch_reserve(struct target *target,
scratch->hart_address = (scratch->hart_address + alignment - 1) & ~(alignment - 1);
if ((size_bytes + scratch->hart_address - info->dataaddr + 3) / 4 >=
- info->datasize) {
+ info->datasize) {
scratch->memory_space = SPACE_DM_DATA;
scratch->debug_address = (scratch->hart_address - info->dataaddr) / 4;
return ERROR_OK;
@@ -1368,8 +1361,8 @@ static int scratch_reserve(struct target *target,
scratch->hart_address = (info->progbuf_address + program_size + alignment - 1) &
~(alignment - 1);
if ((info->progbuf_writable == YNM_YES) &&
- ((size_bytes + scratch->hart_address - info->progbuf_address + 3) / 4 >=
- info->progbufsize)) {
+ ((size_bytes + scratch->hart_address - info->progbuf_address + 3) / 4 >=
+ info->progbufsize)) {
scratch->memory_space = SPACE_DMI_PROGBUF;
scratch->debug_address = (scratch->hart_address - info->progbuf_address) / 4;
return ERROR_OK;
@@ -1377,7 +1370,7 @@ static int scratch_reserve(struct target *target,
/* Option 3: User-configured memory area as scratch RAM */
if (target_alloc_working_area(target, size_bytes + alignment - 1,
- &scratch->area) == ERROR_OK) {
+ &scratch->area) == ERROR_OK) {
scratch->hart_address = (scratch->area->address + alignment - 1) &
~(alignment - 1);
scratch->memory_space = SPACE_DMI_RAM;
@@ -1386,18 +1379,18 @@ static int scratch_reserve(struct target *target,
}
LOG_ERROR("Couldn't find %d bytes of scratch RAM to use. Please configure "
- "a work area with 'configure -work-area-phys'.", size_bytes);
+ "a work area with 'configure -work-area-phys'.", size_bytes);
return ERROR_FAIL;
}
static int scratch_release(struct target *target,
- scratch_mem_t *scratch)
+ scratch_mem_t *scratch)
{
return target_free_working_area(target, scratch->area);
}
static int scratch_read64(struct target *target, scratch_mem_t *scratch,
- uint64_t *value)
+ uint64_t *value)
{
uint32_t v;
switch (scratch->memory_space) {
@@ -1418,26 +1411,27 @@ static int scratch_read64(struct target *target, scratch_mem_t *scratch,
*value |= ((uint64_t) v) << 32;
break;
case SPACE_DMI_RAM:
- {
- uint8_t buffer[8] = {0};
- if (read_memory(target, scratch->debug_address, 4, 2, buffer, 4) != ERROR_OK)
- return ERROR_FAIL;
- *value = buffer[0] |
- (((uint64_t) buffer[1]) << 8) |
- (((uint64_t) buffer[2]) << 16) |
- (((uint64_t) buffer[3]) << 24) |
- (((uint64_t) buffer[4]) << 32) |
- (((uint64_t) buffer[5]) << 40) |
- (((uint64_t) buffer[6]) << 48) |
- (((uint64_t) buffer[7]) << 56);
- }
- break;
+ {
+ uint8_t buffer[8] = {0};
+ if (read_memory(target, scratch->debug_address, 4, 2, buffer,
+ 4) != ERROR_OK)
+ return ERROR_FAIL;
+ *value = buffer[0] |
+ (((uint64_t) buffer[1]) << 8) |
+ (((uint64_t) buffer[2]) << 16) |
+ (((uint64_t) buffer[3]) << 24) |
+ (((uint64_t) buffer[4]) << 32) |
+ (((uint64_t) buffer[5]) << 40) |
+ (((uint64_t) buffer[6]) << 48) |
+ (((uint64_t) buffer[7]) << 56);
+ }
+ break;
}
return ERROR_OK;
}
static int scratch_write64(struct target *target, scratch_mem_t *scratch,
- uint64_t value)
+ uint64_t value)
{
switch (scratch->memory_space) {
case SPACE_DM_DATA:
@@ -1449,21 +1443,21 @@ static int scratch_write64(struct target *target, scratch_mem_t *scratch,
dmi_write(target, DM_PROGBUF1 + scratch->debug_address, value >> 32);
break;
case SPACE_DMI_RAM:
- {
- uint8_t buffer[8] = {
- value,
- value >> 8,
- value >> 16,
- value >> 24,
- value >> 32,
- value >> 40,
- value >> 48,
- value >> 56
- };
- if (write_memory(target, scratch->debug_address, 4, 2, buffer) != ERROR_OK)
- return ERROR_FAIL;
- }
- break;
+ {
+ uint8_t buffer[8] = {
+ value,
+ value >> 8,
+ value >> 16,
+ value >> 24,
+ value >> 32,
+ value >> 40,
+ value >> 48,
+ value >> 56
+ };
+ if (write_memory(target, scratch->debug_address, 4, 2, buffer) != ERROR_OK)
+ return ERROR_FAIL;
+ }
+ break;
}
return ERROR_OK;
}
@@ -1492,15 +1486,15 @@ static bool has_sufficient_progbuf(struct target *target, unsigned size)
* bypasses any caches.
*/
static int register_write_direct(struct target *target, unsigned number,
- uint64_t value)
+ uint64_t value)
{
LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target),
- gdb_regno_name(number), value);
+ gdb_regno_name(number), value);
int result = register_write_abstract(target, number, value,
register_size(target, number));
if (result == ERROR_OK || !has_sufficient_progbuf(target, 2) ||
- !riscv_is_halted(target))
+ !riscv_is_halted(target))
return result;
struct riscv_program program;
@@ -1516,8 +1510,8 @@ static int register_write_direct(struct target *target, unsigned number,
scratch_mem_t scratch;
bool use_scratch = false;
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
- riscv_supports_extension(target, 'D') &&
- riscv_xlen(target) < 64) {
+ riscv_supports_extension(target, 'D') &&
+ riscv_xlen(target) < 64) {
/* There are no instructions to move all the bits from a register, so
* we need to use some scratch RAM. */
use_scratch = true;
@@ -1527,7 +1521,7 @@ static int register_write_direct(struct target *target, unsigned number,
return ERROR_FAIL;
if (register_write_direct(target, GDB_REGNO_S0, scratch.hart_address)
- != ERROR_OK) {
+ != ERROR_OK) {
scratch_release(target, &scratch);
return ERROR_FAIL;
}
@@ -1540,9 +1534,11 @@ static int register_write_direct(struct target *target, unsigned number,
} else {
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
if (riscv_supports_extension(target, 'D'))
- riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0));
+ riscv_program_insert(&program,
+ fmv_d_x(number - GDB_REGNO_FPR0, S0));
else
- riscv_program_insert(&program, fmv_w_x(number - GDB_REGNO_FPR0, S0));
+ riscv_program_insert(&program,
+ fmv_w_x(number - GDB_REGNO_FPR0, S0));
} else if (number == GDB_REGNO_VTYPE) {
if (riscv_save_register(target, GDB_REGNO_S1) != ERROR_OK)
return ERROR_FAIL;
@@ -1560,9 +1556,9 @@ static int register_write_direct(struct target *target, unsigned number,
return ERROR_FAIL;
if (riscv_program_insert(&program, vsetvl(ZERO, S0, S1)) != ERROR_OK)
return ERROR_FAIL;
- } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
+ } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
riscv_program_csrw(&program, S0, number);
- } else {
+ else {
LOG_ERROR("Unsupported register (enum gdb_regno)(%d)", number);
return ERROR_FAIL;
}
@@ -1593,8 +1589,8 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
register_size(target, number));
if (result != ERROR_OK &&
- has_sufficient_progbuf(target, 2) &&
- number > GDB_REGNO_XPR31) {
+ has_sufficient_progbuf(target, 2) &&
+ number > GDB_REGNO_XPR31) {
struct riscv_program program;
riscv_program_init(&program, target);
@@ -1612,29 +1608,30 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
if (riscv_supports_extension(target, 'D')
- && riscv_xlen(target) < 64) {
+ && riscv_xlen(target) < 64) {
/* There are no instructions to move all the bits from a
* register, so we need to use some scratch RAM. */
riscv_program_insert(&program, fsd(number - GDB_REGNO_FPR0, S0,
- 0));
+ 0));
if (scratch_reserve(target, &scratch, &program, 8) != ERROR_OK)
return ERROR_FAIL;
use_scratch = true;
if (register_write_direct(target, GDB_REGNO_S0,
- scratch.hart_address) != ERROR_OK) {
+ scratch.hart_address) != ERROR_OK) {
scratch_release(target, &scratch);
return ERROR_FAIL;
}
- } else if (riscv_supports_extension(target, 'D')) {
- riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0));
- } else {
- riscv_program_insert(&program, fmv_x_w(S0, number - GDB_REGNO_FPR0));
- }
- } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
+ } else if (riscv_supports_extension(target, 'D'))
+ riscv_program_insert(&program,
+ fmv_x_d(S0, number - GDB_REGNO_FPR0));
+ else
+ riscv_program_insert(&program,
+ fmv_x_w(S0, number - GDB_REGNO_FPR0));
+ } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
riscv_program_csrr(&program, S0, number);
- } else {
+ else {
LOG_ERROR("Unsupported register: %s", gdb_regno_name(number));
return ERROR_FAIL;
}
@@ -1660,7 +1657,7 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
if (result == ERROR_OK) {
LOG_DEBUG("{%d} %s = 0x%" PRIx64, riscv_current_hartid(target),
- gdb_regno_name(number), *value);
+ gdb_regno_name(number), *value);
}
return result;
@@ -1679,9 +1676,9 @@ static int wait_for_authbusy(struct target *target, uint32_t *dmstatus)
break;
if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("Timed out after %ds waiting for authbusy to go low (dmstatus=0x%x). "
- "Increase the timeout with riscv set_command_timeout_sec.",
- riscv_command_timeout_sec,
- value);
+ "Increase the timeout with riscv set_command_timeout_sec.",
+ riscv_command_timeout_sec,
+ value);
return ERROR_FAIL;
}
}
@@ -1719,7 +1716,7 @@ static int discover_vlenb(struct target *target)
if (register_read_direct(target, &vlenb, GDB_REGNO_VLENB) != ERROR_OK) {
LOG_WARNING("Couldn't read vlenb for %s; vector register access won't work.",
- target_name(target));
+ target_name(target));
r->vlenb = 0;
return ERROR_OK;
}
@@ -1747,7 +1744,7 @@ static int examine(struct target *target)
}
if (get_field(dtmcontrol, DTM_DTMCS_VERSION) != 1) {
LOG_ERROR("[%s] Unsupported DTM version %d. (dtmcontrol=0x%x)",
- target_name(target), get_field(dtmcontrol, DTM_DTMCS_VERSION), dtmcontrol);
+ target_name(target), get_field(dtmcontrol, DTM_DTMCS_VERSION), dtmcontrol);
return ERROR_FAIL;
}
@@ -1766,8 +1763,7 @@ static int examine(struct target *target)
dmi_write(target, DM_DMCONTROL, DM_DMCONTROL_DMACTIVE);
dm->was_reset = true;
}
- if(!wchwlink)
- {
+ if (!wchwlink) {
dmi_write(target, DM_DMCONTROL, DM_DMCONTROL_HARTSELLO |
DM_DMCONTROL_HARTSELHI | DM_DMCONTROL_DMACTIVE |
DM_DMCONTROL_HASEL);
@@ -1778,7 +1774,7 @@ static int examine(struct target *target)
if (!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE)) {
LOG_ERROR("Debug Module did not become active. dmcontrol=0x%x",
- dmcontrol);
+ dmcontrol);
return ERROR_FAIL;
}
@@ -1796,7 +1792,7 @@ static int examine(struct target *target)
uint32_t hartsel =
(get_field(dmcontrol, DM_DMCONTROL_HARTSELHI) <<
- DM_DMCONTROL_HARTSELLO_LENGTH) |
+ DM_DMCONTROL_HARTSELLO_LENGTH) |
get_field(dmcontrol, DM_DMCONTROL_HARTSELLO);
info->hartsellen = 0;
while (hartsel & 1) {
@@ -1815,8 +1811,8 @@ static int examine(struct target *target)
if (!get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED)) {
LOG_ERROR("Debugger is not authenticated to target Debug Module. "
- "(dmstatus=0x%x). Use `riscv authdata_read` and "
- "`riscv authdata_write` commands to authenticate.", dmstatus);
+ "(dmstatus=0x%x). Use `riscv authdata_read` and "
+ "`riscv authdata_write` commands to authenticate.", dmstatus);
return ERROR_FAIL;
}
@@ -1831,23 +1827,23 @@ static int examine(struct target *target)
info->progbufsize = get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE);
LOG_INFO("[%s] datacount=%d progbufsize=%d", target_name(target),
- info->datacount, info->progbufsize);
+ info->datacount, info->progbufsize);
RISCV_INFO(r);
r->impebreak = get_field(dmstatus, DM_DMSTATUS_IMPEBREAK);
if (!has_sufficient_progbuf(target, 2)) {
LOG_WARNING("We won't be able to execute fence instructions on this "
- "target. Memory may not always appear consistent. "
- "(progbufsize=%d, impebreak=%d)", info->progbufsize,
- r->impebreak);
+ "target. Memory may not always appear consistent. "
+ "(progbufsize=%d, impebreak=%d)", info->progbufsize,
+ r->impebreak);
}
if (info->progbufsize < 4 && riscv_enable_virtual) {
LOG_ERROR("set_enable_virtual is not available on this target. It "
- "requires a program buffer size of at least 4. (progbufsize=%d) "
- "Use `riscv set_enable_virtual off` to continue."
- , info->progbufsize);
+ "requires a program buffer size of at least 4. (progbufsize=%d) "
+ "Use `riscv set_enable_virtual off` to continue."
+ , info->progbufsize);
}
/* Before doing anything else we must first enumerate the harts. */
@@ -1866,7 +1862,8 @@ static int examine(struct target *target)
if (get_field(s, DM_DMSTATUS_ANYHAVERESET))
dmi_write(target, DM_DMCONTROL,
- set_hartsel(DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_ACKHAVERESET, i));
+ set_hartsel(DM_DMCONTROL_DMACTIVE |
+ DM_DMCONTROL_ACKHAVERESET, i));
}
LOG_DEBUG("Detected %d harts.", dm->hart_count);
@@ -1889,7 +1886,7 @@ static int examine(struct target *target)
if (!halted) {
if (riscv013_halt_go(target) != ERROR_OK) {
LOG_ERROR("[%s] Fatal: Hart %d failed to halt during examine()",
- target_name(target), r->current_hartid);
+ target_name(target), r->current_hartid);
return ERROR_FAIL;
}
}
@@ -1903,7 +1900,7 @@ static int examine(struct target *target)
r->xlen = 64;
else
r->xlen = 32;
- if(wchwlink)
+ if (wchwlink)
r->xlen = 32;
/* Save s0 and s1. The register cache hasn't be initialized yet so we
* need to take care of this manually. */
@@ -1934,7 +1931,7 @@ static int examine(struct target *target)
/* Display this as early as possible to help people who are using
* really slow simulators. */
LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
- r->misa);
+ r->misa);
/* Restore s0 and s1. */
if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK) {
@@ -1955,19 +1952,19 @@ static int examine(struct target *target)
return ERROR_FAIL;
if (haltgroup_supported)
LOG_INFO("Core %d made part of halt group %d.", target->coreid,
- target->smp);
+ target->smp);
else
LOG_INFO("Core %d could not be made part of halt group %d.",
- target->coreid, target->smp);
+ target->coreid, target->smp);
}
/* Some regression suites rely on seeing 'Examined RISC-V core' to know
* when they can connect with gdb/telnet.
* We will need to update those suites if we want to change that text. */
LOG_INFO("Examined RISC-V core; found %d harts",
- riscv_count_harts(target));
+ riscv_count_harts(target));
LOG_INFO(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
- r->misa);
+ r->misa);
return ERROR_OK;
}
@@ -2001,7 +1998,7 @@ static int riscv013_authdata_write(struct target *target, uint32_t value, unsign
return ERROR_FAIL;
if (!get_field(before, DM_DMSTATUS_AUTHENTICATED) &&
- get_field(after, DM_DMSTATUS_AUTHENTICATED)) {
+ get_field(after, DM_DMSTATUS_AUTHENTICATED)) {
LOG_INFO("authdata_write resulted in successful authentication");
int result = ERROR_OK;
dm013_info_t *dm = get_dm(target);
@@ -2066,16 +2063,26 @@ COMMAND_HELPER(riscv013_print_info, struct target *target)
RISCV013_INFO(info);
/* Abstract description. */
- riscv_print_info_line(CMD, "target", "memory.read_while_running8", get_field(info->sbcs, DM_SBCS_SBACCESS8));
- riscv_print_info_line(CMD, "target", "memory.write_while_running8", get_field(info->sbcs, DM_SBCS_SBACCESS8));
- riscv_print_info_line(CMD, "target", "memory.read_while_running16", get_field(info->sbcs, DM_SBCS_SBACCESS16));
- riscv_print_info_line(CMD, "target", "memory.write_while_running16", get_field(info->sbcs, DM_SBCS_SBACCESS16));
- riscv_print_info_line(CMD, "target", "memory.read_while_running32", get_field(info->sbcs, DM_SBCS_SBACCESS32));
- riscv_print_info_line(CMD, "target", "memory.write_while_running32", get_field(info->sbcs, DM_SBCS_SBACCESS32));
- riscv_print_info_line(CMD, "target", "memory.read_while_running64", get_field(info->sbcs, DM_SBCS_SBACCESS64));
- riscv_print_info_line(CMD, "target", "memory.write_while_running64", get_field(info->sbcs, DM_SBCS_SBACCESS64));
- riscv_print_info_line(CMD, "target", "memory.read_while_running128", get_field(info->sbcs, DM_SBCS_SBACCESS128));
- riscv_print_info_line(CMD, "target", "memory.write_while_running128", get_field(info->sbcs, DM_SBCS_SBACCESS128));
+ riscv_print_info_line(CMD, "target", "memory.read_while_running8",
+ get_field(info->sbcs, DM_SBCS_SBACCESS8));
+ riscv_print_info_line(CMD, "target", "memory.write_while_running8",
+ get_field(info->sbcs, DM_SBCS_SBACCESS8));
+ riscv_print_info_line(CMD, "target", "memory.read_while_running16",
+ get_field(info->sbcs, DM_SBCS_SBACCESS16));
+ riscv_print_info_line(CMD, "target", "memory.write_while_running16",
+ get_field(info->sbcs, DM_SBCS_SBACCESS16));
+ riscv_print_info_line(CMD, "target", "memory.read_while_running32",
+ get_field(info->sbcs, DM_SBCS_SBACCESS32));
+ riscv_print_info_line(CMD, "target", "memory.write_while_running32",
+ get_field(info->sbcs, DM_SBCS_SBACCESS32));
+ riscv_print_info_line(CMD, "target", "memory.read_while_running64",
+ get_field(info->sbcs, DM_SBCS_SBACCESS64));
+ riscv_print_info_line(CMD, "target", "memory.write_while_running64",
+ get_field(info->sbcs, DM_SBCS_SBACCESS64));
+ riscv_print_info_line(CMD, "target", "memory.read_while_running128",
+ get_field(info->sbcs, DM_SBCS_SBACCESS128));
+ riscv_print_info_line(CMD, "target", "memory.write_while_running128",
+ get_field(info->sbcs, DM_SBCS_SBACCESS128));
/* Lower level description. */
riscv_print_info_line(CMD, "dm", "abits", info->abits);
@@ -2090,17 +2097,18 @@ COMMAND_HELPER(riscv013_print_info, struct target *target)
uint32_t dmstatus;
if (dmstatus_read(target, &dmstatus, false) == ERROR_OK)
- riscv_print_info_line(CMD, "dm", "authenticated", get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED));
+ riscv_print_info_line(CMD, "dm", "authenticated",
+ get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED));
return 0;
}
static int prep_for_vector_access(struct target *target, uint64_t *vtype,
- uint64_t *vl, unsigned *debug_vl)
+ uint64_t *vl, unsigned *debug_vl)
{
RISCV_INFO(r);
- /* TODO: this continuous save/restore is terrible for performance. */
- /* Write vtype and vl. */
+ /* TODO: this continuous save/restore is terrible for performance.
+ * Write vtype and vl.*/
unsigned encoded_vsew;
switch (riscv_xlen(target)) {
case 32:
@@ -2130,7 +2138,7 @@ static int prep_for_vector_access(struct target *target, uint64_t *vtype,
}
static int cleanup_after_vector_access(struct target *target, uint64_t vtype,
- uint64_t vl)
+ uint64_t vl)
{
/* Restore vtype and vl. */
if (register_write_direct(target, GDB_REGNO_VTYPE, vtype) != ERROR_OK)
@@ -2141,7 +2149,7 @@ static int cleanup_after_vector_access(struct target *target, uint64_t vtype,
}
static int riscv013_get_register_buf(struct target *target,
- uint8_t *value, int regno)
+ uint8_t *value, int regno)
{
assert(regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31);
@@ -2182,9 +2190,8 @@ static int riscv013_get_register_buf(struct target *target,
if (register_read_direct(target, &v, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;
buf_set_u64(value, xlen * i, xlen, v);
- } else {
+ } else
break;
- }
}
if (cleanup_after_vector_access(target, vtype, vl) != ERROR_OK)
@@ -2197,7 +2204,7 @@ static int riscv013_get_register_buf(struct target *target,
}
static int riscv013_set_register_buf(struct target *target,
- int regno, const uint8_t *value)
+ int regno, const uint8_t *value)
{
assert(regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31);
@@ -2225,7 +2232,7 @@ static int riscv013_set_register_buf(struct target *target,
int result = ERROR_OK;
for (unsigned i = 0; i < debug_vl; i++) {
if (register_write_direct(target, GDB_REGNO_S0,
- buf_get_u64(value, xlen * i, xlen)) != ERROR_OK)
+ buf_get_u64(value, xlen * i, xlen)) != ERROR_OK)
return ERROR_FAIL;
result = riscv_program_exec(&program, target);
if (result != ERROR_OK)
@@ -2260,7 +2267,7 @@ static uint32_t sb_sbaccess(unsigned int size_bytes)
}
static int sb_write_address(struct target *target, target_addr_t address,
- bool ensure_success)
+ bool ensure_success)
{
RISCV013_INFO(info);
unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
@@ -2270,9 +2277,10 @@ static int sb_write_address(struct target *target, target_addr_t address,
if (sbasize > 64)
dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS2, 0, false, false);
if (sbasize > 32)
- dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS1, address >> 32, false, false);
+ dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS1, address >> 32, false,
+ false);
return dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS0, address,
- false, ensure_success);
+ false, ensure_success);
}
static int batch_run(const struct target *target, struct riscv_batch *batch)
@@ -2310,9 +2318,9 @@ static int sba_supports_access(struct target *target, unsigned int size_bytes)
}
static int sample_memory_bus_v1(struct target *target,
- struct riscv_sample_buf *buf,
- const riscv_sample_config_t *config,
- int64_t until_ms)
+ struct riscv_sample_buf *buf,
+ const riscv_sample_config_t *config,
+ int64_t until_ms)
{
RISCV013_INFO(info);
unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
@@ -2350,8 +2358,8 @@ static int sample_memory_bus_v1(struct target *target,
* loop.
*/
struct riscv_batch *batch = riscv_batch_alloc(
- target, 1 + enabled_count * 5 * repeat,
- info->dmi_busy_delay + info->bus_master_read_delay);
+ target, 1 + enabled_count * 5 * repeat,
+ info->dmi_busy_delay + info->bus_master_read_delay);
if (!batch)
return ERROR_FAIL;
@@ -2359,9 +2367,11 @@ static int sample_memory_bus_v1(struct target *target,
for (unsigned int n = 0; n < repeat; n++) {
for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
if (config->bucket[i].enabled) {
- if (!sba_supports_access(target, config->bucket[i].size_bytes)) {
- LOG_ERROR("Hardware does not support SBA access for %d-byte memory sampling.",
- config->bucket[i].size_bytes);
+ if (!sba_supports_access(target,
+ config->bucket[i].size_bytes)) {
+ LOG_ERROR(
+ "Hardware does not support SBA access for %d-byte memory sampling.",
+ config->bucket[i].size_bytes);
return ERROR_NOT_IMPLEMENTED;
}
@@ -2370,22 +2380,28 @@ static int sample_memory_bus_v1(struct target *target,
sbcs_write |= DM_SBCS_SBREADONDATA;
sbcs_write |= sb_sbaccess(config->bucket[i].size_bytes);
if (!sbcs_valid || sbcs_write != sbcs) {
- riscv_batch_add_dmi_write(batch, DM_SBCS, sbcs_write);
+ riscv_batch_add_dmi_write(batch, DM_SBCS,
+ sbcs_write);
sbcs = sbcs_write;
sbcs_valid = true;
}
if (sbasize > 32 &&
- (!sbaddress1_valid ||
- sbaddress1 != config->bucket[i].address >> 32)) {
+ (!sbaddress1_valid ||
+ sbaddress1 != config->bucket[i].address >> 32)) {
sbaddress1 = config->bucket[i].address >> 32;
- riscv_batch_add_dmi_write(batch, DM_SBADDRESS1, sbaddress1);
+ riscv_batch_add_dmi_write(batch,
+ DM_SBADDRESS1,
+ sbaddress1);
sbaddress1_valid = true;
}
if (!sbaddress0_valid ||
- sbaddress0 != (config->bucket[i].address & 0xffffffff)) {
+ sbaddress0 !=
+ (config->bucket[i].address & 0xffffffff)) {
sbaddress0 = config->bucket[i].address;
- riscv_batch_add_dmi_write(batch, DM_SBADDRESS0, sbaddress0);
+ riscv_batch_add_dmi_write(batch,
+ DM_SBADDRESS0,
+ sbaddress0);
sbaddress0_valid = true;
}
if (config->bucket[i].size_bytes > 4)
@@ -2412,7 +2428,8 @@ static int sample_memory_bus_v1(struct target *target,
/* Discard this batch (too much hassle to try to recover partial
* data) and try again with a larger delay. */
info->bus_master_read_delay += info->bus_master_read_delay / 10 + 1;
- dmi_write(target, DM_SBCS, sbcs_read | DM_SBCS_SBBUSYERROR | DM_SBCS_SBERROR);
+ dmi_write(target, DM_SBCS,
+ sbcs_read | DM_SBCS_SBBUSYERROR | DM_SBCS_SBERROR);
riscv_batch_free(batch);
continue;
}
@@ -2430,11 +2447,17 @@ static int sample_memory_bus_v1(struct target *target,
assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
uint64_t value = 0;
if (config->bucket[i].size_bytes > 4)
- value = ((uint64_t)riscv_batch_get_dmi_read_data(batch, read++)) << 32;
+ value =
+ ((uint64_t)riscv_batch_get_dmi_read_data(
+ batch,
+ read++)) << 32;
value |= riscv_batch_get_dmi_read_data(batch, read++);
buf->buf[buf->used] = i;
- buf_set_u64(buf->buf + buf->used + 1, 0, config->bucket[i].size_bytes * 8, value);
+ buf_set_u64(buf->buf + buf->used + 1,
+ 0,
+ config->bucket[i].size_bytes * 8,
+ value);
buf->used += 1 + config->bucket[i].size_bytes;
}
}
@@ -2447,9 +2470,9 @@ static int sample_memory_bus_v1(struct target *target,
}
static int sample_memory(struct target *target,
- struct riscv_sample_buf *buf,
- riscv_sample_config_t *config,
- int64_t until_ms)
+ struct riscv_sample_buf *buf,
+ riscv_sample_config_t *config,
+ int64_t until_ms)
{
if (!config->enabled)
return ERROR_OK;
@@ -2458,7 +2481,7 @@ static int sample_memory(struct target *target,
}
static int init_target(struct command_context *cmd_ctx,
- struct target *target)
+ struct target *target)
{
LOG_DEBUG("init");
RISCV_INFO(generic_info);
@@ -2526,7 +2549,7 @@ static int init_target(struct command_context *cmd_ctx,
static int assert_reset(struct target *target)
{
RISCV_INFO(r);
-
+
select_dmi(target);
uint32_t control_base = set_field(0, DM_DMCONTROL_DMACTIVE, 1);
@@ -2577,9 +2600,9 @@ static int assert_reset(struct target *target)
return ERROR_OK;
}
- static int deassert_reset(struct target *target)
+static int deassert_reset(struct target *target)
{
-
+
RISCV_INFO(r);
RISCV013_INFO(info);
select_dmi(target);
@@ -2589,8 +2612,8 @@ static int assert_reset(struct target *target)
control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
dmi_write(target, DM_DMCONTROL,
- set_hartsel(control, r->current_hartid));
-
+ set_hartsel(control, r->current_hartid));
+
uint32_t dmstatus;
int dmi_busy_delay = info->dmi_busy_delay;
time_t start = time(NULL);
@@ -2600,24 +2623,23 @@ static int assert_reset(struct target *target)
if (index != target->coreid)
continue;
dmi_write(target, DM_DMCONTROL,
- set_hartsel(control, index));
- } else {
+ set_hartsel(control, index));
+ } else
index = r->current_hartid;
- }
LOG_DEBUG("Waiting for hart %d to come out of reset.", index);
while (1) {
int result = dmstatus_read_timeout(target, &dmstatus, true,
riscv_reset_timeout_sec);
if (result == ERROR_TIMEOUT_REACHED)
LOG_ERROR("Hart %d didn't complete a DMI read coming out of "
- "reset in %ds; Increase the timeout with riscv "
- "set_reset_timeout_sec.",
- index, riscv_reset_timeout_sec);
+ "reset in %ds; Increase the timeout with riscv "
+ "set_reset_timeout_sec.",
+ index, riscv_reset_timeout_sec);
if (result != ERROR_OK)
return result;
- if(wchwlink)
+ if (wchwlink)
break;
-
+
/* Certain debug modules, like the one in GD32VF103
* MCUs, violate the specification's requirement that
* each hart is in "exactly one of four states" and,
@@ -2629,9 +2651,9 @@ static int assert_reset(struct target *target)
break;
if (time(NULL) - start > riscv_reset_timeout_sec) {
LOG_ERROR("Hart %d didn't leave reset in %ds; "
- "dmstatus=0x%x; "
- "Increase the timeout with riscv set_reset_timeout_sec.",
- index, riscv_reset_timeout_sec, dmstatus);
+ "dmstatus=0x%x; "
+ "Increase the timeout with riscv set_reset_timeout_sec.",
+ index, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL;
}
}
@@ -2640,30 +2662,28 @@ static int assert_reset(struct target *target)
if (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) {
/* Ack reset. */
dmi_write(target, DM_DMCONTROL,
- set_hartsel(control, index) |
- DM_DMCONTROL_ACKHAVERESET);
+ set_hartsel(control, index) |
+ DM_DMCONTROL_ACKHAVERESET);
}
if (!target->rtos)
break;
}
info->dmi_busy_delay = dmi_busy_delay;
-
+
uint64_t tmpDcsr;
int res = register_read_direct(target, &tmpDcsr, GDB_REGNO_DCSR);
- if(res != ERROR_OK){
+ if (res != ERROR_OK)
LOG_DEBUG("[wch] dcsr read fail!");
- }
- else{
- LOG_DEBUG("[wch] read dcsr value is 0x%x", tmpDcsr);
- //enable ebreak in m&u mode
+ else {
+ LOG_DEBUG("[wch] read dcsr value is 0x%llx", tmpDcsr);
+ /*enable ebreak in m&u mode */
tmpDcsr = set_field(tmpDcsr, CSR_DCSR_EBREAKM, 1);
- tmpDcsr = set_field(tmpDcsr, CSR_DCSR_EBREAKU, 1);
+ tmpDcsr = set_field(tmpDcsr, CSR_DCSR_EBREAKU, 1);
res = register_write_direct(target, GDB_REGNO_DCSR, tmpDcsr);
register_read_direct(target, &tmpDcsr, GDB_REGNO_DCSR);
- if(res == ERROR_OK){
- }
- else{
+ if (res == ERROR_OK) {
+ } else {
LOG_DEBUG("[wch] dcsr write fail");
assert(false);
}
@@ -2688,14 +2708,14 @@ static int execute_fence(struct target *target)
}
static void log_memory_access(target_addr_t address, uint64_t value,
- unsigned size_bytes, bool read)
+ unsigned size_bytes, bool read)
{
if (debug_level < LOG_LVL_DEBUG)
return;
char fmt[80];
sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%0%d" PRIx64,
- address, read ? "read" : "write", size_bytes * 2);
+ address, read ? "read" : "write", size_bytes * 2);
switch (size_bytes) {
case 1:
value &= 0xff;
@@ -2717,7 +2737,7 @@ static void log_memory_access(target_addr_t address, uint64_t value,
/* Read the relevant sbdata regs depending on size, and put the results into
* buffer. */
static int read_memory_bus_word(struct target *target, target_addr_t address,
- uint32_t size, uint8_t *buffer)
+ uint32_t size, uint8_t *buffer)
{
uint32_t value;
int result;
@@ -2759,8 +2779,8 @@ static int read_sbcs_nonbusy(struct target *target, uint32_t *sbcs)
return ERROR_OK;
if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). "
- "Increase the timeout with riscv set_command_timeout_sec.",
- riscv_command_timeout_sec, *sbcs);
+ "Increase the timeout with riscv set_command_timeout_sec.",
+ riscv_command_timeout_sec, *sbcs);
return ERROR_FAIL;
}
}
@@ -2789,7 +2809,8 @@ static int modify_privilege(struct target *target, uint64_t *mstatus, uint64_t *
/* Write MSTATUS */
if (*mstatus != *mstatus_old)
- if (register_write_direct(target, GDB_REGNO_MSTATUS, *mstatus) != ERROR_OK)
+ if (register_write_direct(target, GDB_REGNO_MSTATUS,
+ *mstatus) != ERROR_OK)
return ERROR_FAIL;
}
}
@@ -2798,7 +2819,7 @@ static int modify_privilege(struct target *target, uint64_t *mstatus, uint64_t *
}
static int read_memory_bus_v0(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{
if (size != increment) {
LOG_ERROR("sba v0 reads only support size==increment");
@@ -2806,7 +2827,7 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address,
}
LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
- TARGET_PRIxADDR, size, count, address);
+ TARGET_PRIxADDR, size, count, address);
uint8_t *t_buffer = buffer;
riscv_addr_t cur_addr = address;
riscv_addr_t fin_addr = address + (count * size);
@@ -2858,7 +2879,7 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address,
while (cur_addr < fin_addr) {
LOG_DEBUG("\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08"
- PRIx64, size, count, cur_addr);
+ PRIx64, size, count, cur_addr);
/* read */
uint32_t value;
if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK)
@@ -2887,7 +2908,7 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address,
* Read the requested memory using the system bus interface.
*/
static int read_memory_bus_v1(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{
if (increment != size && increment != 0) {
LOG_ERROR("sba v1 reads only support increment of size or 0");
@@ -2932,13 +2953,14 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
unsigned attempt = 0;
while (1) {
if (attempt++ > 100) {
- LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
- next_read);
+ LOG_ERROR(
+ "DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
+ next_read);
return ERROR_FAIL;
}
keep_alive();
dmi_status_t status = dmi_scan(target, NULL, &value,
- DMI_OP_READ, sbdata[j], 0, false);
+ DMI_OP_READ, sbdata[j], 0, false);
if (status == DMI_STATUS_BUSY)
increase_dmi_busy_delay(target);
else if (status == DMI_STATUS_SUCCESS)
@@ -2947,7 +2969,10 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
return ERROR_FAIL;
}
if (next_read != address - 1) {
- buf_set_u32(buffer + next_read - address, 0, 8 * MIN(size, 4), value);
+ buf_set_u32(buffer + next_read - address,
+ 0,
+ 8 * MIN(size, 4),
+ value);
log_memory_access(next_read, value, MIN(size, 4), true);
}
next_read = address + i * size + j * 4;
@@ -2960,11 +2985,18 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
unsigned attempt = 0;
while (1) {
if (attempt++ > 100) {
- LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
- next_read);
+ LOG_ERROR(
+ "DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
+ next_read);
return ERROR_FAIL;
}
- dmi_status_t status = dmi_scan(target, NULL, &value, DMI_OP_NOP, 0, 0, false);
+ dmi_status_t status = dmi_scan(target,
+ NULL,
+ &value,
+ DMI_OP_NOP,
+ 0,
+ 0,
+ false);
if (status == DMI_STATUS_BUSY)
increase_dmi_busy_delay(target);
else if (status == DMI_STATUS_SUCCESS)
@@ -2987,9 +3019,9 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
/* Read the last word, after we disabled sbreadondata if necessary. */
if (!get_field(sbcs_read, DM_SBCS_SBERROR) &&
- !get_field(sbcs_read, DM_SBCS_SBBUSYERROR)) {
+ !get_field(sbcs_read, DM_SBCS_SBBUSYERROR)) {
if (read_memory_bus_word(target, address + (count - 1) * size, size,
- buffer + (count - 1) * size) != ERROR_OK)
+ buffer + (count - 1) * size) != ERROR_OK)
return ERROR_FAIL;
if (read_sbcs_nonbusy(target, &sbcs_read) != ERROR_OK)
@@ -3006,9 +3038,9 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
}
unsigned error = get_field(sbcs_read, DM_SBCS_SBERROR);
- if (error == 0) {
+ if (error == 0)
next_address = end_address;
- } else {
+ else {
/* Some error indicating the bus access failed, but not because of
* something we did wrong. */
if (dmi_write(target, DM_SBCS, DM_SBCS_SBERROR) != ERROR_OK)
@@ -3028,10 +3060,10 @@ static void log_mem_access_result(struct target *target, bool success, int metho
/* Compose the message */
snprintf(msg, 60, "%s to %s memory via %s.",
- success ? "Succeeded" : "Failed",
- read ? "read" : "write",
- (method == RISCV_MEM_ACCESS_PROGBUF) ? "program buffer" :
- (method == RISCV_MEM_ACCESS_SYSBUS) ? "system bus" : "abstract access");
+ success ? "Succeeded" : "Failed",
+ read ? "read" : "write",
+ (method == RISCV_MEM_ACCESS_PROGBUF) ? "program buffer" :
+ (method == RISCV_MEM_ACCESS_SYSBUS) ? "system bus" : "abstract access");
/* Determine the log message severity. Show warnings only once. */
if (!success) {
@@ -3056,37 +3088,40 @@ static void log_mem_access_result(struct target *target, bool success, int metho
}
static bool mem_should_skip_progbuf(struct target *target, target_addr_t address,
- uint32_t size, bool read, char **skip_reason)
+ uint32_t size, bool read, char **skip_reason)
{
assert(skip_reason);
if (!has_sufficient_progbuf(target, 3)) {
LOG_DEBUG("Skipping mem %s via progbuf - insufficient progbuf size.",
- read ? "read" : "write");
+ read ? "read" : "write");
*skip_reason = "skipped (insufficient progbuf)";
return true;
}
if (target->state != TARGET_HALTED) {
LOG_DEBUG("Skipping mem %s via progbuf - target not halted.",
- read ? "read" : "write");
+ read ? "read" : "write");
*skip_reason = "skipped (target not halted)";
return true;
}
if (riscv_xlen(target) < size * 8) {
- LOG_DEBUG("Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.",
- read ? "read" : "write", riscv_xlen(target), size * 8);
+ LOG_DEBUG(
+ "Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.",
+ read ? "read" : "write",
+ riscv_xlen(target),
+ size * 8);
*skip_reason = "skipped (XLEN too short)";
return true;
}
if (size > 8) {
LOG_DEBUG("Skipping mem %s via progbuf - unsupported size.",
- read ? "read" : "write");
+ read ? "read" : "write");
*skip_reason = "skipped (unsupported size)";
return true;
}
if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
LOG_DEBUG("Skipping mem %s via progbuf - progbuf only supports %u-bit address.",
- read ? "read" : "write", riscv_xlen(target));
+ read ? "read" : "write", riscv_xlen(target));
*skip_reason = "skipped (too large address)";
return true;
}
@@ -3095,27 +3130,28 @@ static bool mem_should_skip_progbuf(struct target *target, target_addr_t address
}
static bool mem_should_skip_sysbus(struct target *target, target_addr_t address,
- uint32_t size, uint32_t increment, bool read, char **skip_reason)
+ uint32_t size, uint32_t increment, bool read, char **skip_reason)
{
assert(skip_reason);
RISCV013_INFO(info);
if (!sba_supports_access(target, size)) {
LOG_DEBUG("Skipping mem %s via system bus - unsupported size.",
- read ? "read" : "write");
+ read ? "read" : "write");
*skip_reason = "skipped (unsupported size)";
return true;
}
unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
if ((sizeof(address) * 8 > sbasize) && (address >> sbasize)) {
LOG_DEBUG("Skipping mem %s via system bus - sba only supports %u-bit address.",
- read ? "read" : "write", sbasize);
+ read ? "read" : "write", sbasize);
*skip_reason = "skipped (too large address)";
return true;
}
- if (read && increment != size && (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0)) {
+ if (read && increment != size &&
+ (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0)) {
LOG_DEBUG("Skipping mem read via system bus - "
- "sba reads only support size==increment or also size==0 for sba v1.");
+ "sba reads only support size==increment or also size==0 for sba v1.");
*skip_reason = "skipped (unsupported increment)";
return true;
}
@@ -3124,7 +3160,7 @@ static bool mem_should_skip_sysbus(struct target *target, target_addr_t address,
}
static bool mem_should_skip_abstract(struct target *target, target_addr_t address,
- uint32_t size, uint32_t increment, bool read, char **skip_reason)
+ uint32_t size, uint32_t increment, bool read, char **skip_reason)
{
assert(skip_reason);
@@ -3132,19 +3168,21 @@ static bool mem_should_skip_abstract(struct target *target, target_addr_t addres
/* TODO: Add 128b support if it's ever used. Involves modifying
read/write_abstract_arg() to work on two 64b values. */
LOG_DEBUG("Skipping mem %s via abstract access - unsupported size: %d bits",
- read ? "read" : "write", size * 8);
+ read ? "read" : "write", size * 8);
*skip_reason = "skipped (unsupported size)";
return true;
}
if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
- LOG_DEBUG("Skipping mem %s via abstract access - abstract access only supports %u-bit address.",
- read ? "read" : "write", riscv_xlen(target));
+ LOG_DEBUG(
+ "Skipping mem %s via abstract access - abstract access only supports %u-bit address.",
+ read ? "read" : "write",
+ riscv_xlen(target));
*skip_reason = "skipped (too large address)";
return true;
}
if (read && size != increment) {
LOG_ERROR("Skipping mem read via abstract access - "
- "abstract command reads only support size==increment.");
+ "abstract command reads only support size==increment.");
*skip_reason = "skipped (unsupported increment)";
return true;
}
@@ -3158,7 +3196,7 @@ static bool mem_should_skip_abstract(struct target *target, target_addr_t addres
* aamsize fields in the memory access abstract command.
*/
static int read_memory_abstract(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{
RISCV013_INFO(info);
@@ -3166,7 +3204,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
bool use_aampostincrement = info->has_aampostincrement != YNM_NO;
LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
- size, address);
+ size, address);
memset(buffer, 0, count * size);
@@ -3181,10 +3219,14 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
bool updateaddr = true;
unsigned int width32 = (width < 32) ? 32 : width;
for (uint32_t c = 0; c < count; c++) {
- /* Update the address if it is the first time or aampostincrement is not supported by the target. */
+ /* Update the address if it is the first time or aampostincrement is not supported
+ * by the target. */
if (updateaddr) {
/* Set arg1 to the address: address + c * size */
- result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target));
+ result = write_abstract_arg(target,
+ 1,
+ address + c * size,
+ riscv_xlen(target));
if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg1 during read_memory_abstract().");
return result;
@@ -3196,13 +3238,16 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
if (info->has_aampostincrement == YNM_MAYBE) {
if (result == ERROR_OK) {
- /* Safety: double-check that the address was really auto-incremented */
- riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target));
+ /* Safety: double-check that the address was really auto-incremented
+ */
+ riscv_reg_t new_address =
+ read_abstract_arg(target, 1, riscv_xlen(target));
if (new_address == address + size) {
LOG_DEBUG("aampostincrement is supported on this target.");
info->has_aampostincrement = YNM_YES;
} else {
- LOG_WARNING("Buggy aampostincrement! Address not incremented correctly.");
+ LOG_WARNING(
+ "Buggy aampostincrement! Address not incremented correctly.");
info->has_aampostincrement = YNM_NO;
}
} else {
@@ -3210,7 +3255,8 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
command = access_memory_command(target, false, width, false, false);
result = execute_abstract_command(target, command);
if (result == ERROR_OK) {
- LOG_DEBUG("aampostincrement is not supported on this target.");
+ LOG_DEBUG(
+ "aampostincrement is not supported on this target.");
info->has_aampostincrement = YNM_NO;
}
}
@@ -3237,14 +3283,14 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
* byte aamsize fields in the memory access abstract command.
*/
static int write_memory_abstract(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
RISCV013_INFO(info);
int result = ERROR_OK;
bool use_aampostincrement = info->has_aampostincrement != YNM_NO;
LOG_DEBUG("writing %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
- size, address);
+ size, address);
/* Convert the size (bytes) to width (bits) */
unsigned width = size << 3;
@@ -3264,10 +3310,14 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
return result;
}
- /* Update the address if it is the first time or aampostincrement is not supported by the target. */
+ /* Update the address if it is the first time or aampostincrement is not supported
+ * by the target. */
if (updateaddr) {
/* Set arg1 to the address: address + c * size */
- result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target));
+ result = write_abstract_arg(target,
+ 1,
+ address + c * size,
+ riscv_xlen(target));
if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg1 during write_memory_abstract().");
return result;
@@ -3279,13 +3329,16 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
if (info->has_aampostincrement == YNM_MAYBE) {
if (result == ERROR_OK) {
- /* Safety: double-check that the address was really auto-incremented */
- riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target));
+ /* Safety: double-check that the address was really auto-incremented
+ */
+ riscv_reg_t new_address =
+ read_abstract_arg(target, 1, riscv_xlen(target));
if (new_address == address + size) {
LOG_DEBUG("aampostincrement is supported on this target.");
info->has_aampostincrement = YNM_YES;
} else {
- LOG_WARNING("Buggy aampostincrement! Address not incremented correctly.");
+ LOG_WARNING(
+ "Buggy aampostincrement! Address not incremented correctly.");
info->has_aampostincrement = YNM_NO;
}
} else {
@@ -3293,7 +3346,8 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
command = access_memory_command(target, false, width, false, true);
result = execute_abstract_command(target, command);
if (result == ERROR_OK) {
- LOG_DEBUG("aampostincrement is not supported on this target.");
+ LOG_DEBUG(
+ "aampostincrement is not supported on this target.");
info->has_aampostincrement = YNM_NO;
}
}
@@ -3315,7 +3369,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
* even if cmderr=busy is encountered.
*/
static int read_memory_progbuf_inner(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{
RISCV013_INFO(info);
@@ -3327,7 +3381,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
return result;
if (increment == 0 &&
- register_write_direct(target, GDB_REGNO_S2, 0) != ERROR_OK)
+ register_write_direct(target, GDB_REGNO_S2, 0) != ERROR_OK)
return ERROR_FAIL;
uint32_t command = access_register_command(target, GDB_REGNO_S1,
@@ -3349,7 +3403,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
if (dmi_write(target, DM_ABSTRACTAUTO,
1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) != ERROR_OK)
goto error;
- result=ERROR_FAIL;
+ result = ERROR_FAIL;
goto error;
/* Read garbage from dmi_data0, which triggers another execution of the
* program. Now dmi_data0 contains the first good result, and s1 the next
@@ -3423,7 +3477,8 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
riscv_batch_free(batch);
goto error;
}
- if (size > 4 && dmi_read(target, &dmi_data1, DM_DATA1) != ERROR_OK) {
+ if (size > 4 &&
+ dmi_read(target, &dmi_data1, DM_DATA1) != ERROR_OK) {
riscv_batch_free(batch);
goto error;
}
@@ -3431,12 +3486,14 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
/* See how far we got, clobbering dmi_data0. */
if (increment == 0) {
uint64_t counter;
- result = register_read_direct(target, &counter, GDB_REGNO_S2);
+ result =
+ register_read_direct(target, &counter,
+ GDB_REGNO_S2);
next_index = counter;
} else {
uint64_t next_read_addr;
result = register_read_direct(target, &next_read_addr,
- GDB_REGNO_S0);
+ GDB_REGNO_S0);
next_index = (next_read_addr - address) / increment;
}
if (result != ERROR_OK) {
@@ -3446,7 +3503,10 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
uint64_t value64 = (((uint64_t)dmi_data1) << 32) | dmi_data0;
buf_set_u64(buffer + (next_index - 2) * size, 0, 8 * size, value64);
- log_memory_access(address + (next_index - 2) * size, value64, size, true);
+ log_memory_access(address + (next_index - 2) * size,
+ value64,
+ size,
+ true);
/* Restore the command, and execute it.
* Now DM_DATA0 contains the next value just as it would if no
@@ -3455,13 +3515,14 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
next_index++;
dmi_write(target, DM_ABSTRACTAUTO,
- 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
+ 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
ignore_last = 1;
break;
default:
- LOG_DEBUG("error when reading memory, abstractcs=0x%08lx", (long)abstractcs);
+ LOG_DEBUG("error when reading memory, abstractcs=0x%08lx",
+ (long)abstractcs);
riscv013_clear_abstract_error(target);
riscv_batch_free(batch);
result = ERROR_FAIL;
@@ -3492,7 +3553,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
* rare in any case, we return error here and rely on our
* caller to reread the entire block. */
LOG_WARNING("Batch memory read encountered DMI error %d. "
- "Falling back on slower reads.", status);
+ "Falling back on slower reads.", status);
riscv_batch_free(batch);
result = ERROR_FAIL;
goto error;
@@ -3501,7 +3562,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
status = riscv_batch_get_dmi_read_op(batch, read);
if (status != DMI_STATUS_SUCCESS) {
LOG_WARNING("Batch memory read encountered DMI error %d. "
- "Falling back on slower reads.", status);
+ "Falling back on slower reads.", status);
riscv_batch_free(batch);
result = ERROR_FAIL;
goto error;
@@ -3553,7 +3614,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
/* Only need to save/restore one GPR to read a single word, and the progbuf
* program doesn't need to increment. */
static int read_memory_progbuf_one(struct target *target, target_addr_t address,
- uint32_t size, uint8_t *buffer)
+ uint32_t size, uint8_t *buffer)
{
uint64_t mstatus = 0;
uint64_t mstatus_old = 0;
@@ -3568,7 +3629,8 @@ static int read_memory_progbuf_one(struct target *target, target_addr_t address,
/* Write the program (load, increment) */
struct riscv_program program;
riscv_program_init(&program, target);
- if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
+ if (riscv_enable_virtual &&
+ has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
riscv_program_csrrsi(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
switch (size) {
case 1:
@@ -3587,7 +3649,8 @@ static int read_memory_progbuf_one(struct target *target, target_addr_t address,
LOG_ERROR("Unsupported size: %d", size);
goto restore_mstatus;
}
- if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
+ if (riscv_enable_virtual &&
+ has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
riscv_program_csrrci(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
if (riscv_program_ebreak(&program) != ERROR_OK)
@@ -3623,18 +3686,18 @@ static int read_memory_progbuf_one(struct target *target, target_addr_t address,
* Read the requested memory, silently handling memory access errors.
*/
static int read_memory_progbuf(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{
if (riscv_xlen(target) < size * 8) {
LOG_ERROR("XLEN (%d) is too short for %d-bit memory read.",
- riscv_xlen(target), size * 8);
+ riscv_xlen(target), size * 8);
return ERROR_FAIL;
}
int result = ERROR_OK;
LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
- size, address);
+ size, address);
select_dmi(target);
@@ -3665,7 +3728,8 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
/* Write the program (load, increment) */
struct riscv_program program;
riscv_program_init(&program, target);
- if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
+ if (riscv_enable_virtual &&
+ has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
riscv_program_csrrsi(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
switch (size) {
@@ -3686,7 +3750,8 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
return ERROR_FAIL;
}
- if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
+ if (riscv_enable_virtual &&
+ has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
riscv_program_csrrci(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
if (increment == 0)
riscv_program_addi(&program, GDB_REGNO_S2, GDB_REGNO_S2, 1);
@@ -3701,9 +3766,11 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
result = read_memory_progbuf_inner(target, address, size, count, buffer, increment);
if (result != ERROR_OK) {
- /* The full read did not succeed, so we will try to read each word individually. */
- /* This will not be fast, but reading outside actual memory is a special case anyway. */
- /* It will make the toolchain happier, especially Eclipse Memory View as it reads ahead. */
+ /* The full read did not succeed, so we will try to read each word individually.
+ * This will not be fast, but reading outside actual memory is a special case
+ *anyway.
+ * It will make the toolchain happier, especially Eclipse Memory View as it reads
+ *ahead.*/
target_addr_t address_i = address;
uint32_t count_i = 1;
uint8_t *buffer_i = buffer;
@@ -3711,12 +3778,20 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
for (uint32_t i = 0; i < count; i++, address_i += increment, buffer_i += size) {
/* TODO: This is much slower than it needs to be because we end up
* writing the address to read for every word we read. */
- result = read_memory_progbuf_inner(target, address_i, size, count_i, buffer_i, increment);
-
- /* The read of a single word failed, so we will just return 0 for that instead */
+ result = read_memory_progbuf_inner(target,
+ address_i,
+ size,
+ count_i,
+ buffer_i,
+ increment);
+
+ /* The read of a single word failed, so we will just return 0 for that
+ * instead */
if (result != ERROR_OK) {
- LOG_DEBUG("error reading single word of %d bytes from 0x%" TARGET_PRIxADDR,
- size, address_i);
+ LOG_DEBUG(
+ "error reading single word of %d bytes from 0x%" TARGET_PRIxADDR,
+ size,
+ address_i);
buf_set_u64(buffer_i, 0, 8 * size, 0);
}
@@ -3733,7 +3808,7 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
}
static int read_memory(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{
if (count == 0)
return ERROR_OK;
@@ -3763,18 +3838,30 @@ static int read_memory(struct target *target, target_addr_t address,
if (ret != ERROR_OK)
progbuf_result = "failed";
} else if (method == RISCV_MEM_ACCESS_SYSBUS) {
- if (mem_should_skip_sysbus(target, address, size, increment, true, &sysbus_result))
+ if (mem_should_skip_sysbus(target, address, size, increment, true,
+ &sysbus_result))
continue;
if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0)
- ret = read_memory_bus_v0(target, address, size, count, buffer, increment);
+ ret = read_memory_bus_v0(target,
+ address,
+ size,
+ count,
+ buffer,
+ increment);
else if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 1)
- ret = read_memory_bus_v1(target, address, size, count, buffer, increment);
+ ret = read_memory_bus_v1(target,
+ address,
+ size,
+ count,
+ buffer,
+ increment);
if (ret != ERROR_OK)
sysbus_result = "failed";
} else if (method == RISCV_MEM_ACCESS_ABSTRACT) {
- if (mem_should_skip_abstract(target, address, size, increment, true, &abstract_result))
+ if (mem_should_skip_abstract(target, address, size, increment, true,
+ &abstract_result))
continue;
ret = read_memory_abstract(target, address, size, count, buffer, increment);
@@ -3791,17 +3878,22 @@ static int read_memory(struct target *target, target_addr_t address,
return ret;
}
- LOG_ERROR("Target %s: Failed to read memory (addr=0x%" PRIx64 ")", target_name(target), address);
- LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result);
+ LOG_ERROR("Target %s: Failed to read memory (addr=0x%" PRIx64 ")",
+ target_name(target),
+ address);
+ LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s",
+ progbuf_result,
+ sysbus_result,
+ abstract_result);
return ret;
}
static int write_memory_bus_v0(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
/*1) write sbaddress: for singlewrite and autoincrement, we need to write the address once*/
LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
- TARGET_PRIxADDR, size, count, address);
+ TARGET_PRIxADDR, size, count, address);
dmi_write(target, DM_SBADDRESS0, address);
int64_t value = 0;
int64_t access = 0;
@@ -3810,7 +3902,7 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address,
const uint8_t *t_buffer = buffer + offset;
/* B.8 Writing Memory, single write check if we write in one go */
- if (count == 1) { /* count is in bytes here */
+ if (count == 1) { /* count is in bytes here */
value = buf_get_u64(t_buffer, 0, 8 * size);
access = 0;
@@ -3839,10 +3931,11 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address,
value = buf_get_u64(t_buffer, 0, 8 * size);
LOG_DEBUG("SAB:autoincrement: expected address: 0x%08x value: 0x%08x"
- PRIx64, (uint32_t)t_addr, (uint32_t)value);
+ PRIx64, (uint32_t)t_addr, (uint32_t)value);
dmi_write(target, DM_SBDATA0, value);
}
- /*reset the autoincrement when finished (something weird is happening if this is not done at the end*/
+ /*reset the autoincrement when finished (something weird is happening if this is not done at
+ * the end*/
access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 0);
dmi_write(target, DM_SBCS, access);
@@ -3850,7 +3943,7 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address,
}
static int write_memory_bus_v1(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
RISCV013_INFO(info);
uint32_t sbcs = sb_sbaccess(size);
@@ -3865,7 +3958,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
sb_write_address(target, next_address, true);
while (next_address < end_address) {
LOG_DEBUG("transferring burst starting at address 0x%" TARGET_PRIxADDR,
- next_address);
+ next_address);
struct riscv_batch *batch = riscv_batch_alloc(
target,
@@ -3882,23 +3975,23 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
if (size > 12)
riscv_batch_add_dmi_write(batch, DM_SBDATA3,
- ((uint32_t) p[12]) |
- (((uint32_t) p[13]) << 8) |
- (((uint32_t) p[14]) << 16) |
- (((uint32_t) p[15]) << 24));
+ ((uint32_t) p[12]) |
+ (((uint32_t) p[13]) << 8) |
+ (((uint32_t) p[14]) << 16) |
+ (((uint32_t) p[15]) << 24));
if (size > 8)
riscv_batch_add_dmi_write(batch, DM_SBDATA2,
- ((uint32_t) p[8]) |
- (((uint32_t) p[9]) << 8) |
- (((uint32_t) p[10]) << 16) |
- (((uint32_t) p[11]) << 24));
+ ((uint32_t) p[8]) |
+ (((uint32_t) p[9]) << 8) |
+ (((uint32_t) p[10]) << 16) |
+ (((uint32_t) p[11]) << 24));
if (size > 4)
riscv_batch_add_dmi_write(batch, DM_SBDATA1,
- ((uint32_t) p[4]) |
- (((uint32_t) p[5]) << 8) |
- (((uint32_t) p[6]) << 16) |
- (((uint32_t) p[7]) << 24));
+ ((uint32_t) p[4]) |
+ (((uint32_t) p[5]) << 8) |
+ (((uint32_t) p[6]) << 16) |
+ (((uint32_t) p[7]) << 24));
uint32_t value = p[0];
if (size > 2) {
value |= ((uint32_t) p[2]) << 16;
@@ -3932,8 +4025,9 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
while (get_field(sbcs, DM_SBCS_SBBUSY)) {
if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). "
- "Increase the timeout with riscv set_command_timeout_sec.",
- riscv_command_timeout_sec, sbcs);
+ "Increase the timeout with riscv set_command_timeout_sec.",
+ riscv_command_timeout_sec,
+ sbcs);
return ERROR_FAIL;
}
if (dmi_read(target, &sbcs, DM_SBCS) != ERROR_OK)
@@ -3956,7 +4050,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
if (next_address < address) {
/* This should never happen, probably buggy hardware. */
LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
- " - buggy sbautoincrement in hw?", next_address);
+ " - buggy sbautoincrement in hw?", next_address);
/* Fail the whole operation. */
return ERROR_FAIL;
}
@@ -3971,13 +4065,15 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
* (unless sbautoincrement in the HW is buggy).
*/
target_addr_t sbaddress = sb_read_address(target);
- LOG_DEBUG("System bus access failed with sberror=%u (sbaddress=0x%" TARGET_PRIxADDR ")",
- sberror, sbaddress);
+ LOG_DEBUG(
+ "System bus access failed with sberror=%u (sbaddress=0x%" TARGET_PRIxADDR ")",
+ sberror,
+ sbaddress);
if (sbaddress < address) {
/* This should never happen, probably buggy hardware.
* Make a note to the user not to trust the sbaddress value. */
LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
- " - buggy sbautoincrement in hw?", next_address);
+ " - buggy sbautoincrement in hw?", next_address);
}
/* Clear the sticky error flag */
dmi_write(target, DM_SBCS, DM_SBCS_SBERROR);
@@ -3990,13 +4086,13 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
}
static int write_memory_progbuf(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
RISCV013_INFO(info);
if (riscv_xlen(target) < size * 8) {
LOG_ERROR("XLEN (%d) is too short for %d-bit memory write.",
- riscv_xlen(target), size * 8);
+ riscv_xlen(target), size * 8);
return ERROR_FAIL;
}
@@ -4022,7 +4118,8 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
/* Write the program (store, increment) */
struct riscv_program program;
riscv_program_init(&program, target);
- if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
+ if (riscv_enable_virtual &&
+ has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
riscv_program_csrrsi(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
switch (size) {
@@ -4044,7 +4141,8 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
goto error;
}
- if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
+ if (riscv_enable_virtual &&
+ has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
riscv_program_csrrci(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
riscv_program_addi(&program, GDB_REGNO_S0, GDB_REGNO_S0, size);
@@ -4059,7 +4157,7 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
LOG_DEBUG("writing until final address 0x%016" PRIx64, fin_addr);
while (cur_addr < fin_addr) {
LOG_DEBUG("transferring burst starting at address 0x%016" PRIx64,
- cur_addr);
+ cur_addr);
struct riscv_batch *batch = riscv_batch_alloc(
target,
@@ -4106,12 +4204,12 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
}
/* Turn on autoexec */
- if(!wchwlink)
- { dmi_write(target, DM_ABSTRACTAUTO,
- 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
+ if (!wchwlink) {
+ dmi_write(target, DM_ABSTRACTAUTO,
+ 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
setup_needed = false;
- }
+ }
} else {
if (size > 4)
riscv_batch_add_dmi_write(batch, DM_DATA1, value >> 32);
@@ -4140,9 +4238,9 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK)
return ERROR_FAIL;
info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR);
- if (info->cmderr == CMDERR_NONE && !dmi_busy_encountered) {
+ if (info->cmderr == CMDERR_NONE && !dmi_busy_encountered)
LOG_DEBUG("successful (partial?) memory write");
- } else if (info->cmderr == CMDERR_BUSY || dmi_busy_encountered) {
+ else if (info->cmderr == CMDERR_BUSY || dmi_busy_encountered) {
if (info->cmderr == CMDERR_BUSY)
LOG_DEBUG("Memory write resulted in abstract command busy response.");
else if (dmi_busy_encountered)
@@ -4156,7 +4254,8 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
goto error;
setup_needed = true;
} else {
- LOG_ERROR("error when writing memory, abstractcs=0x%08lx", (long)abstractcs);
+ LOG_ERROR("error when writing memory, abstractcs=0x%08lx",
+ (long)abstractcs);
riscv013_clear_abstract_error(target);
result = ERROR_FAIL;
goto error;
@@ -4178,131 +4277,169 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
}
static int write_memory(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16) {
LOG_ERROR("BUG: Unsupported size for memory write: %d", size);
return ERROR_FAIL;
}
- if(address < 0x20000000)
- {
- if(riscvchip==0x03){
- uint64_t actual_value;
- uint8_t txbuffer[4];
- uint32_t length;
- if((address >= ramaddr)){
- LOG_ERROR("THIS ADDRESSS IS NOT ACCESSIBLE");
- server_quit();
- return ERROR_FAIL;
- }
- target_addr_t flashaddress=address;
- if(address < ramaddr)
- {
- if((size*count)==4){
- if(address%4==0){
- read_memory_progbuf_one(target, address, 4, (uint8_t*)&actual_value );
- write_memory_progbuf(target, address, 4, 1, buffer);
- }else{
- address=address-2;
- read_memory_progbuf_one(target, address, 4, (uint8_t*)&actual_value );
- txbuffer[0]= ((uint32_t)actual_value)&0x000000ff;
- txbuffer[1]= (((uint32_t)actual_value)&0x0000ff00)>>8;
- txbuffer[2]= *buffer;
- txbuffer[3]= *(buffer+1);
- write_memory_progbuf(target, address, 4, 1, &txbuffer);
- address=address+2;
- read_memory_progbuf_one(target, address, 4, (uint8_t*)&actual_value );
- txbuffer[0]= *(buffer+2);
- txbuffer[1]= *(buffer+3);
- txbuffer[2]= (((uint32_t)actual_value)&0x00ffffff)>>16;
- txbuffer[3]=((uint32_t)actual_value)>>24;
- write_memory_progbuf(target, address, 4, 1, &txbuffer);
- }
- }else{
- if((size*count)!=2){
-
- }else{
- read_memory_progbuf_one(target, 0x0000, 4, (uint8_t*)&actual_value );
- if(address%4==0){
- read_memory_progbuf_one(target, address, 4, (uint8_t*)&actual_value );
- txbuffer[0]= *buffer;
- txbuffer[1]= *(buffer+1);
- txbuffer[2]= (((uint32_t)actual_value)&0x00ffffff)>>16;
- txbuffer[3]=((uint32_t)actual_value)>>24;
- write_memory_progbuf(target, address, 4, 1, &txbuffer);
- }else{
- address=address-2;
- read_memory_progbuf_one(target, address, 4, (uint8_t*)&actual_value );
- txbuffer[0]= ((uint32_t)actual_value)&0x000000ff;
- txbuffer[1]= (((uint32_t)actual_value)&0x0000ff00)>>8;
- txbuffer[2]= *buffer;
- txbuffer[3]= *(buffer+1);
- write_memory_progbuf(target, address, 4, 1, &txbuffer);
- }
- }
+ if (address < 0x20000000) {
+ if (riscvchip == 0x03) {
+ uint64_t actual_value;
+ uint8_t txbuffer[4];
+ if ((address >= ramaddr)) {
+ LOG_ERROR("THIS ADDRESSS IS NOT ACCESSIBLE");
+ server_quit();
+ return ERROR_FAIL;
+ }
+ /*target_addr_t flashaddress=address; */
+ if (address < ramaddr) {
+ if ((size*count) == 4) {
+ if (address%4 == 0) {
+ read_memory_progbuf_one(target, address, 4,
+ (uint8_t *)&actual_value);
+ write_memory_progbuf(target, address, 4, 1, buffer);
+ } else {
+ address= address-2;
+ read_memory_progbuf_one(target, address, 4,
+ (uint8_t *)&actual_value);
+ txbuffer[0] = ((uint32_t)actual_value)&0x000000ff;
+ txbuffer[1] = (((uint32_t)actual_value)&0x0000ff00)>>
+ 8;
+ txbuffer[2] = *buffer;
+ txbuffer[3] = *(buffer+1);
+ write_memory_progbuf(target, address, 4, 1,
+ (uint8_t *)&txbuffer);
+ address= address+2;
+ read_memory_progbuf_one(target, address, 4,
+ (uint8_t *)&actual_value);
+ txbuffer[0] = *(buffer+2);
+ txbuffer[1] = *(buffer+3);
+ txbuffer[2] = (((uint32_t)actual_value)&0x00ffffff)>>
+ 16;
+ txbuffer[3] = ((uint32_t)actual_value)>>24;
+ write_memory_progbuf(target, address, 4, 1,
+ (uint8_t *)&txbuffer);
+ }
+ } else {
+ if ((size*count) != 2) {
+
+ } else {
+ read_memory_progbuf_one(target, 0x0000, 4,
+ (uint8_t *)&actual_value);
+ if (address%4 == 0) {
+ read_memory_progbuf_one(target,
+ address,
+ 4,
+ (uint8_t *)&actual_value);
+ txbuffer[0] = *buffer;
+ txbuffer[1] = *(buffer+1);
+ txbuffer[2] =
+ (((uint32_t)actual_value)&
+ 0x00ffffff)>>16;
+ txbuffer[3] = ((uint32_t)actual_value)>>24;
+ write_memory_progbuf(target,
+ address,
+ 4,
+ 1,
+ (uint8_t *)&txbuffer);
+ } else {
+ address= address-2;
+ read_memory_progbuf_one(target,
+ address,
+ 4,
+ (uint8_t *)&actual_value);
+ txbuffer[0] = ((uint32_t)actual_value)&
+ 0x000000ff;
+ txbuffer[1] =
+ (((uint32_t)actual_value)&
+ 0x0000ff00)>>8;
+ txbuffer[2] = *buffer;
+ txbuffer[3] = *(buffer+1);
+ write_memory_progbuf(target,
+ address,
+ 4,
+ 1,
+ (uint8_t *)&txbuffer);
+ }
+ }
}
}
-
- //write_flash_data(target, flashaddress, size, count, buffer);
- }
- if((riscvchip==0x01)||(riscvchip==0x02)||(riscvchip==0x06)||(riscvchip==0x05))
- {
- write_flash_data(target, address, size, count, buffer);
+
+ /*write_flash_data(target, flashaddress, size, count, buffer); */
}
+ if ((riscvchip == 0x01) || (riscvchip == 0x02) || (riscvchip == 0x06) ||
+ (riscvchip == 0x05))
+ write_flash_data(target, address, size, count, buffer);
return ERROR_OK;
- }else{
-
- int ret = ERROR_FAIL;
- RISCV_INFO(r);
- RISCV013_INFO(info);
-
- char *progbuf_result = "disabled";
- char *sysbus_result = "disabled";
- char *abstract_result = "disabled";
-
- for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
- int method = r->mem_access_methods[i];
-
- if (method == RISCV_MEM_ACCESS_PROGBUF) {
- if (mem_should_skip_progbuf(target, address, size, false, &progbuf_result))
- continue;
-
- ret = write_memory_progbuf(target, address, size, count, buffer);
-
- if (ret != ERROR_OK)
- progbuf_result = "failed";
- } else if (method == RISCV_MEM_ACCESS_SYSBUS) {
- if (mem_should_skip_sysbus(target, address, size, 0, false, &sysbus_result))
- continue;
-
- if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0)
- ret = write_memory_bus_v0(target, address, size, count, buffer);
- else if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 1)
- ret = write_memory_bus_v1(target, address, size, count, buffer);
-
- if (ret != ERROR_OK)
- sysbus_result = "failed";
- } else if (method == RISCV_MEM_ACCESS_ABSTRACT) {
- if (mem_should_skip_abstract(target, address, size, 0, false, &abstract_result))
- continue;
-
- ret = write_memory_abstract(target, address, size, count, buffer);
+ } else {
- if (ret != ERROR_OK)
- abstract_result = "failed";
- } else if (method == RISCV_MEM_ACCESS_UNSPECIFIED)
- /* No further mem access method to try. */
- break;
+ int ret = ERROR_FAIL;
+ RISCV_INFO(r);
+ RISCV013_INFO(info);
+
+ char *progbuf_result = "disabled";
+ char *sysbus_result = "disabled";
+ char *abstract_result = "disabled";
+
+ for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
+ int method = r->mem_access_methods[i];
+
+ if (method == RISCV_MEM_ACCESS_PROGBUF) {
+ if (mem_should_skip_progbuf(target, address, size, false,
+ &progbuf_result))
+ continue;
+
+ ret = write_memory_progbuf(target, address, size, count, buffer);
+
+ if (ret != ERROR_OK)
+ progbuf_result = "failed";
+ } else if (method == RISCV_MEM_ACCESS_SYSBUS) {
+ if (mem_should_skip_sysbus(target, address, size, 0, false,
+ &sysbus_result))
+ continue;
+
+ if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0)
+ ret = write_memory_bus_v0(target,
+ address,
+ size,
+ count,
+ buffer);
+ else if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 1)
+ ret = write_memory_bus_v1(target,
+ address,
+ size,
+ count,
+ buffer);
+
+ if (ret != ERROR_OK)
+ sysbus_result = "failed";
+ } else if (method == RISCV_MEM_ACCESS_ABSTRACT) {
+ if (mem_should_skip_abstract(target, address, size, 0, false,
+ &abstract_result))
+ continue;
+
+ ret = write_memory_abstract(target, address, size, count, buffer);
+
+ if (ret != ERROR_OK)
+ abstract_result = "failed";
+ } else if (method == RISCV_MEM_ACCESS_UNSPECIFIED)
+ /* No further mem access method to try. */
+ break;
- log_mem_access_result(target, ret == ERROR_OK, method, false);
+ log_mem_access_result(target, ret == ERROR_OK, method, false);
- if (ret == ERROR_OK)
- return ret;
- }
+ if (ret == ERROR_OK)
+ return ret;
+ }
- LOG_ERROR("Target %s: Failed to write memory (addr=0x%" PRIx64 ")", target_name(target), address);
- LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result);
- return ret;
+ LOG_ERROR("Target %s: Failed to write memory (addr=0x%" PRIx64 ")",
+ target_name(target), address);
+ LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s",
+ progbuf_result,
+ sysbus_result,
+ abstract_result);
+ return ret;
}
}
@@ -4332,10 +4469,10 @@ struct target_type riscv013_target = {
/*** 0.13-specific implementations of various RISC-V helper functions. ***/
static int riscv013_get_register(struct target *target,
- riscv_reg_t *value, int rid)
+ riscv_reg_t *value, int rid)
{
LOG_DEBUG("[%s] reading register %s", target_name(target),
- gdb_regno_name(rid));
+ gdb_regno_name(rid));
if (riscv_select_current_hart(target) != ERROR_OK)
return ERROR_FAIL;
@@ -4364,11 +4501,11 @@ static int riscv013_set_register(struct target *target, int rid, uint64_t value)
{
riscv013_select_current_hart(target);
LOG_DEBUG("[%d] writing 0x%" PRIx64 " to register %s",
- target->coreid, value, gdb_regno_name(rid));
+ target->coreid, value, gdb_regno_name(rid));
- if (rid <= GDB_REGNO_XPR31) {
+ if (rid <= GDB_REGNO_XPR31)
return register_write_direct(target, rid, value);
- } else if (rid == GDB_REGNO_PC) {
+ else if (rid == GDB_REGNO_PC) {
LOG_DEBUG("[%d] writing PC to DPC: 0x%" PRIx64, target->coreid, value);
register_write_direct(target, GDB_REGNO_DPC, value);
uint64_t actual_value;
@@ -4376,7 +4513,7 @@ static int riscv013_set_register(struct target *target, int rid, uint64_t value)
LOG_DEBUG("[%d] actual DPC written: 0x%016" PRIx64, target->coreid, actual_value);
if (value != actual_value) {
LOG_ERROR("Written PC (0x%" PRIx64 ") does not match read back "
- "value (0x%" PRIx64 ")", value, actual_value);
+ "value (0x%" PRIx64 ")", value, actual_value);
return ERROR_FAIL;
}
} else if (rid == GDB_REGNO_PRIV) {
@@ -4385,9 +4522,8 @@ static int riscv013_set_register(struct target *target, int rid, uint64_t value)
dcsr = set_field(dcsr, CSR_DCSR_PRV, get_field(value, VIRT_PRIV_PRV));
dcsr = set_field(dcsr, CSR_DCSR_V, get_field(value, VIRT_PRIV_V));
return register_write_direct(target, GDB_REGNO_DCSR, dcsr);
- } else {
+ } else
return register_write_direct(target, rid, value);
- }
return ERROR_OK;
}
@@ -4498,7 +4634,7 @@ static int riscv013_halt_go(struct target *target)
return ERROR_FAIL;
LOG_ERROR("[%s] Unable to halt hart %d. dmcontrol=0x%08x, dmstatus=0x%08x",
- target_name(target), r->current_hartid, dmcontrol, dmstatus);
+ target_name(target), r->current_hartid, dmcontrol, dmstatus);
return ERROR_FAIL;
}
@@ -4589,22 +4725,22 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
switch (get_field(dcsr, CSR_DCSR_CAUSE)) {
- case CSR_DCSR_CAUSE_SWBP:
- return RISCV_HALT_BREAKPOINT;
- case CSR_DCSR_CAUSE_TRIGGER:
- /* We could get here before triggers are enumerated if a trigger was
- * already set when we connected. Force enumeration now, which has the
- * side effect of clearing any triggers we did not set. */
- riscv_enumerate_triggers(target);
- LOG_DEBUG("{%d} halted because of trigger", target->coreid);
- return RISCV_HALT_TRIGGER;
- case CSR_DCSR_CAUSE_STEP:
- return RISCV_HALT_SINGLESTEP;
- case CSR_DCSR_CAUSE_DEBUGINT:
- case CSR_DCSR_CAUSE_HALT:
- return RISCV_HALT_INTERRUPT;
- case CSR_DCSR_CAUSE_GROUP:
- return RISCV_HALT_GROUP;
+ case CSR_DCSR_CAUSE_SWBP:
+ return RISCV_HALT_BREAKPOINT;
+ case CSR_DCSR_CAUSE_TRIGGER:
+ /* We could get here before triggers are enumerated if a trigger was
+ * already set when we connected. Force enumeration now, which has the
+ * side effect of clearing any triggers we did not set. */
+ riscv_enumerate_triggers(target);
+ LOG_DEBUG("{%d} halted because of trigger", target->coreid);
+ return RISCV_HALT_TRIGGER;
+ case CSR_DCSR_CAUSE_STEP:
+ return RISCV_HALT_SINGLESTEP;
+ case CSR_DCSR_CAUSE_DEBUGINT:
+ case CSR_DCSR_CAUSE_HALT:
+ return RISCV_HALT_INTERRUPT;
+ case CSR_DCSR_CAUSE_GROUP:
+ return RISCV_HALT_GROUP;
}
LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
@@ -4614,7 +4750,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data)
{
- if(wchwlink){
+ if (wchwlink) {
if (dmi_write(target, DM_PROGBUF0 + index, data) != ERROR_OK)
return ERROR_FAIL;
}
@@ -4625,9 +4761,8 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins
if (dmi_write(target, DM_PROGBUF0 + index, data) != ERROR_OK)
return ERROR_FAIL;
dm->progbuf_cache[index] = data;
- } else {
+ } else
LOG_DEBUG("cache hit for 0x%" PRIx32 " @%d", data, index);
- }
return ERROR_OK;
}
@@ -4717,8 +4852,8 @@ static uint32_t get_num_sbdata_regs(struct target *target)
}
static int riscv013_test_sba_config_reg(struct target *target,
- target_addr_t legal_address, uint32_t num_words,
- target_addr_t illegal_address, bool run_sbbusyerror_test)
+ target_addr_t legal_address, uint32_t num_words,
+ target_addr_t illegal_address, bool run_sbbusyerror_test)
{
LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13");
@@ -4739,8 +4874,9 @@ static int riscv013_test_sba_config_reg(struct target *target,
}
if (get_field(sbcs, DM_SBCS_SBVERSION) != 1) {
- LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.",
- get_field(sbcs, DM_SBCS_SBVERSION));
+ LOG_ERROR(
+ "System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.",
+ get_field(sbcs, DM_SBCS_SBVERSION));
return ERROR_FAIL;
}
@@ -4759,7 +4895,8 @@ static int riscv013_test_sba_config_reg(struct target *target,
sbcs = set_field(sbcs, DM_SBCS_SBACCESS, sbaccess);
dmi_write(target, DM_SBCS, sbcs);
- uint32_t compare_mask = (sbaccess == 0) ? 0xff : (sbaccess == 1) ? 0xffff : 0xffffffff;
+ uint32_t compare_mask =
+ (sbaccess == 0) ? 0xff : (sbaccess == 1) ? 0xffff : 0xffffffff;
for (uint32_t i = 0; i < num_words; i++) {
uint32_t addr = legal_address + (i << sbaccess);
@@ -4773,9 +4910,13 @@ static int riscv013_test_sba_config_reg(struct target *target,
uint32_t addr = legal_address + (i << sbaccess);
read_memory_sba_simple(target, addr, rd_buf, num_sbdata_regs, sbcs);
for (uint32_t j = 0; j < num_sbdata_regs; j++) {
- if (((test_patterns[j]+i)&compare_mask) != (rd_buf[j]&compare_mask)) {
+ if (((test_patterns[j]+i)&compare_mask) !=
+ (rd_buf[j]&compare_mask)) {
LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x,"
- "expected val = %x, read val = %x", addr, test_patterns[j]+i, rd_buf[j]);
+ "expected val = %x, read val = %x",
+ addr,
+ test_patterns[j]+i,
+ rd_buf[j]);
test_passed = false;
tests_failed++;
}
@@ -4804,7 +4945,9 @@ static int riscv013_test_sba_config_reg(struct target *target,
read_sbcs_nonbusy(target, &sbcs);
curr_addr = sb_read_address(target);
if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) {
- LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x.", sbaccess);
+ LOG_ERROR(
+ "System Bus Access Test 2: Error with address auto-increment, sbaccess = %x.",
+ sbaccess);
test_passed = false;
tests_failed++;
}
@@ -4818,14 +4961,17 @@ static int riscv013_test_sba_config_reg(struct target *target,
uint32_t val;
sbcs = set_field(sbcs, DM_SBCS_SBREADONDATA, 1);
dmi_write(target, DM_SBCS, sbcs);
- dmi_read(target, &val, DM_SBDATA0); /* Dummy read to trigger first system bus read */
+ dmi_read(target, &val, DM_SBDATA0); /* Dummy read to trigger first system bus
+ * read */
curr_addr = legal_address;
for (uint32_t i = 0; i < num_words; i++) {
prev_addr = curr_addr;
read_sbcs_nonbusy(target, &sbcs);
curr_addr = sb_read_address(target);
if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) {
- LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess);
+ LOG_ERROR(
+ "System Bus Access Test 2: Error with address auto-increment, sbaccess = %x",
+ sbaccess);
test_passed = false;
tests_failed++;
}
@@ -4833,7 +4979,9 @@ static int riscv013_test_sba_config_reg(struct target *target,
read_sbcs_nonbusy(target, &sbcs);
if (i != val) {
LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address,"
- "expected val = %x, read val = %x.", i, val);
+ "expected val = %x, read val = %x.",
+ i,
+ val);
test_passed = false;
tests_failed++;
}
@@ -4853,10 +5001,11 @@ static int riscv013_test_sba_config_reg(struct target *target,
if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED.");
else
- LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED, unable to clear to 0.");
- } else {
- LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED, unable to set error code.");
- }
+ LOG_ERROR(
+ "System Bus Access Test 3: Illegal address read test FAILED, unable to clear to 0.");
+ } else
+ LOG_ERROR(
+ "System Bus Access Test 3: Illegal address read test FAILED, unable to set error code.");
/* Test 4: Write to illegal address */
write_memory_sba_simple(target, illegal_address, test_patterns, 1, sbcs_orig);
@@ -4869,20 +5018,23 @@ static int riscv013_test_sba_config_reg(struct target *target,
if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED.");
else {
- LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0.");
+ LOG_ERROR(
+ "System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0.");
tests_failed++;
}
} else {
- LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to set error code.");
+ LOG_ERROR(
+ "System Bus Access Test 4: Illegal address write test FAILED, unable to set error code.");
tests_failed++;
}
/* Test 5: Write with unsupported sbaccess size */
uint32_t sbaccess128 = get_field(sbcs_orig, DM_SBCS_SBACCESS128);
- if (sbaccess128) {
- LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported.");
- } else {
+ if (sbaccess128)
+ LOG_INFO(
+ "System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported.");
+ else {
sbcs = set_field(sbcs_orig, DM_SBCS_SBACCESS, 4);
write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs);
@@ -4893,13 +5045,16 @@ static int riscv013_test_sba_config_reg(struct target *target,
dmi_write(target, DM_SBCS, sbcs);
dmi_read(target, &rd_val, DM_SBCS);
if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
- LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED.");
+ LOG_INFO(
+ "System Bus Access Test 5: SBCS sbaccess error test PASSED.");
else {
- LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0.");
+ LOG_ERROR(
+ "System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0.");
tests_failed++;
}
} else {
- LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to set error code.");
+ LOG_ERROR(
+ "System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to set error code.");
tests_failed++;
}
}
@@ -4915,13 +5070,16 @@ static int riscv013_test_sba_config_reg(struct target *target,
dmi_write(target, DM_SBCS, sbcs);
dmi_read(target, &rd_val, DM_SBCS);
if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
- LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED");
+ LOG_INFO(
+ "System Bus Access Test 6: SBCS address alignment error test PASSED");
else {
- LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0.");
+ LOG_ERROR(
+ "System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0.");
tests_failed++;
}
} else {
- LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to set error code.");
+ LOG_ERROR(
+ "System Bus Access Test 6: SBCS address alignment error test FAILED, unable to set error code.");
tests_failed++;
}
@@ -4945,11 +5103,13 @@ static int riscv013_test_sba_config_reg(struct target *target,
if (get_field(rd_val, DM_SBCS_SBBUSYERROR) == 0)
LOG_INFO("System Bus Access Test 7: SBCS sbbusyerror test PASSED.");
else {
- LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0.");
+ LOG_ERROR(
+ "System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0.");
tests_failed++;
}
} else {
- LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to set error code.");
+ LOG_ERROR(
+ "System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to set error code.");
tests_failed++;
}
}
@@ -4965,7 +5125,7 @@ static int riscv013_test_sba_config_reg(struct target *target,
}
void write_memory_sba_simple(struct target *target, target_addr_t addr,
- uint32_t *write_data, uint32_t write_size, uint32_t sbcs)
+ uint32_t *write_data, uint32_t write_size, uint32_t sbcs)
{
RISCV013_INFO(info);
@@ -4995,7 +5155,7 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr,
}
void read_memory_sba_simple(struct target *target, target_addr_t addr,
- uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs)
+ uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs)
{
RISCV013_INFO(info);
@@ -5037,32 +5197,30 @@ static int maybe_execute_fence_i(struct target *target)
return execute_fence(target);
return ERROR_OK;
}
+
int wlink_cleancache(struct target *target)
{
- uint64_t old_dpc_value,new_dpc_value,t6_new,t6_old;
- uint32_t dmcontrol;
- RISCV013_INFO(info);
+ uint64_t t6_old;
+ struct riscv_program program;
+ register_read_direct(target, &t6_old, GDB_REGNO_T6);
+ register_write_direct(target, GDB_REGNO_T6, 4);
+ riscv_program_init(&program, target);
+ riscv_program_insert(&program, 0x000f8067);
+ int result = riscv_program_exec(&program, target);
+ (void) result;
+ usleep(1000);
+ register_write_direct(target, GDB_REGNO_T6, t6_old);
- {
- struct riscv_program program;
- register_read_direct(target, &t6_old, GDB_REGNO_T6);
- register_write_direct(target, GDB_REGNO_T6, 4);
- riscv_program_init(&program, target);
- riscv_program_insert(&program, 0x000f8067);
- int result = riscv_program_exec(&program, target);
- usleep(1000);
- register_write_direct(target, GDB_REGNO_T6, t6_old);
- }
return ERROR_OK;
}
+
/* Helper Functions. */
static int riscv013_on_step_or_resume(struct target *target, bool step)
{
if (maybe_execute_fence_i(target) != ERROR_OK)
return ERROR_FAIL;
- if((riscvchip==0x01)){
+ if (riscvchip == 0x01)
wlink_cleancache(target);
- }
/* We want to twiddle some bits in the debug CSR so debugging works. */
riscv_reg_t dcsr;
int result = register_read_direct(target, &dcsr, GDB_REGNO_DCSR);
@@ -5080,10 +5238,10 @@ static int riscv013_on_step_or_resume(struct target *target, bool step)
}
static int riscv013_step_or_resume_current_hart(struct target *target,
- bool step, bool use_hasel)
+ bool step, bool use_hasel)
{
RISCV_INFO(r);
-
+
LOG_DEBUG("resuming hart %d (for step?=%d)", r->current_hartid, step);
if (!riscv_is_halted(target)) {
LOG_ERROR("Hart %d is not halted!", r->current_hartid);
@@ -5092,19 +5250,19 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
if (riscv_flush_registers(target) != ERROR_OK)
return ERROR_FAIL;
-
-
+
+
/* Issue the resume command, and then wait for the current hart to resume. */
uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_RESUMEREQ;
if (use_hasel)
dmcontrol |= DM_DMCONTROL_HASEL;
dmcontrol = set_hartsel(dmcontrol, r->current_hartid);
dmi_write(target, DM_DMCONTROL, dmcontrol);
-
-
+
+
dmcontrol = set_field(dmcontrol, DM_DMCONTROL_HASEL, 0);
dmcontrol = set_field(dmcontrol, DM_DMCONTROL_RESUMEREQ, 0);
-
+
uint32_t dmstatus;
for (size_t i = 0; i < 256; ++i) {
usleep(10);
@@ -5116,7 +5274,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
continue;
dmi_write(target, DM_DMCONTROL, dmcontrol);
-
+
return ERROR_OK;
}
@@ -5147,10 +5305,10 @@ void riscv013_clear_abstract_error(struct target *target)
if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("abstractcs.busy is not going low after %d seconds "
- "(abstractcs=0x%x). The target is either really slow or "
- "broken. You could increase the timeout with riscv "
- "set_command_timeout_sec.",
- riscv_command_timeout_sec, abstractcs);
+ "(abstractcs=0x%x). The target is either really slow or "
+ "broken. You could increase the timeout with riscv "
+ "set_command_timeout_sec.",
+ riscv_command_timeout_sec, abstractcs);
break;
}
}
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 4bf30e073..bf2d40eb2 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -27,37 +27,38 @@
extern bool wchwlink;
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
-#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+#define set_field(reg, mask, \
+ val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
/* Constants for legacy SiFive hardware breakpoints. */
-#define CSR_BPCONTROL_X (1<<0)
-#define CSR_BPCONTROL_W (1<<1)
-#define CSR_BPCONTROL_R (1<<2)
-#define CSR_BPCONTROL_U (1<<3)
-#define CSR_BPCONTROL_S (1<<4)
-#define CSR_BPCONTROL_H (1<<5)
-#define CSR_BPCONTROL_M (1<<6)
-#define CSR_BPCONTROL_BPMATCH (0xf<<7)
-#define CSR_BPCONTROL_BPACTION (0xff<<11)
+#define CSR_BPCONTROL_X (1<<0)
+#define CSR_BPCONTROL_W (1<<1)
+#define CSR_BPCONTROL_R (1<<2)
+#define CSR_BPCONTROL_U (1<<3)
+#define CSR_BPCONTROL_S (1<<4)
+#define CSR_BPCONTROL_H (1<<5)
+#define CSR_BPCONTROL_M (1<<6)
+#define CSR_BPCONTROL_BPMATCH (0xf<<7)
+#define CSR_BPCONTROL_BPACTION (0xff<<11)
#define DEBUG_ROM_START 0x800
-#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
-#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
+#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
+#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
#define DEBUG_RAM_START 0x400
-#define SETHALTNOT 0x10c
+#define SETHALTNOT 0x10c
/*** JTAG registers. ***/
-#define DTMCONTROL 0x10
-#define DTMCONTROL_DBUS_RESET (1<<16)
-#define DTMCONTROL_IDLE (7<<10)
-#define DTMCONTROL_ADDRBITS (0xf<<4)
-#define DTMCONTROL_VERSION (0xf)
+#define DTMCONTROL 0x10
+#define DTMCONTROL_DBUS_RESET (1<<16)
+#define DTMCONTROL_IDLE (7<<10)
+#define DTMCONTROL_ADDRBITS (0xf<<4)
+#define DTMCONTROL_VERSION (0xf)
-#define DBUS 0x11
-#define DBUS_OP_START 0
-#define DBUS_OP_SIZE 2
+#define DBUS 0x11
+#define DBUS_OP_START 0
+#define DBUS_OP_SIZE 2
typedef enum {
DBUS_OP_NOP = 0,
DBUS_OP_READ = 1,
@@ -68,9 +69,9 @@ typedef enum {
DBUS_STATUS_FAILED = 2,
DBUS_STATUS_BUSY = 3
} dbus_status_t;
-#define DBUS_DATA_START 2
-#define DBUS_DATA_SIZE 34
-#define DBUS_ADDRESS_START 36
+#define DBUS_DATA_START 2
+#define DBUS_DATA_SIZE 34
+#define DBUS_ADDRESS_START 36
typedef enum slot {
SLOT0,
@@ -80,37 +81,37 @@ typedef enum slot {
/*** Debug Bus registers. ***/
-#define DMCONTROL 0x10
-#define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
-#define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
-#define DMCONTROL_BUSERROR (7<<19)
-#define DMCONTROL_SERIAL (3<<16)
-#define DMCONTROL_AUTOINCREMENT (1<<15)
-#define DMCONTROL_ACCESS (7<<12)
-#define DMCONTROL_HARTID (0x3ff<<2)
-#define DMCONTROL_NDRESET (1<<1)
-#define DMCONTROL_FULLRESET 1
-
-#define DMINFO 0x11
-#define DMINFO_ABUSSIZE (0x7fU<<25)
-#define DMINFO_SERIALCOUNT (0xf<<21)
-#define DMINFO_ACCESS128 (1<<20)
-#define DMINFO_ACCESS64 (1<<19)
-#define DMINFO_ACCESS32 (1<<18)
-#define DMINFO_ACCESS16 (1<<17)
-#define DMINFO_ACCESS8 (1<<16)
-#define DMINFO_DRAMSIZE (0x3f<<10)
-#define DMINFO_AUTHENTICATED (1<<5)
-#define DMINFO_AUTHBUSY (1<<4)
-#define DMINFO_AUTHTYPE (3<<2)
-#define DMINFO_VERSION 3
+#define DMCONTROL 0x10
+#define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
+#define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
+#define DMCONTROL_BUSERROR (7<<19)
+#define DMCONTROL_SERIAL (3<<16)
+#define DMCONTROL_AUTOINCREMENT (1<<15)
+#define DMCONTROL_ACCESS (7<<12)
+#define DMCONTROL_HARTID (0x3ff<<2)
+#define DMCONTROL_NDRESET (1<<1)
+#define DMCONTROL_FULLRESET 1
+
+#define DMINFO 0x11
+#define DMINFO_ABUSSIZE (0x7fU<<25)
+#define DMINFO_SERIALCOUNT (0xf<<21)
+#define DMINFO_ACCESS128 (1<<20)
+#define DMINFO_ACCESS64 (1<<19)
+#define DMINFO_ACCESS32 (1<<18)
+#define DMINFO_ACCESS16 (1<<17)
+#define DMINFO_ACCESS8 (1<<16)
+#define DMINFO_DRAMSIZE (0x3f<<10)
+#define DMINFO_AUTHENTICATED (1<<5)
+#define DMINFO_AUTHBUSY (1<<4)
+#define DMINFO_AUTHTYPE (3<<2)
+#define DMINFO_VERSION 3
/*** Info about the core being debugged. ***/
-#define DBUS_ADDRESS_UNKNOWN 0xffff
+#define DBUS_ADDRESS_UNKNOWN 0xffff
-#define MAX_HWBPS 16
-#define DRAM_CACHE_SIZE 16
+#define MAX_HWBPS 16
+#define DRAM_CACHE_SIZE 16
uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
struct scan_field select_dtmcontrol = {
@@ -129,7 +130,7 @@ struct scan_field select_idcode = {
};
bscan_tunnel_type_t bscan_tunnel_type;
-int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
+int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
static const uint8_t bscan_zero[4] = {0};
static const uint8_t bscan_one[4] = {1};
@@ -141,57 +142,59 @@ struct scan_field select_user4 = {
};
-uint8_t bscan_tunneled_ir_width[4] = {5}; /* overridden by assignment in riscv_init_target */
+uint8_t bscan_tunneled_ir_width[4] = {5}; /* overridden by assignment in riscv_init_target */
struct scan_field _bscan_tunnel_data_register_select_dmi[] = {
- {
- .num_bits = 3,
- .out_value = bscan_zero,
- .in_value = NULL,
- },
- {
- .num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
- .out_value = ir_dbus,
- .in_value = NULL,
- },
- {
- .num_bits = 7,
- .out_value = bscan_tunneled_ir_width,
- .in_value = NULL,
- },
- {
- .num_bits = 1,
- .out_value = bscan_zero,
- .in_value = NULL,
- }
+ {
+ .num_bits = 3,
+ .out_value = bscan_zero,
+ .in_value = NULL,
+ },
+ {
+ .num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
+ .out_value = ir_dbus,
+ .in_value = NULL,
+ },
+ {
+ .num_bits = 7,
+ .out_value = bscan_tunneled_ir_width,
+ .in_value = NULL,
+ },
+ {
+ .num_bits = 1,
+ .out_value = bscan_zero,
+ .in_value = NULL,
+ }
};
struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
- {
- .num_bits = 1,
- .out_value = bscan_zero,
- .in_value = NULL,
- },
- {
- .num_bits = 7,
- .out_value = bscan_tunneled_ir_width,
- .in_value = NULL,
- },
- {
- .num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
- .out_value = ir_dbus,
- .in_value = NULL,
- },
- {
- .num_bits = 3,
- .out_value = bscan_zero,
- .in_value = NULL,
- }
+ {
+ .num_bits = 1,
+ .out_value = bscan_zero,
+ .in_value = NULL,
+ },
+ {
+ .num_bits = 7,
+ .out_value = bscan_tunneled_ir_width,
+ .in_value = NULL,
+ },
+ {
+ .num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
+ .out_value = ir_dbus,
+ .in_value = NULL,
+ },
+ {
+ .num_bits = 3,
+ .out_value = bscan_zero,
+ .in_value = NULL,
+ }
};
struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi;
-uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi);
+uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(
+ _bscan_tunnel_nested_tap_select_dmi);
struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi;
-uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi);
+uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(
+ _bscan_tunnel_data_register_select_dmi);
struct trigger {
uint64_t address;
@@ -282,10 +285,10 @@ void select_dmi_via_bscan(struct target *target)
jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
jtag_add_dr_scan(target->tap, bscan_tunnel_data_register_select_dmi_num_fields,
- bscan_tunnel_data_register_select_dmi, TAP_IDLE);
- else /* BSCAN_TUNNEL_NESTED_TAP */
+ bscan_tunnel_data_register_select_dmi, TAP_IDLE);
+ else /* BSCAN_TUNNEL_NESTED_TAP */
jtag_add_dr_scan(target->tap, bscan_tunnel_nested_tap_select_dmi_num_fields,
- bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
+ bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
}
uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
@@ -401,9 +404,8 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
}
uint32_t in = buf_get_u32(field.in_value, 0, 32);
- if(wchwlink){
- buf_set_u32(&in, 0, 32, 0x00000071);
- }
+ if (wchwlink)
+ buf_set_u32((uint8_t *)&in, 0, 32, 0x00000071);
LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
return in;
@@ -425,7 +427,7 @@ static struct target_type *get_target_type(struct target *target)
return &riscv013_target;
default:
LOG_ERROR("[%s] Unsupported DTM version: %d",
- target_name(target), info->dtm_version);
+ target_name(target), info->dtm_version);
return NULL;
}
}
@@ -443,7 +445,7 @@ static int riscv_create_target(struct target *target, Jim_Interp *interp)
}
static int riscv_init_target(struct command_context *cmd_ctx,
- struct target *target)
+ struct target *target)
{
LOG_DEBUG("riscv_init_target()");
RISCV_INFO(info);
@@ -464,7 +466,7 @@ static int riscv_init_target(struct command_context *cmd_ctx,
bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
bscan_tunnel_data_register_select_dmi[1].num_bits = bscan_tunnel_ir_width;
- else /* BSCAN_TUNNEL_NESTED_TAP */
+ else /* BSCAN_TUNNEL_NESTED_TAP */
bscan_tunnel_nested_tap_select_dmi[2].num_bits = bscan_tunnel_ir_width;
}
@@ -500,7 +502,8 @@ static void riscv_deinit_target(struct target *target)
struct target_type *tt = get_target_type(target);
if (riscv_flush_registers(target) != ERROR_OK)
- LOG_ERROR("[%s] Failed to flush registers. Ignoring this error.", target_name(target));
+ LOG_ERROR("[%s] Failed to flush registers. Ignoring this error.",
+ target_name(target));
if (tt && info->version_specific)
tt->deinit_target(target);
@@ -525,7 +528,7 @@ static void riscv_deinit_target(struct target *target)
}
static void trigger_from_breakpoint(struct trigger *trigger,
- const struct breakpoint *breakpoint)
+ const struct breakpoint *breakpoint)
{
trigger->address = breakpoint->address;
trigger->length = breakpoint->length;
@@ -538,7 +541,7 @@ static void trigger_from_breakpoint(struct trigger *trigger,
}
static int maybe_add_trigger_t1(struct target *target,
- struct trigger *trigger, uint64_t tdata1)
+ struct trigger *trigger, uint64_t tdata1)
{
RISCV_INFO(r);
@@ -567,8 +570,8 @@ static int maybe_add_trigger_t1(struct target *target,
tdata1 = set_field(tdata1, bpcontrol_h,
!!(r->misa & BIT('H' - 'A')));
tdata1 |= bpcontrol_m;
- tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
- tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
+ tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
+ tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
@@ -579,8 +582,8 @@ static int maybe_add_trigger_t1(struct target *target,
if (tdata1 != tdata1_rb) {
LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
- PRIx64 " to tdata1 it contains 0x%" PRIx64,
- tdata1, tdata1_rb);
+ PRIx64 " to tdata1 it contains 0x%" PRIx64,
+ tdata1, tdata1_rb);
riscv_set_register(target, GDB_REGNO_TDATA1, 0);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -589,9 +592,9 @@ static int maybe_add_trigger_t1(struct target *target,
return ERROR_OK;
}
-extern unsigned char riscvchip;
+extern unsigned char riscvchip;
static int maybe_add_trigger_t2(struct target *target,
- struct trigger *trigger, uint64_t tdata1)
+ struct trigger *trigger, uint64_t tdata1)
{
RISCV_INFO(r);
@@ -602,7 +605,7 @@ static int maybe_add_trigger_t2(struct target *target,
}
/* address/data match trigger */
- if(riscvchip==0)
+ if (riscvchip == 0)
tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
tdata1 = set_field(tdata1, MCONTROL_ACTION,
MCONTROL_ACTION_DEBUG_MODE);
@@ -630,8 +633,8 @@ static int maybe_add_trigger_t2(struct target *target,
if (tdata1 != tdata1_rb) {
LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
- PRIx64 " to tdata1 it contains 0x%" PRIx64,
- tdata1, tdata1_rb);
+ PRIx64 " to tdata1 it contains 0x%" PRIx64,
+ tdata1, tdata1_rb);
riscv_set_register(target, GDB_REGNO_TDATA1, 0);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -642,7 +645,7 @@ static int maybe_add_trigger_t2(struct target *target,
}
static int maybe_add_trigger_t6(struct target *target,
- struct trigger *trigger, uint64_t tdata1)
+ struct trigger *trigger, uint64_t tdata1)
{
RISCV_INFO(r);
@@ -682,8 +685,8 @@ static int maybe_add_trigger_t6(struct target *target,
if (tdata1 != tdata1_rb) {
LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
- PRIx64 " to tdata1 it contains 0x%" PRIx64,
- tdata1, tdata1_rb);
+ PRIx64 " to tdata1 it contains 0x%" PRIx64,
+ tdata1, tdata1_rb);
riscv_set_register(target, GDB_REGNO_TDATA1, 0);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -736,7 +739,7 @@ static int add_trigger(struct target *target, struct trigger *trigger)
continue;
LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
- i, type, trigger->unique_id);
+ i, type, trigger->unique_id);
r->trigger_unique_id[i] = trigger->unique_id;
break;
}
@@ -756,26 +759,29 @@ static int add_trigger(struct target *target, struct trigger *trigger)
* Utilize read-modify-write, if needed.
* */
static int write_by_given_size(struct target *target, target_addr_t address,
- uint32_t size, uint8_t *buffer, uint32_t access_size)
+ uint32_t size, uint8_t *buffer, uint32_t access_size)
{
assert(size == 1 || size == 2 || size == 4 || size == 8);
assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
if (access_size <= size && address % access_size == 0)
/* Can do the memory access directly without a helper buffer. */
- return target_write_memory(target, address, access_size, size / access_size, buffer);
+ return target_write_memory(target, address, access_size, size / access_size,
+ buffer);
unsigned int offset_head = address % access_size;
unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
uint8_t helper_buf[n_blocks * access_size];
/* Read from memory */
- if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
+ if (target_read_memory(target, address - offset_head, access_size, n_blocks,
+ helper_buf) != ERROR_OK)
return ERROR_FAIL;
/* Modify and write back */
memcpy(helper_buf + offset_head, buffer, size);
- return target_write_memory(target, address - offset_head, access_size, n_blocks, helper_buf);
+ return target_write_memory(target, address - offset_head, access_size, n_blocks,
+ helper_buf);
}
/**
@@ -797,7 +803,8 @@ static int read_by_given_size(struct target *target, target_addr_t address,
uint8_t helper_buf[n_blocks * access_size];
/* Read from memory */
- if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
+ if (target_read_memory(target, address - offset_head, access_size, n_blocks,
+ helper_buf) != ERROR_OK)
return ERROR_FAIL;
/* Pick the requested portion from the buffer */
@@ -809,7 +816,10 @@ static int read_by_given_size(struct target *target, target_addr_t address,
* Write one memory item using any memory access size that will work.
* Utilize read-modify-write, if needed.
* */
-int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
+int riscv_write_by_any_size(struct target *target,
+ target_addr_t address,
+ uint32_t size,
+ uint8_t *buffer)
{
assert(size == 1 || size == 2 || size == 4 || size == 8);
@@ -841,7 +851,10 @@ int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32
* Read one memory item using any memory access size that will work.
* Read larger section of memory and pick out the required portion, if needed.
* */
-int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
+int riscv_read_by_any_size(struct target *target,
+ target_addr_t address,
+ uint32_t size,
+ uint8_t *buffer)
{
assert(size == 1 || size == 2 || size == 4 || size == 8);
@@ -881,24 +894,30 @@ int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
}
if (0 != (breakpoint->address % 2)) {
- LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
+ LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR,
+ breakpoint->address);
return ERROR_FAIL;
}
/* Read the original instruction. */
if (riscv_read_by_any_size(
- target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
+ target, breakpoint->address, breakpoint->length,
+ breakpoint->orig_instr) != ERROR_OK) {
LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
- breakpoint->address);
+ breakpoint->address);
return ERROR_FAIL;
}
uint8_t buff[4] = { 0 };
- buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
+ buf_set_u32(buff,
+ 0,
+ breakpoint->length * CHAR_BIT,
+ breakpoint->length == 4 ? ebreak() : ebreak_c());
/* Write the ebreak instruction. */
- if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) {
+ if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length,
+ buff) != ERROR_OK) {
LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
- TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
+ TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
return ERROR_FAIL;
}
} else if (breakpoint->type == BKPT_HARD) {
@@ -930,11 +949,11 @@ static int remove_trigger(struct target *target, struct trigger *trigger)
}
if (i >= r->trigger_count) {
LOG_ERROR("Couldn't find the hardware resources used by hardware "
- "trigger.");
+ "trigger.");
return ERROR_FAIL;
}
LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
- trigger->unique_id);
+ trigger->unique_id);
riscv_reg_t tselect;
int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
@@ -949,14 +968,15 @@ static int remove_trigger(struct target *target, struct trigger *trigger)
}
int riscv_remove_breakpoint(struct target *target,
- struct breakpoint *breakpoint)
+ struct breakpoint *breakpoint)
{
if (breakpoint->type == BKPT_SOFT) {
/* Write the original instruction. */
if (riscv_write_by_any_size(
- target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
+ target, breakpoint->address, breakpoint->length,
+ breakpoint->orig_instr) != ERROR_OK) {
LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
- "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
+ "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
return ERROR_FAIL;
}
@@ -978,7 +998,7 @@ int riscv_remove_breakpoint(struct target *target,
}
static void trigger_from_watchpoint(struct trigger *trigger,
- const struct watchpoint *watchpoint)
+ const struct watchpoint *watchpoint)
{
trigger->address = watchpoint->address;
trigger->length = watchpoint->length;
@@ -1005,7 +1025,7 @@ int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
}
int riscv_remove_watchpoint(struct target *target,
- struct watchpoint *watchpoint)
+ struct watchpoint *watchpoint)
{
LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
@@ -1056,8 +1076,8 @@ int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoi
}
LOG_DEBUG("Full instruction is %x", instruction);
- /* find out which memory address is accessed by the instruction at dpc */
- /* opcode is first 7 bits of the instruction */
+ /* find out which memory address is accessed by the instruction at dpc
+ * opcode is first 7 bits of the instruction*/
uint8_t opcode = instruction & 0x7F;
uint32_t rs1;
int16_t imm;
@@ -1104,14 +1124,14 @@ int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoi
static int oldriscv_step(struct target *target, int current, uint32_t address,
- int handle_breakpoints)
+ int handle_breakpoints)
{
struct target_type *tt = get_target_type(target);
return tt->step(target, current, address, handle_breakpoints);
}
static int old_or_new_riscv_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+ target_addr_t address, int handle_breakpoints)
{
RISCV_INFO(r);
LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
@@ -1182,7 +1202,7 @@ int riscv_flush_registers(struct target *target)
if (reg->valid && reg->dirty) {
uint64_t value = buf_get_u64(reg->value, 0, reg->size);
LOG_DEBUG("[%s] %s is dirty; write back 0x%" PRIx64,
- target_name(target), reg->name, value);
+ target_name(target), reg->name, value);
int result = r->set_register(target, number, value);
if (result != ERROR_OK)
return ERROR_FAIL;
@@ -1226,12 +1246,12 @@ int halt_prep(struct target *target)
RISCV_INFO(r);
LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
- target->debug_reason);
+ target->debug_reason);
if (riscv_select_current_hart(target) != ERROR_OK)
return ERROR_FAIL;
if (riscv_is_halted(target)) {
LOG_DEBUG("[%s] Hart is already halted (debug_reason=%d).",
- target_name(target), target->debug_reason);
+ target_name(target), target->debug_reason);
if (target->debug_reason == DBG_REASON_NOTHALTED) {
enum riscv_halt_reason halt_reason =
riscv_halt_reason(target, r->current_hartid);
@@ -1253,9 +1273,9 @@ int riscv_halt_go_all_harts(struct target *target)
if (riscv_select_current_hart(target) != ERROR_OK)
return ERROR_FAIL;
- if (riscv_is_halted(target)) {
+ if (riscv_is_halted(target))
LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
- } else {
+ else {
if (r->halt_go(target) != ERROR_OK)
return ERROR_FAIL;
@@ -1272,9 +1292,8 @@ int halt_go(struct target *target)
if (!r->is_halted) {
struct target_type *tt = get_target_type(target);
result = tt->halt(target);
- } else {
+ } else
result = riscv_halt_go_all_harts(target);
- }
target->state = TARGET_HALTED;
if (target->debug_reason == DBG_REASON_NOTHALTED)
target->debug_reason = DBG_REASON_DBGRQ;
@@ -1338,12 +1357,11 @@ static int riscv_assert_reset(struct target *target)
LOG_DEBUG("[%d]", target->coreid);
struct target_type *tt = get_target_type(target);
riscv_invalidate_register_cache(target);
- if(wchwlink){
- int ret=riscv_halt(target);
- if(ret == ERROR_OK){
+ if (wchwlink) {
+ int ret = riscv_halt(target);
+ if (ret == ERROR_OK)
return tt->assert_reset(target);
- }
- else{
+ else {
LOG_ERROR("[wch] hart must be halted before reset!");
return ERROR_FAIL;
}
@@ -1421,7 +1439,8 @@ static int enable_triggers(struct target *target, riscv_reg_t *state)
if (state[t] != 0) {
if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
return ERROR_FAIL;
- if (riscv_set_register(target, GDB_REGNO_TDATA1, state[t]) != ERROR_OK)
+ if (riscv_set_register(target, GDB_REGNO_TDATA1,
+ state[t]) != ERROR_OK)
return ERROR_FAIL;
}
}
@@ -1449,7 +1468,7 @@ static int enable_triggers(struct target *target, riscv_reg_t *state)
* Get everything ready to resume.
*/
static int resume_prep(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+ target_addr_t address, int handle_breakpoints, int debug_execution)
{
RISCV_INFO(r);
LOG_DEBUG("[%d]", target->coreid);
@@ -1490,7 +1509,7 @@ static int resume_prep(struct target *target, int current,
* possible.
*/
static int resume_go(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+ target_addr_t address, int handle_breakpoints, int debug_execution)
{
riscv_info_t *r = riscv_info(target);
int result;
@@ -1498,9 +1517,8 @@ static int resume_go(struct target *target, int current,
struct target_type *tt = get_target_type(target);
result = tt->resume(target, current, address, handle_breakpoints,
debug_execution);
- } else {
+ } else
result = riscv_resume_go_all_harts(target);
- }
return result;
}
@@ -1545,12 +1563,12 @@ static void tlist_free(struct target_list *tlist)
* configured. This is used to run algorithms on just one hart.
*/
int riscv_resume(
- struct target *target,
- int current,
- target_addr_t address,
- int handle_breakpoints,
- int debug_execution,
- bool single_hart)
+ struct target *target,
+ int current,
+ target_addr_t address,
+ int handle_breakpoints,
+ int debug_execution,
+ bool single_hart)
{
LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
int result = ERROR_OK;
@@ -1565,7 +1583,7 @@ int riscv_resume(
for (struct target_list *tlist = ordered_tlist; tlist; tlist = tlist->next) {
struct target *t = tlist->target;
if (resume_prep(t, current, address, handle_breakpoints,
- debug_execution) != ERROR_OK)
+ debug_execution) != ERROR_OK)
result = ERROR_FAIL;
}
@@ -1574,7 +1592,7 @@ int riscv_resume(
riscv_info_t *i = riscv_info(t);
if (i->prepped) {
if (resume_go(t, current, address, handle_breakpoints,
- debug_execution) != ERROR_OK)
+ debug_execution) != ERROR_OK)
result = ERROR_FAIL;
}
}
@@ -1590,10 +1608,10 @@ int riscv_resume(
} else {
if (resume_prep(target, current, address, handle_breakpoints,
- debug_execution) != ERROR_OK)
+ debug_execution) != ERROR_OK)
result = ERROR_FAIL;
if (resume_go(target, current, address, handle_breakpoints,
- debug_execution) != ERROR_OK)
+ debug_execution) != ERROR_OK)
result = ERROR_FAIL;
if (resume_finish(target) != ERROR_OK)
return ERROR_FAIL;
@@ -1603,7 +1621,7 @@ int riscv_resume(
}
static int riscv_target_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution)
+ int handle_breakpoints, int debug_execution)
{
return riscv_resume(target, current, address, handle_breakpoints,
debug_execution, false);
@@ -1655,7 +1673,7 @@ static int riscv_mmu(struct target *target, int *enabled)
}
static int riscv_address_translate(struct target *target,
- target_addr_t virtual, target_addr_t *physical)
+ target_addr_t virtual, target_addr_t *physical)
{
RISCV_INFO(r);
riscv_reg_t satp_value;
@@ -1684,11 +1702,11 @@ static int riscv_address_translate(struct target *target,
break;
case SATP_MODE_OFF:
LOG_ERROR("No translation or protection." \
- " (satp: 0x%" PRIx64 ")", satp_value);
+ " (satp: 0x%" PRIx64 ")", satp_value);
return ERROR_FAIL;
default:
LOG_ERROR("The translation mode is not supported." \
- " (satp: 0x%" PRIx64 ")", satp_value);
+ " (satp: 0x%" PRIx64 ")", satp_value);
return ERROR_FAIL;
}
LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
@@ -1698,7 +1716,7 @@ static int riscv_address_translate(struct target *target,
target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
if (masked_msbs != 0 && masked_msbs != mask) {
LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended "
- "for %s mode.", virtual, info->name);
+ "for %s mode.", virtual, info->name);
return ERROR_FAIL;
}
@@ -1709,7 +1727,7 @@ static int riscv_address_translate(struct target *target,
uint64_t vpn = virtual >> info->vpn_shift[i];
vpn &= info->vpn_mask[i];
target_addr_t pte_address = table_address +
- (vpn << info->pte_shift);
+ (vpn << info->pte_shift);
uint8_t buffer[8];
assert(info->pte_shift <= 3);
int retval = r->read_memory(target, pte_address,
@@ -1723,12 +1741,12 @@ static int riscv_address_translate(struct target *target,
pte = buf_get_u64(buffer, 0, 64);
LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
- pte_address, pte);
+ pte_address, pte);
if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
return ERROR_FAIL;
- if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
+ if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
break;
i--;
@@ -1750,12 +1768,12 @@ static int riscv_address_translate(struct target *target,
ppn_value = pte >> info->pte_ppn_shift[i];
ppn_value &= info->pte_ppn_mask[i];
*physical &= ~(((target_addr_t)info->pa_ppn_mask[i]) <<
- info->pa_ppn_shift[i]);
+ info->pa_ppn_shift[i]);
*physical |= (ppn_value << info->pa_ppn_shift[i]);
i++;
}
LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
- *physical);
+ *physical);
return ERROR_OK;
}
@@ -1775,7 +1793,7 @@ static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_
}
static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, uint8_t *buffer)
{
RISCV_INFO(r);
if (riscv_select_current_hart(target) != ERROR_OK)
@@ -1784,7 +1802,7 @@ static int riscv_read_phys_memory(struct target *target, target_addr_t phys_addr
}
static int riscv_read_memory(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, uint8_t *buffer)
{
if (count == 0) {
LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR, address);
@@ -1803,7 +1821,7 @@ static int riscv_read_memory(struct target *target, target_addr_t address,
}
static int riscv_write_phys_memory(struct target *target, target_addr_t phys_address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
if (riscv_select_current_hart(target) != ERROR_OK)
return ERROR_FAIL;
@@ -1812,7 +1830,7 @@ static int riscv_write_phys_memory(struct target *target, target_addr_t phys_add
}
static int riscv_write_memory(struct target *target, target_addr_t address,
- uint32_t size, uint32_t count, const uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
if (count == 0) {
LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR, address);
@@ -1843,12 +1861,12 @@ const char *riscv_get_gdb_arch(struct target *target)
}
static int riscv_get_gdb_reg_list_internal(struct target *target,
- struct reg **reg_list[], int *reg_list_size,
- enum target_register_class reg_class, bool read)
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class, bool read)
{
RISCV_INFO(r);
LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
- target_name(target), r->current_hartid, reg_class, read);
+ target_name(target), r->current_hartid, reg_class, read);
if (!target->reg_cache) {
LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
@@ -1876,13 +1894,13 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
for (int i = 0; i < *reg_list_size; i++) {
assert(!target->reg_cache->reg_list[i].valid ||
- target->reg_cache->reg_list[i].size > 0);
+ target->reg_cache->reg_list[i].size > 0);
(*reg_list)[i] = &target->reg_cache->reg_list[i];
if (read &&
- target->reg_cache->reg_list[i].exist &&
- !target->reg_cache->reg_list[i].valid) {
+ target->reg_cache->reg_list[i].exist &&
+ !target->reg_cache->reg_list[i].valid) {
if (target->reg_cache->reg_list[i].type->get(
- &target->reg_cache->reg_list[i]) != ERROR_OK)
+ &target->reg_cache->reg_list[i]) != ERROR_OK)
return ERROR_FAIL;
}
}
@@ -1891,16 +1909,16 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
}
static int riscv_get_gdb_reg_list_noread(struct target *target,
- struct reg **reg_list[], int *reg_list_size,
- enum target_register_class reg_class)
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class)
{
return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
reg_class, false);
}
static int riscv_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size,
- enum target_register_class reg_class)
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class)
{
return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
reg_class, true);
@@ -1914,9 +1932,9 @@ static int riscv_arch_state(struct target *target)
/* Algorithm must end with a software breakpoint instruction. */
static int riscv_run_algorithm(struct target *target, int num_mem_params,
- struct mem_param *mem_params, int num_reg_params,
- struct reg_param *reg_params, target_addr_t entry_point,
- target_addr_t exit_point, int timeout_ms, void *arch_info)
+ struct mem_param *mem_params, int num_reg_params,
+ struct reg_param *reg_params, target_addr_t entry_point,
+ target_addr_t exit_point, int timeout_ms, void *arch_info)
{
RISCV_INFO(info);
@@ -1940,7 +1958,9 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
uint64_t saved_regs[32];
for (int i = 0; i < num_reg_params; i++) {
LOG_DEBUG("save %s", reg_params[i].reg_name);
- struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
+ struct reg *r = register_get_by_name(target->reg_cache,
+ reg_params[i].reg_name,
+ false);
if (!r) {
LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
return ERROR_FAIL;
@@ -1948,7 +1968,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
if (r->size != reg_params[i].size) {
LOG_ERROR("Register %s is %d bits instead of %d bits.",
- reg_params[i].reg_name, r->size, reg_params[i].size);
+ reg_params[i].reg_name, r->size, reg_params[i].size);
return ERROR_FAIL;
}
@@ -1961,7 +1981,8 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
return ERROR_FAIL;
saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
- if (reg_params[i].direction == PARAM_OUT || reg_params[i].direction == PARAM_IN_OUT) {
+ if (reg_params[i].direction == PARAM_OUT ||
+ reg_params[i].direction == PARAM_IN_OUT) {
if (r->type->set(r, reg_params[i].value) != ERROR_OK)
return ERROR_FAIL;
}
@@ -1984,7 +2005,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus,
- ie_mask, 0));
+ ie_mask, 0));
reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
@@ -2037,7 +2058,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
if (exit_point && final_pc != exit_point) {
LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
- TARGET_PRIxADDR, final_pc, exit_point);
+ TARGET_PRIxADDR, final_pc, exit_point);
return ERROR_FAIL;
}
@@ -2054,8 +2075,10 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction == PARAM_IN ||
- reg_params[i].direction == PARAM_IN_OUT) {
- struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
+ reg_params[i].direction == PARAM_IN_OUT) {
+ struct reg *r = register_get_by_name(target->reg_cache,
+ reg_params[i].reg_name,
+ false);
if (r->type->get(r) != ERROR_OK) {
LOG_ERROR("get(%s) failed", r->name);
return ERROR_FAIL;
@@ -2063,7 +2086,9 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
}
LOG_DEBUG("restore %s", reg_params[i].reg_name);
- struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
+ struct reg *r = register_get_by_name(target->reg_cache,
+ reg_params[i].reg_name,
+ false);
buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
if (r->type->set(r, buf) != ERROR_OK) {
LOG_ERROR("set(%s) failed", r->name);
@@ -2075,8 +2100,8 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
}
static int riscv_checksum_memory(struct target *target,
- target_addr_t address, uint32_t count,
- uint32_t *checksum)
+ target_addr_t address, uint32_t count,
+ uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct reg_param reg_params[2];
@@ -2115,7 +2140,7 @@ static int riscv_checksum_memory(struct target *target,
return retval;
if (crc_algorithm->address + crc_algorithm->size > address &&
- crc_algorithm->address < address + count) {
+ crc_algorithm->address < address + count) {
/* Region to checksum overlaps with the work area we've been assigned.
* Bail. (Would be better to manually checksum what we read there, and
* use the algorithm for the rest.) */
@@ -2127,7 +2152,7 @@ static int riscv_checksum_memory(struct target *target,
crc_code);
if (retval != ERROR_OK) {
LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
- crc_algorithm->address, retval);
+ crc_algorithm->address, retval);
target_free_working_area(target, crc_algorithm);
return retval;
}
@@ -2175,7 +2200,7 @@ static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
return RPH_ERROR;
LOG_DEBUG("[%s] polling hart %d, target->state=%d", target_name(target),
- hartid, target->state);
+ hartid, target->state);
/* If OpenOCD thinks we're running but this hart is halted then it's time
* to raise an event. */
@@ -2216,7 +2241,7 @@ int sample_memory(struct target *target)
int result = ERROR_OK;
if (r->sample_memory) {
result = r->sample_memory(target, &r->sample_buf, &r->sample_config,
- start + TARGET_DEFAULT_POLLING_INTERVAL);
+ start + TARGET_DEFAULT_POLLING_INTERVAL);
if (result != ERROR_NOT_IMPLEMENTED)
goto exit;
}
@@ -2225,15 +2250,17 @@ int sample_memory(struct target *target)
while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) {
for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
if (r->sample_config.bucket[i].enabled &&
- r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) {
+ r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes <
+ r->sample_buf.size) {
assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
r->sample_buf.buf[r->sample_buf.used] = i;
result = riscv_read_phys_memory(
- target, r->sample_config.bucket[i].address,
- r->sample_config.bucket[i].size_bytes, 1,
- r->sample_buf.buf + r->sample_buf.used + 1);
+ target, r->sample_config.bucket[i].address,
+ r->sample_config.bucket[i].size_bytes, 1,
+ r->sample_buf.buf + r->sample_buf.used + 1);
if (result == ERROR_OK)
- r->sample_buf.used += 1 + r->sample_config.bucket[i].size_bytes;
+ r->sample_buf.used += 1 +
+ r->sample_config.bucket[i].size_bytes;
else
goto exit;
}
@@ -2261,58 +2288,58 @@ int riscv_openocd_poll(struct target *target)
unsigned should_resume = 0;
unsigned i = 0;
for (struct target_list *list = target->head; list;
- list = list->next, i++) {
+ list = list->next, i++) {
struct target *t = list->target;
if (!target_was_examined(t))
continue;
riscv_info_t *r = riscv_info(t);
enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
switch (out) {
- case RPH_NO_CHANGE:
- break;
- case RPH_DISCOVERED_RUNNING:
- t->state = TARGET_RUNNING;
- t->debug_reason = DBG_REASON_NOTHALTED;
- break;
- case RPH_DISCOVERED_HALTED:
- halts_discovered++;
- t->state = TARGET_HALTED;
- enum riscv_halt_reason halt_reason =
- riscv_halt_reason(t, r->current_hartid);
- if (set_debug_reason(t, halt_reason) != ERROR_OK)
- return ERROR_FAIL;
-
- if (halt_reason == RISCV_HALT_BREAKPOINT) {
- int retval;
- switch (riscv_semihosting(t, &retval)) {
- case SEMI_NONE:
- case SEMI_WAITING:
- /* This hart should remain halted. */
+ case RPH_NO_CHANGE:
+ break;
+ case RPH_DISCOVERED_RUNNING:
+ t->state = TARGET_RUNNING;
+ t->debug_reason = DBG_REASON_NOTHALTED;
+ break;
+ case RPH_DISCOVERED_HALTED:
+ halts_discovered++;
+ t->state = TARGET_HALTED;
+ enum riscv_halt_reason halt_reason =
+ riscv_halt_reason(t, r->current_hartid);
+ if (set_debug_reason(t, halt_reason) != ERROR_OK)
+ return ERROR_FAIL;
+
+ if (halt_reason == RISCV_HALT_BREAKPOINT) {
+ int retval;
+ switch (riscv_semihosting(t, &retval)) {
+ case SEMI_NONE:
+ case SEMI_WAITING:
+ /* This hart should remain halted.
+ */
+ should_remain_halted++;
+ break;
+ case SEMI_HANDLED:
+ /* This hart should be resumed, along with any other
+ * harts that halted due to haltgroups. */
+ should_resume++;
+ break;
+ case SEMI_ERROR:
+ return retval;
+ }
+ } else if (halt_reason != RISCV_HALT_GROUP)
should_remain_halted++;
- break;
- case SEMI_HANDLED:
- /* This hart should be resumed, along with any other
- * harts that halted due to haltgroups. */
- should_resume++;
- break;
- case SEMI_ERROR:
- return retval;
- }
- } else if (halt_reason != RISCV_HALT_GROUP) {
- should_remain_halted++;
- }
- break;
+ break;
- case RPH_ERROR:
- return ERROR_FAIL;
+ case RPH_ERROR:
+ return ERROR_FAIL;
}
}
LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
- should_remain_halted, should_resume);
+ should_remain_halted, should_resume);
if (should_remain_halted && should_resume) {
LOG_WARNING("%d harts should remain halted, and %d should resume.",
- should_remain_halted, should_resume);
+ should_remain_halted, should_resume);
}
if (should_remain_halted) {
LOG_DEBUG("halt all");
@@ -2324,7 +2351,7 @@ int riscv_openocd_poll(struct target *target)
/* Sample memory if any target is running. */
for (struct target_list *list = target->head; list;
- list = list->next, i++) {
+ list = list->next, i++) {
struct target *t = list->target;
if (t->state == TARGET_RUNNING) {
sample_memory(target);
@@ -2341,9 +2368,8 @@ int riscv_openocd_poll(struct target *target)
if (target->state == TARGET_RUNNING)
sample_memory(target);
return ERROR_OK;
- } else if (out == RPH_ERROR) {
+ } else if (out == RPH_ERROR)
return ERROR_FAIL;
- }
halted_hart = riscv_current_hartid(target);
LOG_DEBUG(" hart %d halted", halted_hart);
@@ -2368,15 +2394,14 @@ int riscv_openocd_poll(struct target *target)
case SEMI_ERROR:
return retval;
}
- } else {
+ } else
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- }
return ERROR_OK;
}
int riscv_openocd_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+ target_addr_t address, int handle_breakpoints)
{
LOG_DEBUG("stepping rtos hart");
@@ -2445,7 +2470,8 @@ COMMAND_HANDLER(riscv_set_prefer_sba)
struct target *target = get_current_target(CMD_CTX);
RISCV_INFO(r);
bool prefer_sba;
- LOG_WARNING("`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.");
+ LOG_WARNING(
+ "`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.");
if (CMD_ARGC != 1) {
LOG_ERROR("Command takes exactly 1 parameter");
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -2486,13 +2512,13 @@ COMMAND_HANDLER(riscv_set_mem_access)
/* Check argument validity */
for (unsigned int i = 0; i < CMD_ARGC; i++) {
- if (strcmp("progbuf", CMD_ARGV[i]) == 0) {
+ if (strcmp("progbuf", CMD_ARGV[i]) == 0)
progbuf_cnt++;
- } else if (strcmp("sysbus", CMD_ARGV[i]) == 0) {
+ else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
sysbus_cnt++;
- } else if (strcmp("abstract", CMD_ARGV[i]) == 0) {
+ else if (strcmp("abstract", CMD_ARGV[i]) == 0)
abstract_cnt++;
- } else {
+ else {
LOG_ERROR("Unknown argument '%s'. "
"Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV[i]);
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -2533,13 +2559,17 @@ COMMAND_HANDLER(riscv_set_enable_virtual)
return ERROR_OK;
}
-int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
+int parse_ranges(struct list_head *ranges,
+ const char *tcl_arg,
+ const char *reg_type,
+ unsigned int max_val)
{
char *args = strdup(tcl_arg);
if (!args)
return ERROR_FAIL;
- /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
+ /* For backward compatibility, allow multiple parameters within one TCL argument, separated
+ * by ',' */
char *arg = strtok(args, ",");
while (arg) {
unsigned low = 0;
@@ -2567,7 +2597,8 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (sscanf(dash, "%u%n", &high, &pos) != 1 || pos != strlen(dash)) {
- LOG_ERROR("Failed to parse single register number from '%s'.", dash);
+ LOG_ERROR("Failed to parse single register number from '%s'.",
+ dash);
free(args);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -2597,7 +2628,8 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_
strcpy(name, reg_type);
name[strlen(reg_type)] = '_';
- if (sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1, &pos) != 1 || pos != strlen(equals)) {
+ if (sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1,
+ &pos) != 1 || pos != strlen(equals)) {
LOG_ERROR("Failed to parse register name from '%s'.", equals);
free(args);
free(name);
@@ -2612,7 +2644,11 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_
high = high > low ? high : low;
if (high > max_val) {
- LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type, high, max_val);
+ LOG_ERROR(
+ "Cannot expose %s register number %u, maximum allowed value is %u.",
+ reg_type,
+ high,
+ max_val);
free(name);
free(args);
return ERROR_FAIL;
@@ -2624,10 +2660,14 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_
if ((entry->low <= high) && (low <= entry->high)) {
if (low == high)
LOG_WARNING("Duplicate %s register number - "
- "Register %u has already been exposed previously", reg_type, low);
+ "Register %u has already been exposed previously",
+ reg_type,
+ low);
else
LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
- "with already exposed register/range at %u.", low, entry->low);
+ "with already exposed register/range at %u.",
+ low,
+ entry->low);
}
if (entry->name && name && (strcasecmp(entry->name, name) == 0)) {
@@ -2703,9 +2743,9 @@ COMMAND_HANDLER(riscv_authdata_read)
unsigned int index = 0;
if (CMD_ARGC == 0) {
/* nop */
- } else if (CMD_ARGC == 1) {
+ } else if (CMD_ARGC == 1)
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
- } else {
+ else {
LOG_ERROR("Command takes at most one parameter");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -2741,9 +2781,9 @@ COMMAND_HANDLER(riscv_authdata_write)
if (CMD_ARGC == 0) {
/* nop */
- } else if (CMD_ARGC == 1) {
+ } else if (CMD_ARGC == 1)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
- } else if (CMD_ARGC == 2) {
+ else if (CMD_ARGC == 2) {
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
} else {
@@ -2754,9 +2794,9 @@ COMMAND_HANDLER(riscv_authdata_write)
struct target *target = get_current_target(CMD_CTX);
RISCV_INFO(r);
- if (r->authdata_write) {
+ if (r->authdata_write)
return r->authdata_write(target, value, index);
- } else {
+ else {
LOG_ERROR("authdata_write is not implemented for this target.");
return ERROR_FAIL;
}
@@ -2809,9 +2849,9 @@ COMMAND_HANDLER(riscv_dmi_write)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
- if (r->dmi_write) {
+ if (r->dmi_write)
return r->dmi_write(target, address, value);
- } else {
+ else {
LOG_ERROR("dmi_write is not implemented for this target.");
return ERROR_FAIL;
}
@@ -2893,11 +2933,11 @@ COMMAND_HANDLER(riscv_resume_order)
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if (!strcmp(CMD_ARGV[0], "normal")) {
+ if (!strcmp(CMD_ARGV[0], "normal"))
resume_order = RO_NORMAL;
- } else if (!strcmp(CMD_ARGV[0], "reversed")) {
+ else if (!strcmp(CMD_ARGV[0], "reversed"))
resume_order = RO_REVERSED;
- } else {
+ else {
LOG_ERROR("Unsupported resume order: %s", CMD_ARGV[0]);
return ERROR_FAIL;
}
@@ -2913,9 +2953,9 @@ COMMAND_HANDLER(riscv_use_bscan_tunnel)
if (CMD_ARGC > 2) {
LOG_ERROR("Command takes at most two arguments");
return ERROR_COMMAND_SYNTAX_ERROR;
- } else if (CMD_ARGC == 1) {
+ } else if (CMD_ARGC == 1)
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
- } else if (CMD_ARGC == 2) {
+ else if (CMD_ARGC == 2) {
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tunnel_type);
}
@@ -3019,12 +3059,13 @@ COMMAND_HANDLER(handle_memory_sample_command)
command_print(CMD, "Memory sample configuration for %s:", target_name(target));
for (unsigned i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
if (r->sample_config.bucket[i].enabled) {
- command_print(CMD, "bucket %d; address=0x%" TARGET_PRIxADDR "; size=%d", i,
- r->sample_config.bucket[i].address,
- r->sample_config.bucket[i].size_bytes);
- } else {
+ command_print(CMD,
+ "bucket %d; address=0x%" TARGET_PRIxADDR "; size=%d",
+ i,
+ r->sample_config.bucket[i].address,
+ r->sample_config.bucket[i].size_bytes);
+ } else
command_print(CMD, "bucket %d; disabled", i);
- }
}
return ERROR_OK;
}
@@ -3037,25 +3078,27 @@ COMMAND_HANDLER(handle_memory_sample_command)
uint32_t bucket;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket);
if (bucket > ARRAY_SIZE(r->sample_config.bucket)) {
- LOG_ERROR("Max bucket number is %d.", (unsigned) ARRAY_SIZE(r->sample_config.bucket));
+ LOG_ERROR("Max bucket number is %d.",
+ (unsigned) ARRAY_SIZE(r->sample_config.bucket));
return ERROR_COMMAND_ARGUMENT_INVALID;
}
- if (!strcmp(CMD_ARGV[1], "clear")) {
+ if (!strcmp(CMD_ARGV[1], "clear"))
r->sample_config.bucket[bucket].enabled = false;
- } else {
+ else {
COMMAND_PARSE_ADDRESS(CMD_ARGV[1], r->sample_config.bucket[bucket].address);
if (CMD_ARGC > 2) {
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], r->sample_config.bucket[bucket].size_bytes);
+ COMMAND_PARSE_NUMBER(u32,
+ CMD_ARGV[2],
+ r->sample_config.bucket[bucket].size_bytes);
if (r->sample_config.bucket[bucket].size_bytes != 4 &&
- r->sample_config.bucket[bucket].size_bytes != 8) {
+ r->sample_config.bucket[bucket].size_bytes != 8) {
LOG_ERROR("Only 4-byte and 8-byte sizes are supported.");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
- } else {
+ } else
r->sample_config.bucket[bucket].size_bytes = 4;
- }
r->sample_config.bucket[bucket].enabled = true;
}
@@ -3084,9 +3127,9 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
}
bool base64 = false;
if (CMD_ARGC > 0) {
- if (!strcmp(CMD_ARGV[0], "base64")) {
+ if (!strcmp(CMD_ARGV[0], "base64"))
base64 = true;
- } else {
+ else {
LOG_ERROR("Unknown argument: %s", CMD_ARGV[0]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -3095,7 +3138,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
int result = ERROR_OK;
if (base64) {
unsigned char *encoded = base64_encode(r->sample_buf.buf,
- r->sample_buf.used, NULL);
+ r->sample_buf.used, NULL);
if (!encoded) {
LOG_ERROR("Failed base64 encode!");
result = ERROR_FAIL;
@@ -3117,7 +3160,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
command_print(CMD, "timestamp after: %u", timestamp);
} else if (command < ARRAY_SIZE(r->sample_config.bucket)) {
command_print_sameline(CMD, "0x%" TARGET_PRIxADDR ": ",
- r->sample_config.bucket[command].address);
+ r->sample_config.bucket[command].address);
if (r->sample_config.bucket[command].size_bytes == 4) {
uint32_t value = buf_get_u32(r->sample_buf.buf + i, 0, 32);
i += 4;
@@ -3128,13 +3171,15 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
command_print(CMD, "0x%016" PRIx64, value);
} else {
LOG_ERROR("Found invalid size in bucket %d: %d", command,
- r->sample_config.bucket[command].size_bytes);
+ r->sample_config.bucket[command].size_bytes);
result = ERROR_FAIL;
goto error;
}
} else {
- LOG_ERROR("Found invalid command byte in sample buf: 0x%2x at offset 0x%x",
- command, i - 1);
+ LOG_ERROR(
+ "Found invalid command byte in sample buf: 0x%2x at offset 0x%x",
+ command,
+ i - 1);
result = ERROR_FAIL;
goto error;
}
@@ -3148,7 +3193,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
}
COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
- unsigned value)
+ unsigned value)
{
char full_key[80];
snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
@@ -3166,7 +3211,7 @@ COMMAND_HANDLER(handle_info)
riscv_print_info_line(CMD, "hart", "xlen", riscv_xlen(target));
riscv_enumerate_triggers(target);
riscv_print_info_line(CMD, "hart", "trigger_count",
- r->trigger_count);
+ r->trigger_count);
if (r->print_info)
return CALL_COMMAND_HANDLER(r->print_info, target);
@@ -3239,8 +3284,8 @@ static const struct command_registration riscv_exec_command_handlers[] = {
.mode = COMMAND_ANY,
.usage = "on|off",
.help = "When on, memory accesses are performed on physical or virtual "
- "memory depending on the current system configuration. "
- "When off (default), all memory accessses are performed on physical memory."
+ "memory depending on the current system configuration. "
+ "When off (default), all memory accessses are performed on physical memory."
},
{
.name = "expose_csrs",
@@ -3248,8 +3293,8 @@ static const struct command_registration riscv_exec_command_handlers[] = {
.mode = COMMAND_CONFIG,
.usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
.help = "Configure a list of inclusive ranges for CSRs to expose in "
- "addition to the standard ones. This must be executed before "
- "`init`."
+ "addition to the standard ones. This must be executed before "
+ "`init`."
},
{
.name = "expose_custom",
@@ -3266,7 +3311,7 @@ static const struct command_registration riscv_exec_command_handlers[] = {
.usage = "[index]",
.mode = COMMAND_ANY,
.help = "Return the 32-bit value read from authdata or authdata0 "
- "(index=0), or authdata1 (index=1)."
+ "(index=0), or authdata1 (index=1)."
},
{
.name = "authdata_write",
@@ -3274,7 +3319,7 @@ static const struct command_registration riscv_exec_command_handlers[] = {
.mode = COMMAND_ANY,
.usage = "[index] value",
.help = "Write the 32-bit value to authdata or authdata0 (index=0), "
- "or authdata1 (index=1)."
+ "or authdata1 (index=1)."
},
{
.name = "dmi_read",
@@ -3508,7 +3553,7 @@ static int riscv_resume_go_all_harts(struct target *target)
return ERROR_FAIL;
} else {
LOG_DEBUG("[%s] hart requested resume, but was already resumed",
- target_name(target));
+ target_name(target));
}
riscv_invalidate_register_cache(target);
@@ -3613,8 +3658,8 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
{
/* GPRs, FPRs, vector registers are just normal data stores. */
if (regno <= GDB_REGNO_XPR31 ||
- (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||
- (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31))
+ (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||
+ (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31))
return true;
/* Most CSRs won't change value on us, but we can't assume it about arbitrary
@@ -3642,9 +3687,10 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
*/
return !write;
- case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
+ case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work.
+ */
case GDB_REGNO_TDATA1: /* Changes value when tselect is changed. */
- case GDB_REGNO_TDATA2: /* Changse value when tselect is changed. */
+ case GDB_REGNO_TDATA2: /* Changse value when tselect is changed. */
default:
return false;
}
@@ -3664,7 +3710,7 @@ int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t
/* TODO: Hack to deal with gdb that thinks these registers still exist. */
if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
- riscv_supports_extension(target, 'E'))
+ riscv_supports_extension(target, 'E'))
return ERROR_OK;
struct reg *reg = &target->reg_cache->reg_list[regid];
@@ -3679,12 +3725,12 @@ int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t
}
LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
- target_name(target), value, reg->name, reg->valid);
+ target_name(target), value, reg->name, reg->valid);
return ERROR_OK;
}
int riscv_get_register(struct target *target, riscv_reg_t *value,
- enum gdb_regno regid)
+ enum gdb_regno regid)
{
RISCV_INFO(r);
@@ -3693,20 +3739,20 @@ int riscv_get_register(struct target *target, riscv_reg_t *value,
struct reg *reg = &target->reg_cache->reg_list[regid];
if (!reg->exist) {
LOG_DEBUG("[%s] %s does not exist.",
- target_name(target), gdb_regno_name(regid));
+ target_name(target), gdb_regno_name(regid));
return ERROR_FAIL;
}
if (reg && reg->valid) {
*value = buf_get_u64(reg->value, 0, reg->size);
LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
- gdb_regno_name(regid), *value);
+ gdb_regno_name(regid), *value);
return ERROR_OK;
}
/* TODO: Hack to deal with gdb that thinks these registers still exist. */
if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 &&
- riscv_supports_extension(target, 'E')) {
+ riscv_supports_extension(target, 'E')) {
*value = 0;
return ERROR_OK;
}
@@ -3721,7 +3767,7 @@ int riscv_get_register(struct target *target, riscv_reg_t *value,
}
LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
- gdb_regno_name(regid), *value);
+ gdb_regno_name(regid), *value);
return result;
}
@@ -3842,7 +3888,7 @@ int riscv_enumerate_triggers(struct target *target)
* should be thrown. */
if (result != ERROR_OK) {
LOG_DEBUG("[%s] Cannot access tselect register. "
- "Assuming that triggers are not implemented.", target_name(target));
+ "Assuming that triggers are not implemented.", target_name(target));
r->trigger_count = 0;
return ERROR_OK;
}
@@ -4085,7 +4131,7 @@ static int register_get(struct reg *reg)
if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
if (!r->get_register_buf) {
LOG_ERROR("Reading register %s not supported on this RISC-V target.",
- gdb_regno_name(reg->number));
+ gdb_regno_name(reg->number));
return ERROR_FAIL;
}
@@ -4101,7 +4147,7 @@ static int register_get(struct reg *reg)
reg->valid = gdb_regno_cacheable(reg->number, false);
char *str = buf_to_hex_str(reg->value, reg->size);
LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
- str, reg->name, reg->valid);
+ str, reg->name, reg->valid);
free(str);
return ERROR_OK;
}
@@ -4114,7 +4160,7 @@ static int register_set(struct reg *reg, uint8_t *buf)
char *str = buf_to_hex_str(buf, reg->size);
LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
- str, reg->name, reg->valid);
+ str, reg->name, reg->valid);
free(str);
/* Exit early for writing x0, which on the hardware would be ignored, and we
@@ -4126,7 +4172,7 @@ static int register_set(struct reg *reg, uint8_t *buf)
reg->valid = gdb_regno_cacheable(reg->number, true);
if (reg->number == GDB_REGNO_TDATA1 ||
- reg->number == GDB_REGNO_TDATA2) {
+ reg->number == GDB_REGNO_TDATA2) {
r->manual_hwbp_set = true;
/* When enumerating triggers, we clear any triggers with DMODE set,
* assuming they were left over from a previous debug session. So make
@@ -4139,7 +4185,7 @@ static int register_set(struct reg *reg, uint8_t *buf)
if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
if (!r->set_register_buf) {
LOG_ERROR("Writing register %s not supported on this RISC-V target.",
- gdb_regno_name(reg->number));
+ gdb_regno_name(reg->number));
return ERROR_FAIL;
}
@@ -4184,11 +4230,11 @@ int riscv_init_registers(struct target *target)
if (!list_empty(&info->expose_custom)) {
range_list_t *entry;
list_for_each_entry(entry, &info->expose_custom, list)
- target->reg_cache->num_regs += entry->high - entry->low + 1;
+ target->reg_cache->num_regs += entry->high - entry->low + 1;
}
LOG_DEBUG("[%s] create register cache for %d registers",
- target_name(target), target->reg_cache->num_regs);
+ target_name(target), target->reg_cache->num_regs);
target->reg_cache->reg_list =
calloc(target->reg_cache->num_regs, sizeof(struct reg));
@@ -4223,8 +4269,12 @@ int riscv_init_registers(struct target *target)
};
/* These types are built into gdb. */
- static struct reg_data_type type_ieee_single = { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" };
- static struct reg_data_type type_ieee_double = { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" };
+ static struct reg_data_type type_ieee_single = {
+ .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single"
+ };
+ static struct reg_data_type type_ieee_double = {
+ .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double"
+ };
static struct reg_data_type_union_field single_double_fields[] = {
{"float", &type_ieee_single, single_double_fields + 1},
{"double", &type_ieee_double, NULL},
@@ -4300,30 +4350,26 @@ int riscv_init_registers(struct target *target)
info->vector_fields[0].next = info->vector_fields + 1;
info->vector_fields[1].name = "s";
info->vector_fields[1].type = &info->type_uint16_vector;
- } else {
+ } else
info->vector_fields[0].next = NULL;
- }
if (info->vlenb >= 4) {
info->vector_fields[1].next = info->vector_fields + 2;
info->vector_fields[2].name = "w";
info->vector_fields[2].type = &info->type_uint32_vector;
- } else {
+ } else
info->vector_fields[1].next = NULL;
- }
if (info->vlenb >= 8) {
info->vector_fields[2].next = info->vector_fields + 3;
info->vector_fields[3].name = "l";
info->vector_fields[3].type = &info->type_uint64_vector;
- } else {
+ } else
info->vector_fields[2].next = NULL;
- }
if (info->vlenb >= 16) {
info->vector_fields[3].next = info->vector_fields + 4;
info->vector_fields[4].name = "q";
info->vector_fields[4].type = &info->type_uint128_vector;
- } else {
+ } else
info->vector_fields[3].next = NULL;
- }
info->vector_fields[4].next = NULL;
info->vector_union.fields = info->vector_fields;
@@ -4334,7 +4380,8 @@ int riscv_init_registers(struct target *target)
info->type_vector.reg_type_union = &info->vector_union;
struct csr_info csr_info[] = {
-#define DECLARE_CSR(name, number) { number, #name },
+#define DECLARE_CSR(name, number) { number, #name \
+},
#include "encoding.h"
#undef DECLARE_CSR
};
@@ -4489,9 +4536,8 @@ int riscv_init_registers(struct target *target)
} else if (riscv_supports_extension(target, 'F')) {
r->reg_data_type = &type_ieee_single;
r->size = 32;
- } else {
+ } else
r->exist = false;
- }
switch (number) {
case GDB_REGNO_FT0:
r->name = "ft0";
@@ -4598,12 +4644,12 @@ int riscv_init_registers(struct target *target)
unsigned csr_number = number - GDB_REGNO_CSR0;
while (csr_info[csr_info_index].number < csr_number &&
- csr_info_index < ARRAY_SIZE(csr_info) - 1) {
+ csr_info_index < ARRAY_SIZE(csr_info) - 1) {
csr_info_index++;
}
- if (csr_info[csr_info_index].number == csr_number) {
+ if (csr_info[csr_info_index].number == csr_number)
r->name = csr_info[csr_info_index].name;
- } else {
+ else {
sprintf(reg_name, "csr%d", csr_number);
/* Assume unnamed registers don't exist, unless we have some
* configuration that tells us otherwise. That's important
@@ -4723,18 +4769,18 @@ int riscv_init_registers(struct target *target)
if (!r->exist && !list_empty(&info->expose_csr)) {
range_list_t *entry;
list_for_each_entry(entry, &info->expose_csr, list)
- if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
- if (entry->name) {
- *reg_name = 0;
- r->name = entry->name;
- }
+ if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
+ if (entry->name) {
+ *reg_name = 0;
+ r->name = entry->name;
+ }
- LOG_DEBUG("Exposing additional CSR %d (name=%s)",
- csr_number, entry->name ? entry->name : reg_name);
+ LOG_DEBUG("Exposing additional CSR %d (name=%s)",
+ csr_number, entry->name ? entry->name : reg_name);
- r->exist = true;
- break;
- }
+ r->exist = true;
+ break;
+ }
}
} else if (number == GDB_REGNO_PRIV) {
@@ -4756,7 +4802,9 @@ int riscv_init_registers(struct target *target)
/* Custom registers. */
assert(!list_empty(&info->expose_custom));
- range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list);
+ range_list_t *range = list_first_entry(&info->expose_custom,
+ range_list_t,
+ list);
unsigned custom_number = range->low + custom_within_range;
@@ -4775,7 +4823,7 @@ int riscv_init_registers(struct target *target)
}
LOG_DEBUG("Exposing additional custom register %d (name=%s)",
- number, range->name ? range->name : reg_name);
+ number, range->name ? range->name : reg_name);
custom_within_range++;
if (custom_within_range > range->high - range->low) {
@@ -4788,7 +4836,7 @@ int riscv_init_registers(struct target *target)
r->name = reg_name;
reg_name += strlen(reg_name) + 1;
assert(reg_name < info->reg_names + target->reg_cache->num_regs *
- max_reg_name_len);
+ max_reg_name_len);
}
r->value = calloc(1, DIV_ROUND_UP(r->size, 8));
}
@@ -4798,7 +4846,7 @@ int riscv_init_registers(struct target *target)
void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
- riscv_bscan_tunneled_scan_context_t *ctxt)
+ riscv_bscan_tunneled_scan_context_t *ctxt)
{
jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
diff --git a/src/target/target.c b/src/target/target.c
index 88ae555ad..8416681e3 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -62,7 +62,7 @@
extern unsigned char riscvchip;
-extern int wlink_reset();
+extern int wlink_reset(void);
extern int wlink_quitreset(void);
extern int wlink_verify(unsigned long length, unsigned char *buffer);
static int target_read_buffer_default(struct target *target, target_addr_t address,
@@ -3349,10 +3349,10 @@ COMMAND_HANDLER(handle_reset_command)
return target_process_reset(CMD, reset_mode);
}
+
COMMAND_HANDLER(handle_wlink_reset_resume_command)
{
-
- wlink_quitreset();
+ return wlink_quitreset();
}
COMMAND_HANDLER(handle_resume_command)
@@ -3818,13 +3818,12 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver
int retval;
uint32_t checksum = 0;
uint32_t mem_checksum = 0;
- int i;
struct image image;
struct target *target = get_current_target(CMD_CTX);
if((riscvchip==0x03)||(riscvchip==0x02)||(riscvchip==0x01)){
wlink_reset();
-
+
}
if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -3856,44 +3855,39 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver
image_size = 0x0;
int diffs = 0;
retval = ERROR_OK;
- if(riscvchip){
- uint32_t addr=0;
+ if(riscvchip) {
unsigned long length;
uint8_t *buffer1;
uint8_t *buffer2;
length=image.sections[image.num_sections-1].size + image.sections[image.num_sections-1].base_address;
-
-
- buffer2=malloc(length+256);
+
+
+ buffer2 = malloc(length+256);
memset(buffer2,0xff,length);
- for (i = 0; i < image.num_sections; i++) {
+ for (unsigned i = 0; i < image.num_sections; i++) {
buffer1 = malloc(image.sections[i].size);
retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer1, &buf_cnt);
- for(int j=0;j