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[PATCH][GCC] arm: Fix MVE scalar shift intrinsics code-gen.
This patch modifies the MVE scalar shift RTL patterns. The current patterns have wrong constraints and predicates due to which the values returned from MVE scalar shift instructions are overwritten in the code-gen. example: $ cat x.c int32_t foo(int64_t acc, int shift) { return sqrshrl_sat48 (acc, shift); } Code-gen before applying this patch: $ arm-none-eabi-gcc -march=armv8.1-m.main+mve -mfloat-abi=hard -O2 -S $ cat x.s foo: push {r4, r5} sqrshrl r0, r1, gcc-mirror#48, r2 ----> (a) mov r0, r4 ----> (b) pop {r4, r5} bx lr Code-gen after applying this patch: foo: sqrshrl r0, r1, gcc-mirror#48, r2 bx lr In the current compiler the return value (r0) from sqrshrl (a) is getting overwritten by the mov statement (b). This patch fixes above issue. 2020-06-12 Srinath Parvathaneni <[email protected]> gcc/ * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Correct the predicate and constraint of all the operands. (mve_sqrshrl_sat<supf>_di): Likewise. (mve_uqrshl_si): Likewise. (mve_sqrshr_si): Likewise. (mve_uqshll_di): Likewise. (mve_urshrl_di): Likewise. (mve_uqshl_si): Likewise. (mve_urshr_si): Likewise. (mve_sqshl_si): Likewise. (mve_srshr_si): Likewise. (mve_srshrl_di): Likewise. (mve_sqshll_di): Likewise. * config/arm/predicates.md (arm_low_register_operand): Define. gcc/testsuite/ * gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: New test. * gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise. (cherry picked from commit 6af5987)
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‎gcc/config/arm/mve.md‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -11344,9 +11344,9 @@
1134411344
;; [uqrshll_di]
1134511345
;;
1134611346
(define_insn "mve_uqrshll_sat<supf>_di"
11347-
[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11348-
(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11349-
(match_operand:SI 2 "s_register_operand" "r")]
11347+
[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
11348+
(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
11349+
(match_operand:SI 2 "register_operand" "r")]
1135011350
UQRSHLLQ))]
1135111351
"TARGET_HAVE_MVE"
1135211352
"uqrshll%?\\t%Q1, %R1, #<supf>, %2"
@@ -11356,9 +11356,9 @@
1135611356
;; [sqrshrl_di]
1135711357
;;
1135811358
(define_insn "mve_sqrshrl_sat<supf>_di"
11359-
[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11360-
(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11361-
(match_operand:SI 2 "s_register_operand" "r")]
11359+
[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
11360+
(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
11361+
(match_operand:SI 2 "register_operand" "r")]
1136211362
SQRSHRLQ))]
1136311363
"TARGET_HAVE_MVE"
1136411364
"sqrshrl%?\\t%Q1, %R1, #<supf>, %2"
@@ -11368,9 +11368,9 @@
1136811368
;; [uqrshl_si]
1136911369
;;
1137011370
(define_insn "mve_uqrshl_si"
11371-
[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11372-
(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
11373-
(match_operand:SI 2 "s_register_operand" "r")]
11371+
[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
11372+
(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
11373+
(match_operand:SI 2 "register_operand" "r")]
1137411374
UQRSHL))]
1137511375
"TARGET_HAVE_MVE"
1137611376
"uqrshl%?\\t%1, %2"
@@ -11380,9 +11380,9 @@
1138011380
;; [sqrshr_si]
1138111381
;;
1138211382
(define_insn "mve_sqrshr_si"
11383-
[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11384-
(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
11385-
(match_operand:SI 2 "s_register_operand" "r")]
11383+
[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
11384+
(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
11385+
(match_operand:SI 2 "register_operand" "r")]
1138611386
SQRSHR))]
1138711387
"TARGET_HAVE_MVE"
1138811388
"sqrshr%?\\t%1, %2"
@@ -11392,9 +11392,9 @@
1139211392
;; [uqshll_di]
1139311393
;;
1139411394
(define_insn "mve_uqshll_di"
11395-
[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11396-
(us_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
11397-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11395+
[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
11396+
(us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
11397+
(match_operand:SI 2 "immediate_operand" "Pg")))]
1139811398
"TARGET_HAVE_MVE"
1139911399
"uqshll%?\\t%Q1, %R1, %2"
1140011400
[(set_attr "predicable" "yes")])
@@ -11403,9 +11403,9 @@
1140311403
;; [urshrl_di]
1140411404
;;
1140511405
(define_insn "mve_urshrl_di"
11406-
[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11407-
(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11408-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11406+
[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
11407+
(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
11408+
(match_operand:SI 2 "immediate_operand" "Pg")]
1140911409
URSHRL))]
1141011410
"TARGET_HAVE_MVE"
1141111411
"urshrl%?\\t%Q1, %R1, %2"
@@ -11415,9 +11415,9 @@
1141511415
;; [uqshl_si]
1141611416
;;
1141711417
(define_insn "mve_uqshl_si"
11418-
[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11419-
(us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "r")
11420-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11418+
[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
11419+
(us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "0")
11420+
(match_operand:SI 2 "immediate_operand" "Pg")))]
1142111421
"TARGET_HAVE_MVE"
1142211422
"uqshl%?\\t%1, %2"
1142311423
[(set_attr "predicable" "yes")])
@@ -11426,9 +11426,9 @@
1142611426
;; [urshr_si]
1142711427
;;
1142811428
(define_insn "mve_urshr_si"
11429-
[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11430-
(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
11431-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11429+
[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
11430+
(unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
11431+
(match_operand:SI 2 "immediate_operand" "Pg")]
1143211432
URSHR))]
1143311433
"TARGET_HAVE_MVE"
1143411434
"urshr%?\\t%1, %2"
@@ -11438,9 +11438,9 @@
1143811438
;; [sqshl_si]
1143911439
;;
1144011440
(define_insn "mve_sqshl_si"
11441-
[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11442-
(ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "r")
11443-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11441+
[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
11442+
(ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "0")
11443+
(match_operand:SI 2 "immediate_operand" "Pg")))]
1144411444
"TARGET_HAVE_MVE"
1144511445
"sqshl%?\\t%1, %2"
1144611446
[(set_attr "predicable" "yes")])
@@ -11449,9 +11449,9 @@
1144911449
;; [srshr_si]
1145011450
;;
1145111451
(define_insn "mve_srshr_si"
11452-
[(set (match_operand:SI 0 "arm_general_register_operand" "+r")
11453-
(unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "r")
11454-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11452+
[(set (match_operand:SI 0 "arm_general_register_operand" "=r")
11453+
(unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "0")
11454+
(match_operand:SI 2 "immediate_operand" "Pg")]
1145511455
SRSHR))]
1145611456
"TARGET_HAVE_MVE"
1145711457
"srshr%?\\t%1, %2"
@@ -11461,9 +11461,9 @@
1146111461
;; [srshrl_di]
1146211462
;;
1146311463
(define_insn "mve_srshrl_di"
11464-
[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11465-
(unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
11466-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
11464+
[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
11465+
(unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
11466+
(match_operand:SI 2 "immediate_operand" "Pg")]
1146711467
SRSHRL))]
1146811468
"TARGET_HAVE_MVE"
1146911469
"srshrl%?\\t%Q1, %R1, %2"
@@ -11473,9 +11473,9 @@
1147311473
;; [sqshll_di]
1147411474
;;
1147511475
(define_insn "mve_sqshll_di"
11476-
[(set (match_operand:DI 0 "arm_general_register_operand" "+r")
11477-
(ss_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
11478-
(match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
11476+
[(set (match_operand:DI 0 "arm_low_register_operand" "=l")
11477+
(ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
11478+
(match_operand:SI 2 "immediate_operand" "Pg")))]
1147911479
"TARGET_HAVE_MVE"
1148011480
"sqshll%?\\t%Q1, %R1, %2"
1148111481
[(set_attr "predicable" "yes")])

‎gcc/config/arm/predicates.md‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,18 @@
155155
|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
156156
})
157157

158+
;; Low core register, or any pseudo.
159+
(define_predicate "arm_low_register_operand"
160+
(match_code "reg,subreg")
161+
{
162+
if (GET_CODE (op) == SUBREG)
163+
op = SUBREG_REG (op);
164+
165+
return (REG_P (op)
166+
&& (REGNO (op) <= LAST_LO_REGNUM
167+
|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
168+
})
169+
158170
(define_predicate "arm_general_adddi_operand"
159171
(ior (match_operand 0 "arm_general_register_operand")
160172
(and (match_code "const_int")

‎gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
/* { dg-do run } */
2+
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
3+
/* { dg-options "-O2" } */
4+
/* { dg-add-options arm_v8_1m_mve } */
5+
6+
#include "arm_mve.h"
7+
#include "stdio.h"
8+
#include <stdlib.h>
9+
10+
void
11+
foo (int64_t acc, int shift)
12+
{
13+
acc = sqrshrl_sat48 (acc, shift);
14+
if (acc != 16)
15+
abort();
16+
acc = sqrshrl (acc, shift);
17+
if (acc != 2)
18+
abort();
19+
}
20+
21+
void
22+
foo1 (uint64_t acc, int shift)
23+
{
24+
acc = uqrshll_sat48 (acc, shift);
25+
if (acc != 16)
26+
abort();
27+
acc = uqrshll (acc, shift);
28+
if (acc != 128)
29+
abort();
30+
}
31+
32+
int main()
33+
{
34+
int64_t acc = 128;
35+
uint64_t acc1 = 2;
36+
int shift = 3;
37+
foo (acc, shift);
38+
foo1 (acc1, shift);
39+
return 0;
40+
}

‎gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
/* { dg-do run } */
2+
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
3+
/* { dg-options "-O2" } */
4+
/* { dg-add-options arm_v8_1m_mve } */
5+
6+
#include "arm_mve.h"
7+
#include "stdio.h"
8+
#include <stdlib.h>
9+
10+
#define IMM 3
11+
12+
void
13+
foo (int64_t acc, uint64_t acc1)
14+
{
15+
acc = sqshll (acc, IMM);
16+
if (acc != 128)
17+
abort();
18+
acc = srshrl (acc, IMM);
19+
if (acc != 16)
20+
abort();
21+
acc1 = uqshll (acc1, IMM);
22+
if (acc1 != 128)
23+
abort();
24+
acc1 = urshrl (acc1, IMM);
25+
if (acc1 != 16)
26+
abort();
27+
}
28+
29+
int main()
30+
{
31+
int64_t acc = 16;
32+
uint64_t acc1 = 16;
33+
foo (acc, acc1);
34+
return 0;
35+
}

‎gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
/* { dg-do run } */
2+
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
3+
/* { dg-options "-O2" } */
4+
/* { dg-add-options arm_v8_1m_mve } */
5+
6+
#include "arm_mve.h"
7+
#include "stdio.h"
8+
#include <stdlib.h>
9+
10+
void
11+
foo (int32_t acc, uint32_t acc1, int shift)
12+
{
13+
acc = sqrshr (acc, shift);
14+
if (acc != 16)
15+
abort();
16+
acc1 = uqrshl (acc1, shift);
17+
if (acc1 != 128)
18+
abort();
19+
}
20+
21+
int main()
22+
{
23+
int32_t acc = 128;
24+
uint32_t acc1 = 16;
25+
int shift = 3;
26+
foo (acc, acc1, shift);
27+
return 0;
28+
}

‎gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
/* { dg-do run } */
2+
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
3+
/* { dg-options "-O2" } */
4+
/* { dg-add-options arm_v8_1m_mve } */
5+
6+
#include "arm_mve.h"
7+
#include <stdlib.h>
8+
9+
#define IMM 3
10+
11+
void
12+
foo (int32_t acc, uint32_t acc1)
13+
{
14+
acc = sqshl (acc, IMM);
15+
if (acc != 128)
16+
abort();
17+
acc = srshr (acc, IMM);
18+
if (acc != 16)
19+
abort();
20+
acc1 = uqshl (acc1, IMM);
21+
if (acc1 != 128)
22+
abort();
23+
acc1 = urshr (acc1, IMM);
24+
if (acc1 != 16)
25+
abort();
26+
}
27+
28+
int main()
29+
{
30+
int32_t acc = 16;
31+
uint32_t acc1 = 16;
32+
foo (acc, acc1);
33+
return 0;
34+
}

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