handle consecutive PC-relative instructions

change Rn to something else than pc, fill it with value of origin pc

example1:
     ldr r0, [pc, #4]
     ldr r0, [pc, r0]  ; <- we are here
     bx lr
     dcd vmaddr_offset_relative_to_pc

example2:
     ldr r1, [pc, #8]
     add r1, pc, r1    ; <- we are here
     str r0, [r1]
     bx lr
     dcd vmaddr_offset_relative_to_pc

Author: segfault-bilibili

source/InstructionRelocation/arm/InstructionRelocationARM.cc

@@ -10,6 +10,8 @@
 #include "core/assembler/assembler-arm.h"
 #include "core/codegen/codegen-arm.h"
 
+#include <algorithm>
+
 using namespace zz;
 using namespace zz::arm;
 
@@ -155,29 +157,26 @@ static void ARMRelocateSingleInsn(relo_ctx_t *ctx, int32_t insn) {
     uint32_t P, U, o2, W, o1, Rn, Rt, imm12;
     P = bit(insn, 24);
     U = bit(insn, 23);
+    o2 = bit(insn, 22);
     W = bit(insn, 21);
-    imm12 = bits(insn, 0, 11);
+    o1 = bit(insn, 20);
     Rn = bits(insn, 16, 19);
     Rt = bits(insn, 12, 15);
-    o1 = bit(insn, 20);
-    o2 = bit(insn, 22);
+    imm12 = bits(insn, 0, 11);
     uint32_t P_W = (P << 1) | W;
     do {
       // LDR (literal)
       DEBUG_LOG("%d:relo <ldr_literal> at %p", ctx->relocated_offset_map.size(), relo_cur_src_vmaddr(ctx));
-      if (o1 == 1 && o2 == 0 && P_W != 0b01 && Rn == 0b1111) {
-        goto load_literal_fix_scheme;
-      }
-      if (o1 == 1 && o2 == 1 && P_W != 0b01 && Rn == 0b1111) {
+      if (o1 == 1 /* && o2 == 0 */ && P_W != 0b01 && Rn == pc.code()) {
         goto load_literal_fix_scheme;
       }
       break;
     load_literal_fix_scheme:
-      addr32_t dst_vmaddr = 0;
+      addr32_t dst_vmaddr = relo_cur_src_vmaddr(ctx); // origin pc
       if (U == 0b1)
-        dst_vmaddr = relo_cur_src_vmaddr(ctx) + imm12;
+        dst_vmaddr += imm12;
       else
-        dst_vmaddr = relo_cur_src_vmaddr(ctx) - imm12;
+        dst_vmaddr -= imm12;
 
       Register intermediateReg = Register::R(Rt == pc.code() ? VOLATILE_REGISTER.code() : Rt);
       Register regRt = Register::R(Rt);
@@ -204,6 +203,74 @@ static void ARMRelocateSingleInsn(relo_ctx_t *ctx, int32_t insn) {
     } while (0);
   }
 
+  // handle some kinds of pc-relative instructions
+  if (cond != 0b1111 && (op0 == 0b000 || op0 == 0b011)) {
+    uint32_t P, U, o2, W, o1, Rn, Rt, imm5, type, Rm;
+    P = bit(insn, 24);
+    U = bit(insn, 23);
+    o2 = bit(insn, 22);
+    W = bit(insn, 21);
+    o1 = bit(insn, 20);
+    Rn = bits(insn, 16, 19);
+    Rt = bits(insn, 12, 15);
+    imm5 = bits(insn, 7, 11);
+    type = bits(insn, 5, 6);
+    Rm = bits(insn, 0, 3);
+    uint32_t P_W = (P << 1) | W;
+    if (Rn == pc.code() || Rm == pc.code()) {
+      do {
+        if (op0 == 0b000 && P == 0 && U == 1 && o2 == 0 && W == 0 && o1 == 0) {
+          // consecutive LDR (literal) - ADD (register, PC-relative)
+          // example:
+          //     ldr r1, [pc, #8]
+          //     add r1, pc, r1    ; <- we are here
+          //     str r0, [r1]
+          //     bx lr
+          //     dcd vmaddr_offset_relative_to_pc
+          goto inject_insn_change_Rn;
+        }
+        if (op0 == 0b011 && o1 == 1 && o2 == 0 && P_W != 0b01) {
+          // consecutive LDR (literal) - LDR (register, PC-relative)
+          // example:
+          //     ldr r0, [pc, #4]
+          //     ldr r0, [pc, r0]  ; <- we are here
+          //     bx lr
+          //     dcd vmaddr_offset_relative_to_pc
+          goto inject_insn_change_Rn;
+        }
+        break;
+      inject_insn_change_Rn:
+        int RnOffset = 16;
+        if (Rm == pc.code()) {
+          std::swap(Rm, Rn);
+          RnOffset = 0;
+        }
+        Register RmReg = Register::R(Rm);
+
+        // change Rn to something else than pc, fill it with value of origin pc
+        int32_t RnVal = relo_cur_src_vmaddr(ctx); // origin pc
+        Register RnReg = Register::R(Rm == 1 ? 0 : 1);
+        RegisterList RnRegList(RnReg);
+        insn &= ~(0x0f << RnOffset);
+        insn |= RnReg.code() << RnOffset;
+
+        auto RnValLabel = RelocLabel::withData(RnVal);
+        _ AppendRelocLabel(RnValLabel);
+
+        if (Rn != Rt) {
+          _ push(RnRegList);
+        }
+        _ Ldr(RnReg, RnValLabel);
+        _ EmitARMInst(insn);
+        if (Rn != Rt) {
+          _ pop(RnRegList);
+        }
+
+        is_insn_relocated = true;
+      } while (0);
+    }
+  }
+
   // Data-processing and miscellaneous instructions
   if (cond != 0b1111 && (op0 & 0b110) == 0b000) {
     uint32_t op0, op1, op2, op3, op4;