Ignore VUnit Defines

[AlexLao512]

Hi is it possible to add a feature to this tool so it will ignore defines in VUnit testbenches?

See Example - https://vunit.github.io/user_guide.html#systemverilog-test-benches

It would also be helpful if it did a find and replace of "TEST_SUITE begin" "TEST_SUITE_SETUP begin" with appropriate reasonable SystemVerilog syntax so syntax checking works within those blocks.

[AlexLao512]

Nevermind adding include directories to the argument list for the vlog command using "+incdir+" works.