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I'm planning to build a version of this analyzer to use with the 6809E, which has some differences from the 6809. Among them, it is possible to detect the beginning of instruction fetch by snooping the LIC (Last Instruction Cycle) signal (pin 38 of the 6809E).
This output goes high during the last cycle of every instruction and its high-to-low transition indicates that the first byte of an opcode will be latched at the end of the present bus cycle.
I'm opening this issue just to make a note of it.
The text was updated successfully, but these errors were encountered:
I'm planning to build a version of this analyzer to use with the 6809E, which has some differences from the 6809. Among them, it is possible to detect the beginning of instruction fetch by snooping the LIC (Last Instruction Cycle) signal (pin 38 of the 6809E).
Quoting "MC6809-MC6809E 8-Bit Microprocessor Programming Manual [M6809PM/AD]", section [1.11.4]:
1.11.4 LAST INSTRUCTION CYCLE (LIC) (MC6809E).This output goes high during the last cycle of every instruction and its high-to-low transition indicates that the first byte of an opcode will be latched at the end of the present bus cycle.
I'm opening this issue just to make a note of it.
The text was updated successfully, but these errors were encountered: