{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":24047050,"defaultBranch":"call0-4.8.2","name":"gcc-xtensa","ownerLogin":"jcmvbkbc","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2014-09-15T07:27:48.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/166731?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1717233717.0","currentOid":""},"activityList":{"items":[{"before":"17ee4e65dbd88b17f1c17fccca3d043bccf211f4","after":"ed96d0a44ac686032634737a323989f055dd8c46","ref":"refs/heads/xtensa-15-updates","pushedAt":"2024-07-30T00:24:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"jcmvbkbc","name":"Max Filippov","path":"/jcmvbkbc","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/166731?s=80&v=4"},"commit":{"message":"xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COST\n\nAccording to the implemented pipeline model, this cost can be assumed to be\n1 clock cycle.\n\ngcc/ChangeLog:\n\n\t* config/xtensa/xtensa.cc (xtensa_insn_cost):\n\tAdd a case statement for TYPE_FARITH.","shortMessageHtmlLink":"xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COST"}},{"before":"29e230baeba397ec924e59cfea8eccc9e34b88d5","after":"17ee4e65dbd88b17f1c17fccca3d043bccf211f4","ref":"refs/heads/xtensa-15-updates","pushedAt":"2024-07-29T07:10:02.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"jcmvbkbc","name":"Max Filippov","path":"/jcmvbkbc","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/166731?s=80&v=4"},"commit":{"message":"xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions\n\n[U]FLOAT.S machine instruction in Xtensa ISA, which converts an integer to\na hardware single-precision FP register, has the ability to divide the\nresult by power of two (0 to 15th).\n\nSimilarly, [U]TRUNC.S instruction, which truncates single-precision FP to\ninteger, can multiply the source value by power of two in advance, but\nneither of these currently uses this function (always specified with 0th\npower of two, i.e. a scaling factor of 1).\n\nThis patch unleashes the scaling ability of the above instructions.\n\n /* example */\n float test0(int a) {\n return a / 2.f;\n }\n float test1(unsigned int a) {\n return a / 32768.f;\n }\n int test2(float a) {\n return a * 2;\n }\n unsigned int test3(float a) {\n return a * 32768;\n }\n\n ;; before\n test0:\n \tmovi.n\ta9, 0x3f\n \tfloat.s\tf0, a2, 0\n \tslli\ta9, a9, 24\n \twfr\tf1, a9\n \tmul.s\tf0, f0, f1\n \trfr\ta2, f0\n \tret.n\n test1:\n \tmovi.n\ta9, 7\n \tufloat.s\tf0, a2, 0\n \tslli\ta9, a9, 27\n \twfr\tf1, a9\n \tmul.s\tf0, f0, f1\n \trfr\ta2, f0\n \tret.n\n test2:\n \twfr\tf1, a2\n \tadd.s\tf0, f1, f1\n \ttrunc.s\ta2, f0, 0\n \tret.n\n test3:\n \tmovi.n\ta9, 0x47\n \tslli\ta9, a9, 24\n \twfr\tf1, a2\n \twfr\tf2, a9\n \tmul.s\tf0, f1, f2\n \tutrunc.s\ta2, f0, 0\n \tret.n\n\n ;; after\n test0:\n \tfloat.s\tf0, a2, 1\n \trfr\ta2, f0\n \tret.n\n test1:\n \tufloat.s\tf0, a2, 15\n \trfr\ta2, f0\n \tret.n\n test2:\n \twfr\tf0, a2\n \ttrunc.s\ta2, f0, 1\n \tret.n\n test3:\n \twfr\tf0, a2\n \tutrunc.s\ta2, f0, 15\n \tret.n\n\ngcc/ChangeLog:\n\n\t* config/xtensa/predicates.md\n\t(fix_scaling_operand, float_scaling_operand): New predicates.\n\t* config/xtensa/xtensa.md\n\t(any_fix/m_fix/s_fix, any_float/m_float/s_float):\n\tNew code iterators and their attributes.\n\t(fix_truncsfsi2): Change from \"fix_truncsfsi2\".\n\t(*fix_truncsfsi2_2x, *fix_truncsfsi2_scaled):\n\tNew insn definitions.\n\t(floatsisf2): Change from \"floatsisf2\".\n\t(*floatsisf2_scaled): New insn definition.","shortMessageHtmlLink":"xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions"}},{"before":"9c697d888d5d15f88f72d909471d971ba1f1a45e","after":"29e230baeba397ec924e59cfea8eccc9e34b88d5","ref":"refs/heads/xtensa-15-updates","pushedAt":"2024-07-20T04:55:38.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"jcmvbkbc","name":"Max Filippov","path":"/jcmvbkbc","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/166731?s=80&v=4"},"commit":{"message":"xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions\n\n[U]FLOAT.S machine instruction in Xtensa ISA, which converts an integer to\na hardware single-precision FP register, has the ability to divide the\nresult by power of two (0 to 15th).\n\nSimilarly, [U]TRUNC.S instruction, which truncates single-precision FP to\ninteger, can multiply the source value by power of two in advance, but\nneither of these currently uses this function (always specified with 0th\npower of two, i.e. a scaling factor of 1).\n\nThis patch unleashes the scaling ability of the above instructions.\n\n /* example */\n float test0(int a) {\n return a / 2.f;\n }\n float test1(unsigned int a) {\n return a / 32768.f;\n }\n int test2(float a) {\n return a * 2;\n }\n unsigned int test3(float a) {\n return a * 32768;\n }\n\n ;; before\n test0:\n \tmovi.n\ta9, 0x3f\n \tfloat.s\tf0, a2, 0\n \tslli\ta9, a9, 24\n \twfr\tf1, a9\n \tmul.s\tf0, f0, f1\n \trfr\ta2, f0\n \tret.n\n test1:\n \tmovi.n\ta9, 7\n \tufloat.s\tf0, a2, 0\n \tslli\ta9, a9, 27\n \twfr\tf1, a9\n \tmul.s\tf0, f0, f1\n \trfr\ta2, f0\n \tret.n\n test2:\n \twfr\tf1, a2\n \tadd.s\tf0, f1, f1\n \ttrunc.s\ta2, f0, 0\n \tret.n\n test3:\n \tmovi.n\ta9, 0x47\n \tslli\ta9, a9, 24\n \twfr\tf1, a2\n \twfr\tf2, a9\n \tmul.s\tf0, f1, f2\n \tutrunc.s\ta2, f0, 0\n \tret.n\n\n ;; after\n test0:\n \tfloat.s\tf0, a2, 1\n \trfr\ta2, f0\n \tret.n\n test1:\n \tufloat.s\tf0, a2, 15\n \trfr\ta2, f0\n \tret.n\n test2:\n \twfr\tf0, a2\n \ttrunc.s\ta2, f0, 1\n \tret.n\n test3:\n \twfr\tf0, a2\n \tutrunc.s\ta2, f0, 15\n \tret.n\n\ngcc/ChangeLog:\n\n\t* config/xtensa/predicates.md\n\t(fix_scaling_operand, float_scaling_operand): New predicates.\n\t* config/xtensa/xtensa.md\n\t(any_fix/m_fix/s_fix, any_float/m_float/s_float):\n\tNew code iterators and their attributes.\n\t(fix_truncsfsi2): Change from \"fix_truncsfsi2\".\n\t(*fix_truncsfsi2_2x, *fix_truncsfsi2_scaled):\n\tNew insn definitions.\n\t(floatsisf2): Change from \"floatsisf2\".\n\t(*floatsisf2_scaled): New insn definition.","shortMessageHtmlLink":"xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions"}},{"before":"a5e14a113d6fb6e7d16b409ecac7e86e5488f5b5","after":"9c697d888d5d15f88f72d909471d971ba1f1a45e","ref":"refs/heads/xtensa-15-updates","pushedAt":"2024-07-15T20:22:03.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"jcmvbkbc","name":"Max Filippov","path":"/jcmvbkbc","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/166731?s=80&v=4"},"commit":{"message":"xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions\n\n[U]FLOAT.S machine instruction in Xtensa ISA, which converts an integer to\na hardware single-precision FP register, has the ability to divide the\nresult by power of two (0 to 15th).\n\nSimilarly, [U]TRUNC.S instruction, which truncates single-precision FP to\ninteger, can multiply the source value by power of two in advance, but\nneither of these currently uses this function (always specified with 0th\npower of two, i.e. a scaling factor of 1).\n\nThis patch unleashes the scaling ability of the above instructions.\n\n /* example */\n float test0(int a) {\n return a / 2.f;\n }\n float test1(unsigned int a) {\n return a / 32768.f;\n }\n int test2(float a) {\n return a * 2;\n }\n unsigned int test3(float a) {\n return a * 32768;\n }\n\n ;; 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