RISC-V: CT and doit are wrong

[eponier]

We modelled RISC-V with every instruction being both CT and doit. Now that we have DIV and REM, this is certainly false.

This is not hard to do but I don't have the time right now. In the RISC-V spec, there is something called Zkt which, if mentioned by a device, means that the instructions listed are guaranteed to be CT. There is no flag, unlike x86 and ARM.

There is also a notion of hints, encoded with instructions whose destination register is x0. The instruction can be in Zkt (e.g. it can be ADDI). One must just check that this is not problematic for our modeling of CT and doit.