From 358604d4b5669a531aa0da789336da61ae195f5b Mon Sep 17 00:00:00 2001 From: Ian Wood Date: Fri, 2 May 2025 09:17:04 -0700 Subject: [PATCH 1/5] Fix for changes to LLVM::GEPOp https://github.com/llvm/llvm-project/pull/137272 plumbs through nusw and nuw by removing `inbounds` and replaces it with a enum. Signed-off-by: Ian Wood --- .../src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp | 6 +++--- .../src/iree/compiler/Codegen/LLVMCPU/DispatchABI.cpp | 9 +++++---- third_party/llvm-project | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp index 67b13d5e4810..62a23eb3284e 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp +++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp @@ -349,9 +349,9 @@ acquireInstrumentationEntry(Location loc, Value buffer, Value bufferPtr, Value offsetIndex = builder.create(loc, i64Type, headOffset); auto i8Type = builder.getI8Type(); - Value offsetPtr = builder.create(loc, basePtr.getType(), i8Type, - basePtr, offsetIndex, - /*inbounds=*/true); + Value offsetPtr = builder.create( + loc, basePtr.getType(), i8Type, basePtr, offsetIndex, + /*noWrapFlags =*/LLVM::GEPNoWrapFlags::inbounds); Value rawOffset = builder.create( loc, LLVM::AtomicBinOp::add, offsetPtr, entrySize, LLVM::AtomicOrdering::monotonic); diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/DispatchABI.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/DispatchABI.cpp index 47c545412bd3..01ad266334a0 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMCPU/DispatchABI.cpp +++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/DispatchABI.cpp @@ -952,11 +952,12 @@ Value HALDispatchABI::updateProcessorDataFromTargetAttr( for (int64_t i = 1, e = ProcessorDataCapacity; i < e; ++i) { Value loadPtr = builder.create( loc, processorDataPtrValue.getType(), i64Ty, processorDataPtrValue, - LLVM::GEPArg(int32_t(i)), /*inbounds =*/true); + LLVM::GEPArg(int32_t(i)), + /*noWrapFlags =*/LLVM::GEPNoWrapFlags::inbounds); Value loadVal = builder.create(loc, i64Ty, loadPtr); Value storePtr = builder.create( loc, alloca.getType(), i64Ty, alloca, LLVM::GEPArg(int32_t(i)), - /*inbounds =*/true); + /*noWrapFlags =*/LLVM::GEPNoWrapFlags::inbounds); builder.create(loc, loadVal, storePtr); } return alloca; @@ -978,12 +979,12 @@ Value HALDispatchABI::loadProcessorData(Operation *forOp, OpBuilder &builder) { loc, LLVM::LLVMPointerType::get(context), LLVM::LLVMPointerType::get(context), environmentPtrValue, LLVM::GEPArg(int32_t(EnvironmentField::processor)), - /*inbounds=*/true); + /*noWrapFlags =*/LLVM::GEPNoWrapFlags::inbounds); Value processorDataPtrValue = builder.create( loc, LLVM::LLVMPointerType::get(context), LLVM::LLVMPointerType::get(context), processorPtrValue, LLVM::GEPArg(int32_t(ProcessorField::data)), - /*inbounds=*/true); + /*noWrapFlags =*/LLVM::GEPNoWrapFlags::inbounds); Value updatedProcessorData = updateProcessorDataFromTargetAttr(forOp, processorDataPtrValue, builder); return buildValueDI(forOp, updatedProcessorData, "processor_data", diff --git a/third_party/llvm-project b/third_party/llvm-project index d599f44c260b..9b3db2955f17 160000 --- a/third_party/llvm-project +++ b/third_party/llvm-project @@ -1 +1 @@ -Subproject commit d599f44c260bbd900756021d7aa0dd39f49dea86 +Subproject commit 9b3db2955f17d97b1c7e96fc532ef1307284e67a From d822b9fedf5dec7945ff967af17e79463ed5ff75 Mon Sep 17 00:00:00 2001 From: Ian Wood Date: Mon, 5 May 2025 08:35:16 -0700 Subject: [PATCH 2/5] Revert llvm/llvm-project 7318074168e324097b7f6ec93e34915463bf70f1 Signed-off-by: Ian Wood --- third_party/llvm-project | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/llvm-project b/third_party/llvm-project index 9b3db2955f17..5ac9646a9b49 160000 --- a/third_party/llvm-project +++ b/third_party/llvm-project @@ -1 +1 @@ -Subproject commit 9b3db2955f17d97b1c7e96fc532ef1307284e67a +Subproject commit 5ac9646a9b4975982a4f93ff54144146d034242e From c592a5b8099c214d04a49305b427481fff8e367f Mon Sep 17 00:00:00 2001 From: Ian Wood Date: Mon, 5 May 2025 08:37:53 -0700 Subject: [PATCH 3/5] Advance LLVM to 15f7c6ed70c82ead0f2bd6725fa0c4ec9a6b2dfa: [mlir] Remove unused local variables (NFC) (#138481) (Kazu Hirata on 2025-05-05 10:08:00 -0700) (0 of 1) Signed-off-by: Ian Wood --- third_party/llvm-project | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/llvm-project b/third_party/llvm-project index 5ac9646a9b49..d50462866eb2 160000 --- a/third_party/llvm-project +++ b/third_party/llvm-project @@ -1 +1 @@ -Subproject commit 5ac9646a9b4975982a4f93ff54144146d034242e +Subproject commit d50462866eb20ff52bd6a1d69d18ba5a672cd9b9 From 9f731f87b196646973c77268d88618533b40347d Mon Sep 17 00:00:00 2001 From: Ian Wood Date: Mon, 5 May 2025 13:51:08 -0700 Subject: [PATCH 4/5] Fix tests after https://github.com/llvm/llvm-project/commit/1a44f38d2af8724e9819f03d4b76a50615217a8d Signed-off-by: Ian Wood --- .../gpu_nested_layout_vector_distribution_mask.mlir | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_mask.mlir b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_mask.mlir index c87fb3d2ca18..564c0ba8e0d6 100644 --- a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_mask.mlir +++ b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_mask.mlir @@ -223,10 +223,9 @@ builtin.module attributes { transform.with_named_sequence } { // CHECK: %[[RED_IDENTITY:.+]] = arith.constant dense<0.000000e+00> : vector<2x1x2x1x2x8xf16> // CHECK: %[[MASK:.+]] = vector.create_mask -// CHECK: %[[MASK_PCK:.+]] = vector.shape_cast %[[MASK]] : vector<8x8xi1> to vector<2x2x2x1x1x8xi1> -// CHECK: %[[MASK_ITL_PCK:.+]] = vector.transpose %[[MASK_PCK]], [0, 3, 1, 4, 2, 5] : vector<2x2x2x1x1x8xi1> to vector<2x1x2x1x2x8xi1> +// CHECK: %[[MASK_PCK:.+]] = vector.shape_cast %[[MASK]] : vector<8x8xi1> to vector<2x1x2x1x2x8xi1> -// CHECK: %[[SELECT:.+]] = arith.select %[[MASK_ITL_PCK]], {{.*}}, %[[RED_IDENTITY]] : vector<2x1x2x1x2x8xi1>, vector<2x1x2x1x2x8xf16> +// CHECK: %[[SELECT:.+]] = arith.select %[[MASK_PCK]], {{.*}}, %[[RED_IDENTITY]] : vector<2x1x2x1x2x8xi1>, vector<2x1x2x1x2x8xf16> // CHECK: vector.multi_reduction , %[[SELECT]], {{.*}} [0, 2, 4] : vector<2x1x2x1x2x8xf16> to vector<1x1x8xf16> // ----- @@ -308,8 +307,7 @@ builtin.module attributes { transform.with_named_sequence } { // Currently, it does not fold away. // CHECK-DAG: %[[MASK_OP_1D:.+]] = vector.extract %[[MASK_OP]][0] : vector<2xi1> from vector<2x2xi1> // CHECK-DAG: %[[MASK_OP_1D_PACKED:.+]] = vector.shape_cast %[[MASK_OP_1D]] : vector<2xi1> to vector<1x1x2xi1> -// CHECK-DAG: %[[MASK_OP_PACKED:.+]] = vector.shape_cast %[[MASK_OP]] : vector<2x2xi1> to vector<1x1x2x1x1x2xi1> -// CHECK-DAG: %[[MASK_OP_INTERLEAVED:.+]] = vector.transpose %[[MASK_OP_PACKED]], [0, 3, 1, 4, 2, 5] : vector<1x1x2x1x1x2xi1> to vector<1x1x1x1x2x2xi1> +// CHECK-DAG: %[[MASK_OP_PACKED:.+]] = vector.shape_cast %[[MASK_OP]] : vector<2x2xi1> to vector<1x1x1x1x2x2xi1> // CHECK-DAG: %[[MASK_OUT:.+]] = vector.create_mask {{.*}} : vector<2xi1> // CHECK-DAG: %[[LHS_READ:.+]] = vector.transfer_read %arg0{{.*}} %[[MASK_LHS]] {in_bounds = [true]} : memref, vector<2xf16> @@ -318,6 +316,6 @@ builtin.module attributes { transform.with_named_sequence } { // CHECK-DAG: %[[RHS:.+]] = vector.insert_strided_slice %[[RHS_READ]] // CHECK-DAG: %[[LHS_SELECT:.+]] = arith.select %[[MASK_OP_1D_PACKED]], %[[LHS]], %[[RED_IDENTITY_LHS]] : vector<1x1x2xi1>, vector<1x1x2xf16> -// CHECK-DAG: %[[RHS_SELECT:.+]] = arith.select %[[MASK_OP_INTERLEAVED]], %[[RHS]], %[[RED_IDENTITY_RHS]] : vector<1x1x1x1x2x2xi1>, vector<1x1x1x1x2x2xf16> +// CHECK-DAG: %[[RHS_SELECT:.+]] = arith.select %[[MASK_OP_PACKED]], %[[RHS]], %[[RED_IDENTITY_RHS]] : vector<1x1x1x1x2x2xi1>, vector<1x1x1x1x2x2xf16> // CHECK: vector.contract {{.*}} %[[LHS_SELECT]], %[[RHS_SELECT]] From cfb1d001caa40fa9d152a43f03da47a65b6b23dd Mon Sep 17 00:00:00 2001 From: Ian Wood Date: Tue, 6 May 2025 09:42:35 -0700 Subject: [PATCH 5/5] Revert AMDGPU change causing correctness issue Reverts https://github.com/llvm/llvm-project/pull/137930 and https://github.com/llvm/llvm-project/commit/e1cff21f65fc876f7a9d0531a4b4d2aa3f0b4f21 to fix failure of e2e_matmul_cdna3_pad_i8_rocm_hip. Signed-off-by: Ian Wood --- third_party/llvm-project | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/llvm-project b/third_party/llvm-project index d50462866eb2..09419768db5a 160000 --- a/third_party/llvm-project +++ b/third_party/llvm-project @@ -1 +1 @@ -Subproject commit d50462866eb20ff52bd6a1d69d18ba5a672cd9b9 +Subproject commit 09419768db5a65fc12735ac0c293931aac482171