bd466fq0394.ttx

title         |    SEMICONDUCTOR CRYSTAL ISLANDS FOR
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title         |       THREE-DIMENSIONAL INTEGRATION
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text          |                    A DISSERTATION
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text          | SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
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text          |        AND THE COMMITTEE ON GRADUATE STUDIES
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text          |                OF STANFORD UNIVERSITY
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text          |      IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
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text          |                   FOR THE DEGREE OF
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text          |                 DOCTOR OF PHILOSOPHY
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text          |                      Filip Crnogorac
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text          |                        June 2010
              |                    © 2010 by Filip Crnogorac. All Rights Reserved.
              |          Re-distributed by Stanford University under license with the author.
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text          |                          This work is licensed under a Creative Commons Attribution-
              |                          Noncommercial 3.0 United States License.
              |                          http://creativecommons.org/licenses/by-nc/3.0/us/
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text          | This dissertation is online at: http://purl.stanford.edu/bd466fq0394
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meta          |                                            ii
text          | I certify that I have read this dissertation and that, in my opinion, it is fully adequate
              | in scope and quality as a dissertation for the degree of Doctor of Philosophy.
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text          |                                                                    R Pease, Primary Adviser
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text          | I certify that I have read this dissertation and that, in my opinion, it is fully adequate
              | in scope and quality as a dissertation for the degree of Doctor of Philosophy.
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text          |                                                              Mark Brongersma, Co-Adviser
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text          | I certify that I have read this dissertation and that, in my opinion, it is fully adequate
              | in scope and quality as a dissertation for the degree of Doctor of Philosophy.
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text          |                                                                                   Yoshio Nishi
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text          | I certify that I have read this dissertation and that, in my opinion, it is fully adequate
              | in scope and quality as a dissertation for the degree of Doctor of Philosophy.
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text          |                                                                             Theodore Kamins
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text          | Approved for the Stanford University Committee on Graduate Studies.
              |                                  Patricia J. Gumport, Vice Provost Graduate Education
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text          | This signature page was generated electronically upon submission of this dissertation in
              | electronic format. An original signed hard copy of the signature page is on file in
              | University Archives.
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title         | Abstract
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text          |        The critical operation needed to achieve 3-dimensional integrated circuits
              | (3DICs) is obtaining single-crystal, device-quality semiconductor material on upper
              | circuit layers without damaging circuits below (400°C temperature limit). Simulation
              | shows that microsecond pulse 532 nm Nd:YAG laser can melt and crystallize
              | amorphous Si or Ge layers without excessively heating the circuit layers underneath.
              | However, experimental results of unseeded (graphoepitaxy) and seeded (RMG)
              | crystallization of Si and Ge indicate that much longer pulse lengths are required for
              | high-quality single-crystal formation, rendering the approach not 3DIC compatible.
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text          |        A more straightforward approach is to directly attach high-quality crystal islands
              | for upper-layer device fabrication. A variety of viable low-temperature (≤400°C)
              | bonding methods have been investigated: fusion bonding (SiO2-SiO2, Si-SiO2, Ge-
              | SiO2), thermo-compressive bonding (Cu-Cu, Ti-Ti), as well as AlGe eutectic bonding.
              | The unique advantages of AlGe technique for 3DICs are reported for the first time.
              | They include superior bond strength, low void density, non-stringent roughness
              | requirement, use of thin films and CMOS friendly materials. Finally, we present a
              | completed 3DIC compatible process of obtaining single crystal Si or Ge islands for
              | upper layer device fabrication via SmartCut® and CMP finish.
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title         |                                                  Acknowledgements
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text          |            Professor Pease, for your uplifting enthusiasm, honesty and guidance,
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text          |                               Professor Wong, for putting your confidence in me,
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text          |                  Professor Brongersma, for making me fall in love with teaching,
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text          |                  Professor Kamins, for your patience and dedication beyond call,
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text          |     Professors Nishi and Wang, for being accessible and offering your expertise,
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text          | Ann, Rich and Bob, for making electron microscopy the most exciting of pursuits,
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text          | Bipin, Dan, Pickard, Ali and Zhi, for safely guiding me through the rough waters,
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text          |                                  Sandy and Gail, for clockwork-like organization,
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text          |        SNF staff, Gary Yama, Peter Griffin, for fighting the battles alongside me,
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text          |            Colleagues at CIS, for sharing the best of times and the worst of times,
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text          |              Pease group members, present and past, for spicing up my daily life,
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text          |                     My parents and sister, for your unwavering love and support,
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text          |                    My friends, for going through it all, and still being my friends,
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text          |                                  Sophie, Andrew, Ben and Phil, for being family,
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text          |                                                                      Thank you all.
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title         | Table of Contents
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text          | Chapter 1: Introduction ....................................................................................................1
              |      1.1       Motivation ......................................................................................................1
              |      1.2       Construction methods for 3-D ICs..................................................................3
              |      1.3       Monolithic 3-D integration .............................................................................8
              |      1.4       Prior art .........................................................................................................10
              |      1.5       Contributions ................................................................................................13
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text          | Chapter 2: Graphoepitaxy...............................................................................................15
              |      2.1       Introduction to graphoepitaxy.......................................................................15
              |      2.2       Liquid phase graphoepitaxy (Prior art).........................................................19
              |      2.3       Feasibility of transient heating for 3-D integration ......................................20
              |      2.4       Laser annealing apparatus.............................................................................22
              |      2.5       Graphoepitaxy using 1-D templates .............................................................23
              |                2.5.1      Design of nano-grating template ......................................................23
              |                2.5.2      Results of pulsed laser (1-D) graphoepitaxy ....................................24
              |                2.5.3      Conclusions of initial 1-D template experiments .............................27
              |      2.6       Graphoepitaxy using 2-D templates .............................................................29
              |                2.6.1      Design of inverted pyramid template ...............................................29
              |                2.6.2      Results of 2-D template experiments................................................31
              |                2.6.3      Conclusions of 2-D template graphoepitaxy ....................................38
              |      2.7       Solid phase graphoepitaxy............................................................................39
              |                2.7.1      Silicon solid phase graphoepitaxy (1-D) ..........................................39
              |      2.8       Graphoepitaxy by excimer laser annealing...................................................43
              |      2.9       Graphoepitaxy by scanned cw laser anneal ..................................................45
              |      2.10      Summary of graphoepitaxy results ...............................................................47
              |      2.11      Conclusions...................................................................................................47
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text          | Chapter 3: Modeling and Smiulation .............................................................................50
              |      3.1       Introduction...................................................................................................50
              |      3.2       Classical crystallization theory .....................................................................50
              |      3.3       Test structure - model and fabrication ..........................................................54
              |      3.4       Algorithm......................................................................................................55
              |      3.5       Results ..........................................................................................................56
              |      3.6       Conclusion and implications for graphoepitaxy ...........................................59
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text          | Chapter 4: Aluminum-Germanium Bonding..................................................................61
              |      4.1       Introduction...................................................................................................61
              |      4.2       Experimental details .....................................................................................62
              |      4.3       Strength of Al-Ge eutectic bond ...................................................................65
              |      4.4       Void formation in Al-Ge eutectic bonds ......................................................68
              |      4.5       Bond morphology of Al-Ge eutectic bond ...................................................69
              |      4.6       Attaching silicon islands by Al-Ge eutectic bonding ...................................73
              |      4.7       SmartCut® release method............................................................................76
              |      4.8       Semiconductor islands using SmartCut® donor wafer release .....................78
              |      4.9       Sub-eutectic Al-Ge bonding .........................................................................80
              |      4.10      Conclusions...................................................................................................82
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text          | Chapter 5: Copper Bonding ............................................................................................83
              |      5.1       Introduction...................................................................................................83
              |      5.2       Mechanism....................................................................................................84
              |      5.3       Surface preparation and characterization......................................................85
              |      5.4       Cu-Cu bonding procedure.............................................................................87
              |      5.5       Copper bond strength tests............................................................................88
              |      5.6       Copper bonding for monolithic 3DIC applications ......................................89
              |      5.7       Conclusions and future of copper based bonding.........................................94
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text          | Chapter 6: Titanium Bonding.........................................................................................95
              |      6.1       Introduction...................................................................................................95
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text          |      6.2       Advantages of titnium-based bonding ..........................................................95
              |      6.3       Mechanism....................................................................................................96
              |      6.4       Ti-Ti bonding process...................................................................................97
              |      6.5       Titnium bonding results................................................................................99
              |      6.6       Conclusions.................................................................................................103
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text          | Chapter 7: Fusion Bonding...........................................................................................104
              |      7.1       Introduction.................................................................................................104
              |      7.2       Mechanism of hydrophilic bonding............................................................105
              |      7.3       Low-temperature hydrophilic bonding .......................................................107
              |                7.3.1      Surface activation for low-temperature fusion bonding .................107
              |                7.3.2      Achieving surface smoothness required for fusion bonding ..........110
              |      7.4       Fusion bonding procedure ..........................................................................113
              |      7.5       Fusion bonding results................................................................................114
              |      7.6       CMP polishing of fusion attached islands ..................................................118
              |      7.7       Strength tests...............................................................................................119
              |      7.8       Fusion island bonding - design considerations...........................................121
              |      7.9       Conclusions.................................................................................................123
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text          | Chapter 8: Conclusion ..................................................................................................124
              |      8.1       Summary of results .....................................................................................124
              |      8.2       Monolithic 3-D integration of FPGA .........................................................127
              |      8.3       Final thoughts .............................................................................................129
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text          | Appendix A: CMP processing and cleaning.................................................................130
              |      A.1       Experimental procedure..............................................................................130
              |      A.2       Results of CMP experiments ......................................................................131
              |      A.3       Attached island isolation (STI variant) process development ....................135
              |      A.4       Post CMP decontamination ........................................................................136
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text          | Appendix B: Epitaxial Germanium Growth Process....................................................138
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text          |    B.1    Experimental procedure of epi-Ge growth .................................................139
              |    B.2    Characterizing epi-Ge surface quality ........................................................140
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text          | Bibliography        ........................................................................................................142
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title         | List of Tables
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text          | Table 2.1: Summary of graphoepitaxy experiments from literature (top half)
              |           [93,68,73,98], and from this work (bottom half)..........................................49
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text          | Table 4.1: Summary of Al-Ge eutectic bonding conditions: all bonding tests were
              |           performed utilizing both one and two-sided configurations. *For the 400 °C
              |           tests, bonding time was set to 120 minutes...................................................64
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text          | Table 5.1: Wafer saw dicing test results for Cu-Cu bonded Si wafers at various
              |           conditions. K&S 775 wafer dicing saw was used to cut 5mm x 5mm dies
              |           with a resinoid blade spinning at 20k rpm and feed rate of 1 mm/s.............89
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text          | Table 8.1: Summary of low-temperature bonding techniques for monolithic 3D
              |           integration. ..................................................................................................126
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title         | List of Figures
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text          | Figure 1.1: a) Interconnect delay as a function of technology generation for different
              |            architectures. Interconnect delay limits the 2D IC performance, but promises
              |            significant reduction with 3D integration [2]; b) Power consumption by the
              |            MPU interconnects grows with successive generations [1]. The data is
              |            normalized to a constant VDD to reflect the effects of interconnect scaling. 1
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text          | Figure 1.2: Three-dimensional integrated circuit (3DIC). Multiple layers of active
              |            devices are stacked and connected vertically at the transistor level [15]. ......2
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text          | Figure 1.3: Chip stacking approach to 3DIC with peripheral interconnections between
              |            layers (achieving density <10 mm-2): a) STATS ChipPAC [17]; b) Neo-
              |            Stack flash memory from Irvine Sensors [18]................................................3
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text          | Figure 1.4: Elpida 8-Gbit DRAM with TSV Cu connections between dies [19]. ............4
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text          | Figure 1.5: Die-on-wafer stacking with 8 µm vertical interconnect pitch achieved by
              |            simultaneous Cu-Cu and direct oxide bonding (DBI®) [25]. .........................4
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text          | Figure 1.6: SEM cross-section of 3-layer 3DIC from Tezzaron showing deep Cu
              |            SuperVias® connecting device layers that have been thinned to ~15 µm
              |            [26]..................................................................................................................5
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text          | Figure 1.7: MIT Lincoln Lab’s 3DIC process: (a) Two completed circuit wafers are
              |            planarised, aligned, and bonded face to face; (b) the handle silicon is
              |            removed; (c) 3D vias are etched through the deposited BOX and the field
              |            oxides; (d) tungsten plugs are formed to connect circuits in both tiers; and
              |            (e) after tier 3 is transferred, bond pads are etched through the BOX for
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text          |            testing and packaging. Vertical interconnect density of around 3x104 mm-2
              |            has been demonstrated [28]. ...........................................................................6
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text          | Figure 1.8: Cross-sectional SEM of a functional three-tier ring oscillator showing
              |            tungsten plug 3D-vias as well as conventional inter-level connections [30]..7
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text          | Figure 1.9: IBM 3DIC process: a) transparent handling wafer with an active layer of
              |            devices; b) shallow 3D vias are made post-bonding allowing for high
              |            density [33]. ....................................................................................................8
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text          | Figure 1.10: Monolithic 3DIC process flow (not to scale): first layer is fabricated and
              |            the amorphous surface planarized. High quality semiconductor material is
              |            either bonded or deposited and crystallized on top. Finally, devices are
              |            fabricated in the second layer, and inter-layer connections made [15]. .........9
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text          | Figure 1.11: Three level monolithic 3DIC with upper layers obtained via solid-phase
              |            crystallization (Mitsubishi, 1986) [44] .........................................................10
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text          | Figure 2.1: SEM (plan view) of KCl crystallites on square-wave grating in amorphous
              |            SiO2 showing oriented crystal growth where <100> directions are parallel to
              |            the gratings [70]............................................................................................16
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text          | Figure 2.2: a) Square-wave relief structure results in (100) textured film, with <100>
              |            in-plane orientation of cubic crystals; b) Saw-tooth pattern is amenable to
              |            (111) planes of the diamond cubic crystal structure of group IV elements
              |            such as Si and Ge [69]. .................................................................................18
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text          | Figure 2.3: Vapour deposited Ge crystallites preferentially nucleate on the corners of a
              |            square-grating template etched in amorphous SiO2: a) XTEM; b) plan view
              |            SEM. Note: SiO2 grating was covered with a self-assembled monolayer
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text          |            (SAM) of octadecyltrichlorosilane (OTS) to facilitate Ge nucleation. Images
              |            obtained in collaboration with T.I. Kamins et al. [87]. ................................18
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text          | Figure 2.4: Sequence of growth for a cubic crystalline material on a square-wave
              |            structure with perfect ‘decoration’ where all the oriented nucleation occurs
              |            at the steps, and random nucleation in between the steps is suppressed
              |            [70]…............................................................................................................19
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text          | Figure 2.5: a) Graphoepitaxy of 500nm thick Si films on fused silica grating (3.8μm
              |            pitch, 0.1μm depth). After heating the substrate to 1000+ °C, the scanning
              |            IR lamp melted the Si film, which then recrystallized into preferentially
              |            oriented Si (100) grains, with in-plane orientation also (100) along the
              |            grating [68]. ..................................................................................................20
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text          | Figure 2.6: One dimensional simulation results: thermal profile evolution due to a 15 µs
              |            laser pulse anneal demonstrating complete melting of 100 nm thick α-Si
              |            layer while maintaining sub-450 °C temperature in underlying layers (5 µm
              |            below α-Si). ..................................................................................................21
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text          | Figure 2.7: Laser annealing apparatus: Nd:YAG power laser at λ = 532 nm is acousto-
              |            optically modulated into pulses and guided onto the sample placed on X-Y
              |            stage. The Gaussian beam is focused through a Mitutoyo objective (NA =
              |            0.90) creating a beam spot of various FWHM diameters (10-32 µm) [89]..22
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text          | Figure 2.8: a) AFM image and section analysis of the grating pattern etched in SiO2
              |            using nanoimprint lithography (190 nm pitch, 70 nm linewidth); b) TEM
              |            cross-section of the final structure showing nanoimprinted grating in thermal
              |            SiO2 (190 nm pitch, 30 nm linewidth) covered with LPCVD layer of α-Si
              |            (100 nm thick) followed by a capping layer of LTO (170 nm thick). ..........23
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text          | Figure 2.9: a) TEM cross-section of the melt zone for 500 nm thick Si film with 1.2 μm
              |           LTO capping layer. Laser was in continuous-wave mode (non-scanning)
              |           with spot size 15 μm FWHM; b) individual crystal grains visible near the
              |           center of the laser beam; c) solid phase crystallization region; d) as
              |           deposited α-Si layer away from the laser beam............................................24
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text          | Figure 2.10: TEM cross-section of recrystallized Si film (100nm thick) on NIL
              |           patterned grating in SiO2 (190 nm pitch, 30 nm linewidth). Individual grain
              |           boundaries emanating from the periodic NIL gratings are clearly visible. ..25
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text          | Figure 2.11: TEM cross-section of α-Si film (500 nm) deposited by LPCVD at 585 °C
              |           for 90 min over the patterned SiO2, showing small Si crystallites around the
              |           nano-grating. Due to their higher melting temperature than α-Si, these bits
              |           of crystal may effectively ‘mask’ the SiO2 grating. .....................................26
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text          | Figure 2.12: HRTEM cross-section of the LPCVD deposited amorphous Si-SiO2
              |           heterogeneous interface. Si film deposited at 585 °C shows small crystallites
              |           present at the interface, while at 525 °C their formation is significantly
              |           suppressed.....................................................................................................27
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text          | Figure 2.13: a) Cross-sectional TEM image of the fabricated sample illustrating the
              |           sharp, lattice defined corners of template (rc < 5nm); b) corresponding
              |           schematic cross-section of the 500 nm inverted pyramid template sample c)
              |           Top view SEM of the 2D inverted pyramid array with the LTO cap removed
              |           for imaging....................................................................................................30
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text          | Figure 2.14: a) Cross-sectional SEM image of the delaminated LTO cap after 100 µs
              |           pulse laser anneal; b) The cause of cap delamination can be seen in the top
              |           view SEM of the annealed area. Agglomerated silicon islands cluster around
              |           the middle of irradiated area due to de-wetting of molten Si film on SiO2
              |           surface...........................................................................................................31
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text          | Figure 2.15: TEM cross-section of the 50 nm thick silicon film just outside of the
              |            melted region shows fine grain polycrystalline structure formed by solid
              |            phase crystallization......................................................................................32
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text          | Figure 2.16: TEM cross-section of the agglomerated silicon island after a 100 µs pulse
              |            laser anneal. Red arrows indicate out-of-plane orientation. In addition, all
              |            grains have in-plane orientation matching the 2D template, demonstrating a
              |            high degree of graphoepitaxial orientation. ..................................................33
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text          | Figure 2.17: HRTEM cross-section of a defect free recrystallized grain terminating at a
              |            (111) twin grain boundary. Inset: microdiffraction (CBED) pattern affirms
              |            the excellent crystal quality of the recrystallized silicon grain.....................34
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text          | Figure 2.18: TEM cross-section of the annealed structure. Atomically flat silicon (111)
              |            plane ‘walls’ of the pyramids have become wavy following the 100 µs
              |            pulsed laser anneal indicating substrate melting took place.........................35
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text          | Figure 2.19: a) TEM cross-section of the agglomerated silicon film after a 100 µs pulse
              |            laser anneal; b) the crystallized grain has in-plane orientation matching that
              |            of Si substrate, while the out-of-plane orientation is twinned along <111>
              |            plane, making it 70.6° off from <100> Si substrate. The thin grain
              |            emanating from the corner of the template is graphoepitaxially oriented
              |            (matches the Si substrate exactly).................................................................36
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text          | Figure 2.20: One-dimensional simulation results: thermal profile evolution due to a 10
              |            µs laser pulse anneal. Top curve illustrates slow cooling rates of 50 nm thick
              |            silicon film with 1000 °C substrate biasing, limiting the undercooling the
              |            film experiences compared to the case of non-temperature biased sample..37
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text          | Figure 2.21: Glancing angle XRD spectra of thermally annealed 60 nm thick Si films
              |            on NIL patterned and flat (control) SiO2 substrates: a) after 24 hours at 600
              |            °C, b) after 24 hours at 1100 °C. Note, the errors in spectra at lower
              |            reciprocal space coordinates is due to imperfect subtraction of the SiO2
              |            background X-ray peak.................................................................................40
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text          | Figure 2.22: a) TEM cross-section of 60 nm α-Si film on NIL patterned nano-grating in
              |            fused silica (SiO2) substrate. Solid phase crystallization takes place after: b)
              |            24 hours at 600 °C; c) 1 hour at 1100 °C; d) 24 hours at 1100 °C. ..............42
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text          | Figure 2.23: Cross-sectional TEM of excimer laser (KrF) annealed α-Si film on SiO2
              |            nano-grating 1D template: a) after single 34 ns pulse at 192 mJ/cm2; b) dark
              |            field image of recrystallized film after 136 mJ/cm2. ....................................44
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text          | Figure 2.24: Rastered laser scan annealing of α-Ge film on top of SiO2 1-D grating. The
              |            SEM image contrast delineates the zigzag shape of crystallized Ge grains.
              |            Note: 100nm thick SiO2 cap has been removed for imaging purposes. .......45
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text          | Figure 2.25: a) SEM image of α-Ge film on SiO2 grating after scanned laser anneal; b)
              |            resulting EBSD map of out-of-plane crystal orientation, with inverse pole
              |            plot (each grain colour corresponds to specific crystal orientation).............46
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text          | Figure 3.1: Nucleation mechanisms in liquid material in solid (SiO2) container. ΔGV is
              |            the absolute value of the Gibbs free energy change per unit volume
              |            associated with the liquid-solid phase transformation, γls is the liquid-solid
              |            interface energy, while γsw and γlw are interface energy related to the SiO2
              |            container wall................................................................................................51
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text          | Figure 3.2: Even though the size of the critical nucleus (r*) is the same, the nucleation
              |            energy barrier for heterogeneous integration (ΔG*Het) is lower than that of
              |            homogeneous nucleation (ΔG*Het) by a factor S(θ).......................................52
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text          | Figure 3.3: Homogeneous (red) and heterogeneous (blue) nucleation rates in
              |            undercooled Ge liquid stripe (40x1x0.1µm) surrounded by SiO2 as a
              |            function of temperature: a) log scale; b) linear scale....................................53
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text          | Figure 3.4: a) Simplified test structure for 1-D thermal diffusion modeling, as well as
              |            nucleation and grain growth model; b) cross-section of fabricated structure
              |            showing attached Si (100) seed and α-Ge thin stripe to be laser crystallized.
              |            (Not to scale).................................................................................................54
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text          | Figure 3.5: a) Single pulse (~40ns) laser anneal of 180 mJ/cm2 is used to melt 120 nm
              |            thick α-Ge stripe; b) liquid Ge at 937 °C undercools as the heat diffuses to
              |            Si substrate; c) simulation result: spontaneous heterogeneous nucleation
              |            crystallizes the liquid into polycrystalline germanium.................................56
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text          | Figure 3.6: TEM cross-section of laser annealed Ge stripe indicating polycrystalline
              |            structure due to spontaneous nucleation in deeply undercooled Ge liquid. .57
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text          | Figure 3.7: Laser annealed Ge stripe crystallization with a Si (100) seed: a) simulation
              |            result: seeded epitaxial growth gets interrupted by spontaneous nucleation;
              |            b) TEM cross-section of the test structure annealed by a single 180 mJ/cm2
              |            pulse agrees with the simulation result; c) epitaxially grown Ge (100) grain
              |            with corresponding SAD pattern; d) fine grain poly-Ge region seeded by
              |            spontaneous heterogeneous nucleation.........................................................58
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text          | Figure 3.8: RTA anneal (960 °C, 1 sec) of Ge stripe crystallization with a Si (100) seed:
              |            a) both simulation and the test structure show unimpeded grain growth of
              |            seeded Ge(100), up to 40 µm long; b) HR XTEM demonstrating high-
              |            quality defect-free Ge (100) grain on SiO2 substrate with corresponding
              |            single crystal SAD pattern c)........................................................................59
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              | 
              | 
              | 
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text          | Figure 4.1: Aluminum-germanium binary alloy phase diagram. Even though pure Al
              |           melts at 600°C, and pure Ge close to 940°C, the eutectic alloy of 30.3% Ge
              |           in Al melts at a significantly lower temperature of 424 °C [125]. ...............61
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              | 
text          | Figure 4.2: a) AFM scan (5x5 µm) of as-deposited bilayer (30nm Al + 17nm Ge) with
              |           surface roughness of 1.63nm RMS; b) FIB cross-section of evaporated Al-
              |           Ge stack (300nm Al + 175nm Ge) on top of SiO2 diffusion barrier. Note: the
              |           Ge surface roughness in (b) is due to Ga+ ion milling process (FIB)...........63
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              | 
text          | Figure 4.3: Wafer flat area of 4-inch wafer pair bonded at 450°C showing a small drop
              |           of solidified Al-Ge alloy that has been squeezed out during the bonding step.
              |           Thus, Al-Ge bilayer alloy does indeed melt above eutectic temperature. ....65
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              | 
text          | Figure 4.4: a) Double cantilever beam technique sample schematic showing the debond
              |           length caused by tension forces applied at the end of the beams through
              |           metal tabs (b). ...............................................................................................66
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              | 
text          | Figure 4.5: Measured bond strength of copper-copper bond under pure Mode I tension
              |           is about Gc = 2.5 J/m2 [134]. This value is much smaller compared to
              |           measured Al-Ge bond fracture energy of Gc = 50 J/m2 [133]. .....................67
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              | 
text          | Figure 4.6: Scanning acoustic microscope (SAM) image of 4-inch wafer pair bonded at
              |           435 °C with 2.2 kN applied force (200 kPa) for 30 min (condition A). The
              |           Al-Ge eutectic bonding achieves a nearly void-free bond, with a single
              |           defect (white) in the center due to a known pressure weak spot. Note: white
              |           areas are voids, black areas are solid bond, while the faint grey lines are due
              |           to Ge dendrites..............................................................................................68
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              | 
text          | Figure 4.7: Map of pressure distribution over a 4-inch wafer placed under 3.3 kN
              |           downward force (350 kPa) applied by the bonder. Measurement was
              |           performed using Pressurex® pressure sensitive paper. .................................69
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              | 
meta          |                                                                                                                     xviii
text          | Figure 4.8: Plan-view optical (a) and SEM (b) images showing the microstructure of
              |           the Al-Ge eutectic bond formed at 450 °C (condition A). The top wafer has
              |           been ground and etched away to reveal Al-Ge layer segregated into
              |           germanium dendrites (light grey) within an aluminum matrix (dark grey)..70
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              | 
text          | Figure 4.9: AES elemental map of Al-Ge eutectic bond formed at 450°C. As the bond
              |           is cooled, the eutectic alloy segregates into solid Ge dendrites in an Al
              |           matrix............................................................................................................70
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              | 
text          | Figure 4.10: Auger depth profile of Al-Ge eutectic bond formed at 450 °C, after
              |           backside grinding and etching. The dendritic phase separation occurs
              |           vertically as well, forming six alternating layers of Al and Ge upon
              |           solidification of eutectic melt. .....................................................................71
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              | 
text          | Figure 4.11: Cross-section TEM of Al-Ge eutectic bond formed at 435 °C in 1 hour.
              |           The void-free bonding layer consists of laterally segregated Al and Ge
              |           domains that span the thickness of the film (~100nm), as indicated by the
              |           local EDS spectra shown. .............................................................................72
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              | 
text          | Figure 4.12: TEM cross-section of Al-Ge eutectic bond layer: a) Al forms long (up to
              |           10 μm) grains while Ge is polycrystalline; b) HRTEM of Al crystal lattice
              |           fringes with a single stacking fault defect shown.........................................73
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              | 
text          | Figure 4.13: Schematic (not to scale) showing: a) one-sided Al-Ge eutectic bonding of
              |           20 µm polysilicon islands; b) razor blade spitting of bonded wafers via SiO2
              |           pedestal fracture. Note: Si3N4 diffusion barrier on polysilicon islands is
              |           marked in red. ...............................................................................................74
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              | 
              | 
              | 
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text          | Figure 4.14: SEM of an array of polysilicon islands attached to a SiO2 substrate using
              |           Al-Ge eutectic bonding at 435 °C. The excess Al-Ge in between the islands
              |           has been etched away in phosphoric, acetic, nitric acid solution (PAN)......75
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              | 
text          | Figure 4.15: Cross-sectional SEM of the Al-Ge bonding interface between the
              |           polysilicon island and the oxidized Si substrate, showing seamless and void-
              |           free attachment. A full 20 µm cross section examined contained no voids. 75
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              | 
text          | Figure 4.16: Rough (4.3 nm RMS over 5x5 µm area) polysilicon island (with 100 nm
              |           LPCVD SiO2 diffusion barrier) is successfully bonded onto oxidized Si
              |           substrate via Al-Ge eutectic bonding (435 °C, 200 kPa)..............................76
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              | 
text          | Figure 4.17: Bright field X-TEM images of GeOI preparation: a) H+ implant damage in
              |           bulk Ge; b) hydrogen blisters appear upon annealing; c) fusion bonded and
              |           exfoliated Ge film [83]. ................................................................................77
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              | 
text          | Figure 4.18: Al-Ge bonding of Si islands for monolithic 3DICs: a) thermally oxidized
              |           Si (100) donor wafer is implanted with H+ ions (6x1016 cm-2, 75 keV, Rp=
              |           630 nm) for eventual SmartCut®; b) donor islands are patterned; c) 157 nm
              |           thick Al-Ge bilayer is evaporated onto an oxidized Si acceptor wafer and
              |           patterned into pads; d) donor and acceptor wafers to be bonded are placed
              |           face-to-face; e) Al-Ge eutectic bonding takes place at 435 °C and 200 kPa
              |           pressure for 30 minutes; f) donor wafer is split away using SmartCut®
              |           process; g) the splitting process leaves surface roughness that is removed
              |           with CMP (h); i) resulting in single crystalline Si (100) islands on top of
              |           amorphous SiO2 acceptor wafer. ..................................................................78
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              | 
text          | Figure 4.19: a) SEM of Si islands on the donor wafer implanted with H+ and ready to
              |           bond; b) IR camera image of the Al-Ge bonded 4-inch wafers (with Si
              |           islands visible). .............................................................................................79
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              | 
              | 
              | 
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text          | Figure 4.20: a) SEM image of 10 µm Si crystal island bonded to SiO2 via Al-Ge
              |            eutectic bonding at 435 °C; b) optical image of 50 µm Ge (100) island on
              |            SiO2 with Al-Ge bond pad visible (bright area). CMP step is needed to
              |            remove surface roughness.............................................................................80
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              | 
text          | Figure 4.21: Sub-eutectic Al-Ge bond at 400 °C. The mating wafers had 475 nm thick
              |            Al-Ge bilayer each, and were bonded for 2 hours at 350 kPa down-
              |            pressure... ......................................................................................................81
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              | 
text          | Figure 4.22: Silicon (100) island attached to SiO2 wafer via sub-eutectic Al-Ge bond at
              |            400 °C. Donor wafer has been successfully removed via SmartCut®. .........82
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              | 
text          | Figure 5.1: 5x5 µm AFM scan of 300 nm thick Cu film evaporated at: a) 0.3 nm/s rate,
              |            b) 0.9 nm/s rate. Root-mean-square (RMS) surface roughness is not affected
              |            by deposition rate..........................................................................................85
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              | 
text          | Figure 5.2: Copper metal surface roughening by dilute HCl solution: a) as deposited; b)
              |            30 sec, and c) 60 sec. AFM scans are of 5x5 µm area..................................86
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              | 
text          | Figure 5.3: Diagram of Cu-Cu bonding of Si for monolithic 3DICs: a) Si (100) donor
              |            wafer is implanted with H+ ions for eventual SmartCut; b) 300 nm thick Cu
              |            layer (with 30 nm Ta diffusion barrier) is evaporated on both donor and an
              |            oxidized Si acceptor wafers; c) donor and acceptor wafers to be bonded are
              |            placed face-to-face; d) Cu-Cu bonding takes place at 400 °C and 400 kPa
              |            pressure for 30 minutes; e) donor wafer is split away using SmartCut
              |            process; f) resulting single crystalline Si (100) layer on top of amorphous
              |            SiO2 acceptor wafer. .....................................................................................87
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              | 
text          | Figure 5.4: Dicing test results for Cu-Cu bonded 4” Si wafers at 350 °C (Sample 2).
              |            Two brown squares are two 5x5 mm square dies debonded during sawing.88
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              | 
              | 
              | 
meta          |                                                                                                                           xxi
text          | Figure 5.5: Cross-sectional SEM of the acceptor wafer illustrating successful transfer of
              |            ~600 nm thick Si crystalline film on top of amorphous substrate (SiO2) via
              |            Cu-Cu bonding at 400°C. Note: the top of the Si transferred layer exhibits
              |            Ga+ ion damage incurred during sample preparation (FIB), and not the
              |            SmartCut process. .........................................................................................90
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              | 
text          | Figure 5.6: Cross-sectional SEM of germanium crystalline film bonded onto SiO2 wafer
              |            via 400 °C Cu-Cu bond. Copper grains are clearly visible, while the two
              |            bright stripes lining the copper bond are 40 nm thick tantalum (Ta) diffusion
              |            barriers. Note: this sample was prepared using JEOL SM Ion polisher (Ar+),
              |            and the Ge surface roughness is due to SmartCut splitting process. ............91
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              | 
text          | Figure 5.7: Cross-sectional SEM illustrating the morphology of the Cu-Cu bond (at 400
              |            °C) used to attach Ge (100) crystalline film. There are very few interfacial
              |            voids and the large copper grains have completely erased the original
              |            bonding interface. .........................................................................................92
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              | 
text          | Figure 5.8: Copper bonded post-transfer images of: a) 4-inch Si donor wafer after
              |            splitting; b) 4-inch oxidized Si acceptor wafer with bonded crystalline Si
              |            (100) film (appears pink). Note that the non-bonded areas still have reddish
              |            Cu film visible. .............................................................................................92
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              | 
text          | Figure 5.9: Cu-Cu thermo-compressive bonding of rough epi-Ge (3.2 nm RMS) to an
              |            oxidized Si prime wafer at 400 °C: a) Scanning acoustic microscope (SAM)
              |            image of the bonded pair showing interfacial voids in white and bonded
              |            areas in black; b) raw image of the pressure sensitive paper indicating
              |            uneven pressure distribution applied over the 4-inch wafer; c) resulting
              |            acceptor wafer after SmartCut splitting, exhibiting incomplete transfer of Ge
              |            crystal film (light grey colour)......................................................................93
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              | 
              | 
              | 
meta          |                                                                                                                      xxii
text          | Figure 6.1: HRTEM image of Ti/Ti bonded wafers, showing titanium grain growth
              |            across the original interface [164]. ...............................................................96
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              | 
text          | Figure 6.2: Diagram of Ti/Ti bonding of Si islands and subsequent removal of the bulk
              |            donor wafer using SmartCut®, leaving behind an array of Si (100) crystal
              |            islands on top of SiO2. ..................................................................................97
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              | 
text          | Figure 6.3: AFM (1x1 µm) surface roughness scans of 40 nm deposited Ti on Si prime
              |            substrate, indicating a smoother film was achieved by evaporation (0.69 nm
              |            RMS). The e-beam evaporation deposition rate was 0.15 nm/s, while that of
              |            Ar ion sputtering Ti deposition rate was 0.4 nm/s........................................98
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              | 
text          | Figure 6.4: Optical image of Si crystal islands (light areas) attached to SiO2 acceptor
              |            wafer after Ti/Ti bonding and donor wafer splitting. ...................................99
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              | 
text          | Figure 6.5: Photo of 4-inch acceptor wafer with Si islands attached (green) via Ti-Ti
              |            bonding. The brown-coloured edges are exposed Ti surface that has been
              |            inadvertently oxidized. ...............................................................................100
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              | 
text          | Figure 6.6: SEM image of Ti/Ti bonded Si island on the SiO2 acceptor wafer. The
              |            resulting height of the island is 630 nm, while the surface roughness is the
              |            result of hydrogen ion induced splitting. ....................................................101
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              | 
text          | Figure 6.7: Ti-bonded epi-Ge (100) islands on SiO2 substrates, showing incomplete
              |            transfer. Rounded dark areas are transferred Ge crystals, while the bright
              |            area is the non-bonded Ti layer. The intended square shape of large Ge
              |            islands can be discerned..............................................................................101
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              | 
text          | Figure 6.8: AFM (20x20 µm) scan of epi-Ge layer (1 µm thick), after multiple 800°C
              |            hydrogen anneals. The resulting roughness is 2.03nm root mean square
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              | 
              | 
              | 
meta          |                                                                                                                  xxiii
text          |           (rms) with Z range being 12.1 nm. Note: diagonal line visible is a crystal
              |           defect (boundary)........................................................................................102
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              | 
text          | Figure 7.1: Mechanism of hydrophilic fusion bonding: a) interfacial monolayers of
              |           water (H2O) bridge the wafers by hydrogen bonding to surface silanol
              |           groups (Si–OH); b) water molecules rearrange, accommodating surface
              |           roughness; c) at points of close contact, direct hydrogen bonding between
              |           OH groups occurs; d) the silanol groups polymerize forming much stronger
              |           siloxane bonds (reversible reaction up to 425 °C)......................................105
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              | 
text          | Figure 7.2: SiO2 surface schematic showing a single silanol                                    (Si–OH) bond. Wet
              |           chemical activation could increase the density of silanol bonds by breaking
              |           the covalent Si–O–Si bonds of the silica matrix.........................................108
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              | 
text          | Figure 7.3: Water contact angle as a function of different silicon surface treatments.
              |           The degree of activation (hydrophilic surface) is greatest when the contact
              |           angle is smallest. Note: RCA-1 treatment is NH4OH:H2O2:H2O (1:1:5) at 80
              |           °C, while RCA-2 treatment is composed of HCl:H2O2:H2O (1:1:6) at 80°C
              |           [79]..............................................................................................................109
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              | 
text          | Figure 7.4: Tapping-mode AFM scans (5x5 µm) demonstrating surface roughness
              |           (RMS) of various SiO2 films (200nm thick). Note: vertical scale has a range
              |           of 5 nm except for TEOS sample (30 nm)..................................................111
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              | 
text          | Figure 7.5: Infrared (IR) image of hydrophilic fusion bonded 4” wafer pair, after 36
              |           hour anneal at 400 °C. a) Si bonded to thermal SiO2 is almost void-free,
              |           while b) Si bonded to PECVD SiO2 shows many particle induced voids
              |           (appear as Newton’s rings). ........................................................................112
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              | 
              | 
              | 
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text          | Figure 7.6: AFM scans (5x5 µm) depicting surface roughness of as deposited LPCVD
              |            SiO2 (LTO) and the smoothening effect of CMP treatment for 60 and 180
              |            seconds........................................................................................................112
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              | 
text          | Figure 7.7: RMS surface roughness of low temperature oxide (LTO) deposited at 300
              |            °C as a function of CMP polish time. Within 1 minute, the roughness is
              |            reduced below the requirement for successful fusion bonding (0.5 nm
              |            RMS)...........................................................................................................113
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              | 
text          | Figure 7.8: IR camera images of interfacial voids present between Si-Si, Si-SiO2 and Si
              |            islands-SiO2 wafer pairs, after various thermal anneals. Si-SiO2 pairs had
              |            significantly fewer thermally induced voids than the Si-Si pair, while the
              |            island wafers produced no voids at all........................................................115
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              | 
text          | Figure 7.9: Post-SmartCut SiO2 acceptor 4” wafers with: a) transferred crystalline
              |            silicon film (pink colour) ~600 nm thick, after SiO2-SiO2 hydrophilic fusion
              |            bonding and 48 hour anneal at 200°C; b) an array of Si-SiO2 fusion bonded
              |            Si (100) islands on top of thermal SiO2 (blue colour). Post-bonding anneal
              |            was at 400 °C for 22 hours. ........................................................................116
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              | 
text          | Figure 7.10: SEM of 3 µm sized Si (100) islands fusion bonded onto SiO2. Optical
              |            images on the right illustrate successfully attached arrays of square islands
              |            with sizes from 3 µm to 200+ µm. The thickness of Si islands after
              |            SmartCut is ~ 630nm. .................................................................................117
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              | 
text          | Figure 7.11: Optical images of Ge (100) layer fusion bonded to SiO2. By patterning Ge
              |            into 300x300 µm islands (b), the number of thermally induced voids is
              |            reduced compared to the full wafer transfer (a). The channel width between
              |            the islands is 10 µm. ...................................................................................118
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              | 
              | 
              | 
meta          |                                                                                                                         xxv
text          | Figure 7.12: AFM scan (5x5 µm) of Si island surface after hydrogen-induced splitting
              |           (SmartCut®). The rough and damaged surface becomes smooth after 30 sec
              |           of CMP........................................................................................................118
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              | 
text          | Figure 7.13: a) 4-inch SiO2 wafer with an array of Ge (100) islands attached via Ge-
              |           SiO2 fusion bonding and 400 °C anneal. The donor wafer was removed via
              |           SmartCut, while the islands were polished by CMP, leaving behind device-
              |           ready Ge (100) islands on SiO2. .................................................................119
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              | 
text          | Figure 7.14: a) Crack opening method of bonding-energy measurement consists of
              |           inserting a blade between bonded wafers, and measuring the length (L) of
              |           resulting delamination; b) IR image of fusion bonded Si-SiO2 wafers with a
              |           razor blade inserted. The darker shade area of delamination is clearly
              |           visible..........................................................................................................120
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              | 
text          | Figure 7.15: Local elastic deformation of mating wafers could yield to ‘ceiling
              |           collapse’ causing undesired fusion bond in certain areas...........................122
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              | 
text          | Figure 8.1: Area reduction of an FPGA circuit in a 3-layer implementation (LB – logic
              |           block; CB – connection block; SB – switch block); a) 2D layout; b) 3D
              |           layout, with memory split out of SBs onto a separate 3rd layer. The vertical
              |           integration of three distinct blocks substantially reduces circuit area
              |           [189]…........................................................................................................127
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              | 
text          | Figure 8.2: Three-dimensional FPGA implementation pursued by Stanford University.
              |           Switching devices in the 2nd layer are Ge MOSFETs, while the third layer
              |           consists of resistance-change memory (RCM) cells...................................128
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              | 
text          | Figure A.1: Time progression of CMP polish of Si (100) islands (50% fill ratio) using
              |           Ultra-Sol S10 slurry with table/head speed of 60/30 rpm, and polishing
              |           pressure of 200 psi. .....................................................................................132
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              | 
meta          |                                                                                                                        xxvi
text          | Figure A.2: CMP of Si (100) islands leaves speckled slurry residue (a), which can be
              |            removed by wet PVA sponge scrub (b), bringing the surface roughness to
              |            0.416 nm RMS. Reference Si prime wafer (c). All AFM scans are 5x5
              |            µm…. ..........................................................................................................133
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              | 
text          | Figure A.3: Time progression of CMP polish of LPCVD deposited SiO2 (LTO) using
              |            Ultra-Sol 3EX slurry with table/head speed of 60/30 rpm, and polishing
              |            pressure of 200 psi. .....................................................................................133
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              | 
text          | Figure A.4: a) Germanium removal rate vs. H2O2 concentration in slurry [192]; b) AFM
              |            scan (1x1μm) of epi-Ge (100) surface after 60 sec CMP using S10 slurry (no
              |            H2O2). The RMS roughness is 0.158 nm....................................................134
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              | 
text          | Figure A.5: a) LPCVD deposited conformal SiO2 fills the gaps between the attached
              |            crystal islands, and the excess is polished off by CMP; b) poor selectivity
              |            between Si and SiO2 causes severe dishing to occur..................................135
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              | 
text          | Figure A.6: a) CMP of deposited SiO2 dielectric isolation stops once the buried silicon
              |            nitride (SiN) layer is reached; b) cross-sectional SEM of the resulting
              |            planarity between the Si island and the SiO2 filling. ..................................136
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              | 
text          | Figure B.1: a) A 155 nm thick epi-Ge layer grown at 400 °C shows defects at the
              |            heterogeneous interface, while b) illustrates that successive Ge layer growth
              |            (at 400 °C) with hydrogen anneals (at 825 °C) produce a high-quality crystal
              |            near the surface [196]. ................................................................................139
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              | 
text          | Figure B.2: Cross-sectional SEM of grown epi-Ge (100) layer that is 914 nm thick. The
              |            corresponding 20x20 µm AFM scan, indicating 2.03 nm RMS surface
              |            roughness. Note: relief of the epi-Ge layer in the SEM is due to cleaving
              |            process and not due to crystal defects.........................................................140
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              | 
meta          |                                                                                                                      xxvii
text          | Figure B.3: AFM scan (20x20 µm) of 5 layer epi-Ge showing characteristic “cross-
              |           hatch” pattern along the <110> direction with a spatial wavelength of the
              |           order of a micron, superimposed on mounds the size of several microns,
              |           with maximum peak to valley height of ~ 11 nm. The thickness of the epi-
              |           Ge film is 2.2 µm. .......................................................................................141
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              | 
              | 
              | 
meta          |                                                                                                                xxviii
title         | Chapter 1 – Introduction
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title         | 1.1 Motivation
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text          |        As the features of a MOSFET continue with their relentless descent deep into
              | sub-100 nm dimensions, device performance improves with decreasing intrinsic
              | transistor delay [1]. However, simultaneous miniaturization of interconnects does not
              | enhance circuit performance, setting a limitation that potentially threatens to decelerate
              | or halt the historical progression of the conventional (2D) semiconductor circuits
              | (Figure 1.1) [2]. In particular, as the cross-sectional area of metal wires shrinks, the
              | effective resistance increases while their coupling capacitance also grows as they are
              | placed ever closer together. At the same time, growing complexity and circuit area
              | required by new functionalities radically augment both the total number of
              | interconnects and their length. Combined, these factors set scaling limitations such as
              | increased RC delay and power consumption of interconnects (Fig. 1.1) [3].
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              | 
              | 
              | 
text          |  Figure 1.1: a) Interconnect delay as a function of technology generation for different
              | architectures. Interconnect delay limits the 2D IC performance, but promises significant
              |   reduction with 3D integration [2]; b) Power consumption by the MPU interconnects
              |   grows with successive generations [1]. The data is normalized to a constant VDD to
              |                        reflect the effects of interconnect scaling.
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              | 
meta          |                                                                                           1
text          |        Three dimensional integrated circuits (3DICs), where multiple layers of active
              | devices are stacked directly on top of each other, offer an attractive architectural
              | solution to the 2D scaling limitations by offering better packing density, increased
              | performance, and greater functionality (Fig. 1.2) [4-7]. To begin, adding a third
              | dimension to 2D circuits increases density and reduces chip footprint. This is
              | particularly appealing for wireless or portable electronics where silicon real estate is at
              | premium. 3DICs also promise reduced average interconnect length, yielding less RC
              | delay, less power consumption, less noise coupling and enhanced accessible die area [8-
              | 10]. Finally, vertical integration of heterogeneous materials and devices could open the
              | door for hybrid photonic/electronic circuits, combined digital/analog/RF circuits,
              | stacked memory on logic circuits, and other novel system designs [3].
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              | 
              | 
              | 
text          |    Figure 1.2: Three-dimensional integrated circuit (3DIC). Multiple layers of active
              |         devices are stacked and connected vertically at the transistor level [15].
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              | 
text          |        Together with these compelling benefits come certain challenges that need to be
              | addressed before 3D integration becomes accepted as a mainstream technology. Firstly,
              | maintaining device integrity on lower layers during 3DIC fabrication is of crucial
              | importance, where excessive thermal cycling could degrade the electrical integrity of
              | the underlying devices. Secondly, managing increased power densities in tightly packed
              | 3D circuits require new schemes to dissipate power efficiently and minimize thermal
              | stresses [11-13]. Thirdly, new processes need to be developed to precisely align and
              | interconnect multiple layers in order to fully harness 3DIC benefits. If the alignment
              | accuracy is poorer than the critical feature size, limited vertical via density could
              | ultimately diminish the very advantage of going 3D [14]. Finally, due to inherent
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              | 
meta          |                                                                                          2
text          | complexity of 3D circuits novel design tools are necessary to optimize inter-layer
              | connections and maximize circuit performance [16].
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              | 
title         | 1.2 Construction methods for 3-D ICs
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text          |        There are numerous technologies developed to achieve 3D integration. The
              | packaging community has pursued the simplest solution where bare dies are stacked
              | vertically, secured by epoxy or other types of ‘glue’. Companies such as STAT
              | ChipPAC [17] and Irvine Sensors [18] implement wiring between layers as peripheral
              | interconnections, as exemplified in Fig. 1.3.
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              | 
              | 
              | 
text          |  Figure 1.3: Chip stacking approach to 3DIC with peripheral interconnections between
              |             layers (achieving density <10 mm-2): a) STATS ChipPAC [17];
              |                   b) Neo-Stack flash memory from Irvine Sensors [18].
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              | 
text          |        More advanced approaches use through silicon vias (TSV) that connect the dies
              | through the bulk of the silicon electrically, while attaching them together with a ball-
              | grid array pattern of solder bumps. Elpida [19] and Samsung [20] have used this
              | technology to manufacture 8 Gbit and 16 Gbit TSV DRAM by stacking 8 thinned dies
              | with 1030 vertical interconnects (Fig. 1.4). Overall, these packaging solutions are viable
              | for applications where interconnect density is not large, with maximum vertical
              | interconnect pitch of 100 μm yielding about 102 mm-2 density.
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              | 
              | 
              | 
meta          |                                                                                         3
text          |     Figure 1.4: Elpida 8-Gbit DRAM with TSV Cu connections between dies [19].
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              | 
text          |        The next level of sophistication is die-on-wafer stacking, where known good
              | dies (KGD) are bonded on top a wafer containing other KGD sites. After thinning good
              | dies are bonded using organic glues, oxide bonding or metal (Cu-Cu) bonding, with
              | aligned vertical interconnects. Given the placement accuracy of about 10 μm [21],
              | higher interconnect density can be achieved (102-103 mm-2) [22] with possibility of
              | stacking mixed substrates as long as process temperatures are kept low to avoid unequal
              | expansion. ZyCube has reported three-layer devices using through-die vias, adhesive
              | bonding and micro bumps [23], while Ziptronix uses a process of simultaneous oxide
              | and Cu-Cu bonding [24] and have reduced interconnect pitch down to 8 μm with their
              | DBI® technology at only 350 °C thermal budget [25].
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              | 
              | 
              | 
text          |  Figure 1.5: Die-on-wafer stacking with 8 µm vertical interconnect pitch achieved by
              |               simultaneous Cu-Cu and direct oxide bonding (DBI®) [25].
blank         | 
              | 
text          |        While intra-chip connections in 3D package and die-on-wafer are shorter than
              | standard off chip wires, to take advantage of potential gains from true 3DICs, devices
blank         | 
              | 
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text          | must be brought even closer together. Wafer stacking approaches, however, can lead to
              | much smaller vertical interconnect pitch, and correspondingly higher density. In this
              | method, pre-fabricated wafers with devices and metalization are planarised and attached
              | face-to-face using copper-copper bonding of vertical interconnects, usually at 400-450
              | °C [26]. The back surface of the top layer is thinned to less than 15 μm exposing deep
              | SuperVias® filled with Cu, allowing to extend the process and stack multiple layers
              | (Fig. 1.6). Inter-layer alignment accuracy, as well as management of thermal expansion
              | of substrates during bonding (warping) ultimately set the limits of this technique.
              | Tezzaron’s process consistently achieves alignment accuracy of less than ±1 μm (3σ)
              | across 200 mm wafer [27], allowing for Cu vias of only 1.2 μm width and 2.4 μm pitch
              | for face-to-face bonding [26], reaching 105 mm-2 vertical interconnect density with
              | stacks up to four layers thick. While an impressive feat, it is far from the 2D global
              | wiring pitch of 0.25 μm for the 65 nm technology node (ITRS) [1].
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              | 
              | 
              | 
text          |     Figure 1.6: SEM cross-section of 3-layer 3DIC from Tezzaron showing deep Cu
              |      SuperVias® connecting device layers that have been thinned to ~15 μm [26].
blank         | 
              | 
text          | Since the largest impact on 3D via pitch, and therefore density, in wafer stacking
              | technology is due to the wafer-to-wafer overlay tolerance, an alternative approach to
              | form vias after bonding has been pursued by MIT Lincoln Labs, IBM and others [28]
              | (Fig. 1.7). At MIT, fully fabricated SOI wafer pair was oxide-oxide bonded at 150-275
              | °C achieving ±0.5 µm (3σ) overlay tolerance over 150 mm diameter [29] (Fig. 1.8).
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              | 
              | 
              | 
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text          | Figure 1.7: MIT Lincoln Lab’s 3DIC process: (a) Two completed circuit wafers are
              |   planarised, aligned, and bonded face to face; (b) the handle silicon is removed;
              | (c) 3D vias are etched through the deposited BOX and the field oxides; (d) tungsten
              | plugs are formed to connect circuits in both tiers; and (e) after tier 3 is transferred,
              |     bond pads are etched through the BOX for testing and packaging. Vertical
              |       interconnect density of around 3x104 mm-2 has been demonstrated [28].
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              | 
              | 
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text          |    Figure 1.8: Cross-sectional SEM of a functional three-tier ring oscillator showing
              |       tungsten plug 3D-vias as well as conventional inter-level connections [30].
blank         | 
              | 
text          | Once the bond was complete, the subsequent tungsten 3D vias could be placed with
              | overlay alignment accuracy of optical lithography, allowing for much smaller size
              | (~1µm diameter) and finer pitch (3.4 µm) [30]. Such technology was utilized to
              | demonstrate first functional 3-layer ICs with active devices on all layers, with a
              | megapixel CMOS 3-D image sensor featuring 100% pixel fill factor [31] and a 3-D
              | laser radar imager [32]. IBM has demonstrated a similar process, except that they rely
              | on a glass handle wafer to transfer fully fabricated SOI device layer (~7µm) onto the 3D
              | stack [33]. The transparent handle wafer allows for through-wafer optical alignment and
              | is easily released by laser ablation of the blanket adhesive layer upon bonding (Fig.
              | 1.9). In addition, the Rensselaer Polytechnic (RPI) approach using polymeric glues such
              | as BCB to bond full wafers of active devices at 300 °C is promising [34], but suffers
              | from outgassing, delamination and alignment limitations. The essence of via-last
              | techniques is that very thin active device layers are accurately transferred, allowing for
              | thin and shallow vertical interconnects to be more densely packed (105-106 mm-2).
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              | 
              | 
              | 
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text          |   Figure 1.9: IBM 3DIC process: a) transparent handling wafer with an active layer of
              |    devices; b) shallow 3D vias are made post-bonding allowing for high density [33].
blank         | 
              | 
text          |        However, to unleash the true potential of 3DICs, an even higher inter-layer via
              | density is required, exceeding the already impressive achievements of wafer level
              | stacking technologies described above. Therefore, for the rest of this work, we turn to
              | our ultimate goal of achieving monolithic 3-D integration, which promises transistor
              | level vertical interconnects that amount to densities of 106 – 107 mm-2.
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              | 
title         | 1.3 Monolithic 3-D integration
blank         | 
text          |        Instead of fabricating multiple layers in parallel on separate wafers, monolithic
              | 3D integration technique sequentially processes them from the bottom-up, all on one
              | wafer (Fig. 1.10). This method eliminates the limitations associated with aligned wafer
              | bonding, since feature placement is determined by consecutive photolithography steps
              | on the same wafer for all of the layers. Hence, routine sub-100 nm alignment can be
              | repeated as the layers are built sequentially, pushing interconnect density above a
              | million wires per square millimeter (>106 mm-2).
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              | 
              | 
              | 
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text          |  Figure 1.10: Monolithic 3DIC process flow (not to scale): first layer is fabricated and
              | the amorphous surface planarized. High quality semiconductor material is either bonded
              | or deposited and crystallized on top. Finally, devices are fabricated in the second layer,
              |                          and inter-layer connections made [15].
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              | 
text          |        Fabrication of upper layer devices in-situ, requires a couple of fundamental
              | breakthroughs. Firstly, we need a method to obtain device-quality single-crystalline
              | semiconductor material on top of an amorphous substrate. Secondly, once the crystal
              | region is formed, low thermal budget processing of upper devices is crucial to preserve
              | the circuit integrity of underlying layers. Otherwise, dopant redistribution, hillocking or
              | voids in the interconnect lines, as well as degradation of low-k dielectrics could
              | adversely affect existing circuit performance. Generally, a temperature limit of around
              | 400 – 450 °C should be sufficient to preserve aluminum or copper interconnects [35]
              | and low-k dielectrics [36], while maintaining dopant profiles. Much effort has been put
              | into satisfying the second requirement of low-temperature processing. Rajendran et al.
              | have developed an excimer laser annealing process that activates dopants in silicon
              | devices, resulting in bulk-like performance [37]. The nanosecond pulse melts the
              | uppermost layer of silicon so quickly that the heat does not diffuse appreciably into
              | lower layers. Tada et al. demonstrated fully low temperature (350°C) process for Si
              | PMOSFET with poly-Ge gate and Schottky source/drain junctions, achieving Ion/Ioff
              | ratio over 107, low gate leakage and sub-threshold slope of only 78 mV/decade [38]. In
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              | 
              | 
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text          | the case of high performance Ge CMOS technology, J-H. Park et al. utilized metal-
              | induced dopant activation (using cobalt) as well as ALD-deposited high-k gate
              | dielectric (Al2O3) to build n- and p-MOSFETs at process temperatures below 380°C
              | [39,40]. Therefore, the primary focus of this work is the first requirement of obtaining a
              | single-crystalline device layer for upper layer monolithic 3DICs.
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              | 
title         | 1.4 Prior art
blank         | 
text          |        In the 1980s some of the earliest monolithic 3DICs were implemented using
              | solid phase crystallization (SPC) of deposited amorphous films to build additional
              | devices on top of a layer of pre-fabricated MOSFETs [41,42], a method similar to that
              | used in thin film transistors (TFT) [43]. For instance, a three level monolithic 3DIC
              | achieved at Mitsubishi in 1986 fabricated devices in re-crystallized α-Si at 950°C (Fig.
              | 1.11) [44], while inter-level wiring was completed with doped poly-silicon
              | (interconnect density ~45mm-2). However, these circuits suffered from poor material
              | quality and crystalline defects such as grain boundaries within active devices, ultimately
              | degrading mobility and leakage performance [45]. Moreover, undue thermal cycling
              | negatively impacted the performance of underlying layers (manifested as threshold
              | voltage shifts) [44]. More recently, in an effort to reduce process temperature, catalysts
              | such as Ni, Pd, Co, Al and others [46-49], have been used to induce solid-phase
              | crystallization at temperatures between 300-500°C. While sizeable (~10µm) single
              | crystal grains have been demonstrated, device performance is typically poor [50] due to
              | leftover catalyst in the active device region.
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              | 
              | 
              | 
text          |         Figure 1.11: Three level monolithic 3DIC with upper layers obtained via
              |                    solid-phase crystallization (Mitsubishi, 1986) [44].
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              | 
              | 
              | 
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text          |        Another bottom-up scheme adopts epitaxial silicon lateral overgrowth to
              | produce upper layers. Typically a seed window is opened to the underlying device
              | layer, from which epitaxial silicon is selectively grown [51]. Although the material
              | quality is good, the growth temperature is high (900-1000°C) for sufficient overgrowth,
              | which degrades the underlying devices and virtually precludes buried metal
              | interconnects. Recently, the technique has been improved with the use of pulsed or
              | scanned laser annealing combined with lower melting temperature germanium (937°C)
              | as the device material. Thus, rapid melt and subsequent seeded epitaxial growth has
              | been shown to crystallize perfectly oriented and large (~100µm) stripes amenable to
              | 3DIC applications [52-54]. In addition, the method could produce a variety of high
              | quality semiconductor grains (Si, Ge, GaAs) [55,56] on amorphous layers if provided
              | with an easily accessible substrate from which to nucleate. However, opening seed
              | windows through microns thick inter-layer dielectric of multi-layered 3DIC and
              | subsequently bringing the crystal seed up presents a formidable challenge, in addition to
              | the space penalty it incurs.
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              | 
text          |        Seedless crystallization techniques offer an attractive alternative, since large
              | single-crystalline grains could be formed directly on the top amorphous layer.
              | Pioneering work in the 1970’s and 1980’s involved scanned strip heater ovens and
              | continuous-wave (cw) lasers to melt and recrystallize large areas of amorphous material
              | on quartz substrates for flat panel displays [57-60]. Biegelsen et al. observed the
              | phenomenon of partial melt in radiatively melted silicon, arising from the reflectivity
              | difference between solid and liquid phases. Due to slight advantage in surface energy at
              | the quartz interface, preferentially textured <100> solid lamellae would form within the
              | melt and subsequently seed large <100> out-of-plane oriented grains upon
              | crystallization [61]. While the use of CO2 and Argon cw lasers for partial melt is hardly
              | low-temperature, Witte et al. adapted the process for 3DIC applications by using short
              | pulses of 532 nm Nd:YAG laser [62]. For example, a pulse of 2 ms used to melt 185 nm
              | thick α-Si film on quartz yielded <100> oriented grains several micrometers long [63].
              | However, the orientation effect seems to disappear for pulse lengths shorter than 200
              | µs, limiting the technique’s applicability to monolithic 3DICs. Other seedless
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              | 
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text          | crystallization approaches rely on patterning the silicon film to ensure single seeding of
              | grains either by a narrow necking region [64,65], or by orientation filtering via growth
              | velocity competition [66,67].
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              | 
text          |        Graphoepitaxy is another technique that has been demonstrated as a means for
              | fashioning regions of single crystal semiconductors on amorphous substrates [68-72]. In
              | this approach, periodic surface relief structures induce crystallographic orientation in
              | thin films upon solidification. While the mechanism is still uncertain, it most likely
              | relies on surface energy advantages in preferentially oriented grains (see Chapter 2).
              | Earliest results by H.I. Smith et al. showed that strip heater melted 500 nm thick α-Si
              | film deposited over a square grating (3.8µm pitch) etched in quartz substrate
              | crystallized into large and uniformly oriented <100> Si crystal with <001> in-plane-
              | orientation parallel to the grating [69]. However, all of the efforts reported employ high
              | power melting techniques (ovens, cw Ar lasers) while maintaining substantial substrate
              | heating (>800°C) [70], even in the case of Ge graphoepitaxy [73]. Such conditions
              | allow for longer cooling times and increased control over random nucleation and crystal
              | growth, yet they are 3DIC incompatible [74,75]. Chapters 2 and 3 are dedicated to
              | exploring ways to achieve successful graphoepitaxy at reduced process temperature
              | suitable for monolithic 3-D integration.
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              | 
text          |        A completely different approach is to directly attach known high quality crystal
              | islands for upper layer device fabrication. The advantage of this technique is that the
              | single crystalline material can be formed or grown separately by conventional means,
              | ensuring a good quality, defect-free device layer. Subsequently, the material is
              | transferred onto the 3DIC wafer using a suitable low-temperature bonding method, and
              | the upper layer device is fabricated via low thermal budget techniques described in the
              | previous section. Unlike wafer stacking, no strict wafer-to-wafer alignment is required
              | during the bonding step, and more importantly, vertical interconnect density is not
              | sacrificed since the approach is monolithic. The main challenge, however, is achieving
              | sufficient bond strength and quality at temperatures compatible with the underlying
              | devices.
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              | 
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text          |        The SOI community pioneered the ‘bond and etch-back SOI’ (BESOI) process
              | to attain full wafer crystalline Si device layer transfer using direct fusion bonding,
              | grinding and etch-back [76,77]. Early demonstrations were plagued by high defect
              | densities at the bonded interface (manifested as trapped particles, bubbles, voids, and
              | delaminated regions), while high temperature post-bonding anneal (typically 800-1100
              | °C) was required to achieve sufficient bond strength (>1 J/m2) [78]. Activation of ultra-
              | smooth (<5Å RMS) mating surfaces by plasma [79] or chemical [80] means prior to
              | bonding have strengthened the attachment considerably while also lowering required
              | anneal temperature [81]. In addition, the removal of the bulk donor wafer has become
              | much simpler with the hydrogen ion induced layer-splitting process (SmartCut®) [82],
              | eliminating the grinding and etching steps. With these advances, very thin crystal layers
              | were transferred to make strained Si-, SiGe- and Ge-on-insulator (GeOI) substrates up
              | to 200mm in diameter [83,84]. Soon thereafter, initial attempts were made at building
              | monolithic 3DICs by transferring thin Si [85] or Ge [86] crystal layers onto
              | prefabricated wafers, but they suffered from weak bonds and defects inherent in large
              | area layer transfers. Therefore, to address the need for strong, void-free and low-
              | temperature (≤400 °C) methods of crystal island attachment for monolithic 3DICs, the
              | remainder of this work explores a variety of bonding techniques: thermo-compressive
              | (Cu-Cu, Ti-Ti), hydrophilic fusion (SiO2-SiO2, Si-SiO2, Ge-SiO2), as well as AlGe
              | eutectic bonding.
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              | 
title         | 1.5 Contributions
blank         | 
text          |    •   Experimental exploration of transient laser annealing of Si and Ge
              |        semiconductor materials for achieving graphoepitaxy under 3DIC compatible
              |        conditions (substrate temperature < 400°C).
blank         | 
              | 
text          |    •   Demonstration of laser-induced graphoepitaxy of Si on amorphous substrate
              |        using a 2-dimensional inverted-pyramid array template (350 nm half-pitch).
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              | 
              | 
              | 
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text          | •   Implementation of a Monte Carlo simulation modeling spontaneous nucleation
              |     processes in undercooled Ge liquids. Model identified the substantial vertical
              |     thermal gradient as the limiting factor in grain growth of pulsed-laser melted Si
              |     and Ge.
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              | 
text          | •   Demonstration of rapid melt growth (RMG) of α-Ge from isothermal Si (100)
              |     seed (i.e. no thermal biasing of the seed region). The single Nd:YAG laser pulse
              |     produced high quality Ge (100) grain on top of SiO2.
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              | 
text          | •   Experimental evaluation of different low-temperature bonding techniques (SiO2-
              |     SiO2, Si-SiO2, Ge-SiO2, Cu-Cu, Ti-Ti, Al-Ge eutectic) for the purposes of
              |     crystal island transfer for monolithic 3DIC integration.
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              | 
text          | •   Development and characterization of thin Al-Ge eutectic bonding technique,
              |     analyzing bond morphology, microstructure, void density, strength, and surface
              |     smoothness requirements. Sub-eutectic Al-Ge bonding at 400 °C has also been
              |     demonstrated.
blank         | 
              | 
text          | •   First recorded measurements of fracture energy (bond strength) of eutectic Al-
              |     Ge bonds using double cantilever beam (DCB) measurement method.
blank         | 
              | 
text          | •   Development and demonstration of a chemical mechanical polishing (CMP)
              |     process for crystalline Ge achieving surface roughness less than 0.15 nm RMS.
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              | 
              | 
              | 
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title         | Chapter 2 – Graphoepitaxy
blank         | 
text          |        An architectural scheme involving multiple layers of active transistors stacked
              | one above the other and connected to each other has been proposed to address the
              | interconnect bottleneck associated with two dimensional Integrated Circuits (ICs) [35].
              | Such three dimensional structures have been fabricated by bonding pre-fabricated
              | circuits together. However, the vertical interconnect density of these systems has been
              | limited to about 106 vertical wires/mm2 due to factors such as alignment limitations of
              | wafer bonding, mismatch in the thermal expansion coefficients of different materials
              | and particle contamination [75]. In a monolithic approach, the upper level circuits are
              | fabricated in situ on thin single crystal films (<200nm thick), alleviating alignment
              | requirements and enabling much larger interconnect density. However, a practical
              | method to obtain single crystal islands of known orientation and grain quality remains
              | elusive. In this chapter we describe extensive work on the use of surface nanostructures
              | and transient laser annealing as a method to achieve oriented single crystal islands of
              | semiconductors over amorphous SiO2 layers.
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              | 
text          |        Ultimately, graphoepitaxy [68-72] via transient laser annealing could open the
              | possibility of fabricating truly monolithic 3DICs with device quality semiconductor
              | crystals on an amorphous substrate without any seed requirement or any adverse effects
              | to underlying device layers during processing.
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              | 
title         | 2.1 Introduction to graphoepitaxy
blank         | 
text          |        Graphoepitaxy is a technique that uses artificial surface relief structures to
              | induce crystallographic orientation in thin films. Since the starting surface material of
              | graphoepitaxy is amorphous and thus atomically disordered, carefully designed periodic
              | structures are fashioned to create a template, which closely mimics the desired
              | crystalline structure. Similarly to the process of heteroepitaxy, where the lattice of an
              | underlying crystalline material imparts the crystal orientation, a deposited material
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              | 
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text          | would acquire a preferred crystal orientation either during deposition or recrystallization
              | due to the underlying artificial relief pattern. Because epitaxy occurs on a substrate that
              | has been pre-written or drawn, the process is named graphoepitaxy [68].
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              | 
              | 
              | 
text          |  Figure 2.1: SEM (plan view) of KCl crystallites on square-wave grating in amorphous
              |     SiO2 showing oriented crystal growth where <100> directions are parallel to the
              |                                       gratings [70].
blank         | 
              | 
text          |        The mechanism for graphoepitaxial orientation relies on surface energy
              | anisotropy between different crystal planes and the amorphous material of the template.
              | Considering a hypothetical columnar grain of area A and thickness h, the Gibbs free
              | energy ΔE can be expressed as [71]:
blank         | 
text          |                         ΔE = AhΔGV + Alsγ ls + 2 Aγ ss
blank         | 
text          | where ΔGv is bulk free energy, γss is the grain-template interfacial surface energy, γls is
              | the grain-liquid surface energy, Als is the interface area between the solid grain and
              | liquid surrounding, and it is assumed the top and bottom surfaces are identical for
              | simplicity. If we compare the contribution of the last term for grains with orientations
              | that minimize surface energy, γmin, with the average surface energy of all grains, γav, we
              | can define a measure of surface energy anisotropy:
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              | 
              | 
              | 
meta          |                                                                                         16
text          |                                     Δγ = γ av − γ min
              | Then, the free energy advantage ΔFS of a grain that minimizes surface energy,
              | normalized per unit volume becomes [71]:
blank         | 
text          |                         ΔFS = −2 A ⋅ Δγ / hA = −2Δγ / h
              | This reduction in surface energy component drives the preferential orientation of
              | graphoepitaxial films. As expected, greater degree of anisotropy Δγ accentuates the
              | effect, but more significantly, energy reduction increases with decreasing film
              | thickness.
blank         | 
              | 
text          |        Finally, it is important to note that minimizing interfacial energy on a smooth
              | amorphous surface would yield a preferential texture, or out-of-plane orientation,
              | leaving the in-plane orientation random. The presence of artificial structures does
              | increase the surface area, but it also creates local energy minima for particular
              | azimuthal, or in-plane orientations [70]. Therefore, surface relief structures provide an
              | additional constraint that limits the degree of freedom to a unique crystal in-plane-
              | orientation that simultaneously minimizes interfacial energy over the complete surface.
              | For example, the cubic crystals of KCl are neatly oriented on top of a square-wave
              | grating in SiO2 substrate (Fig. 2.1). Crystal <100> planes have the minimum surface
              | energy to SiO2 and thus (100) texture develops. Moreover, purposely-built 90°
              | geometry of the grating allows the <010> planes to also cover the sidewalls determining
              | preferential in-plane orientation as well (Fig. 2.2a).
blank         | 
              | 
text          |        Graphoepitaxy most likely takes place during nucleation, where the surface
              | relief pattern provides preferential nucleation sites (Fig. 2.3). The slightly lower energy
              | required for formation of preferentially oriented critical nucleus would cause higher
              | nucleation rates compared to those of randomly-oriented nuclei. As long as random
              | nucleation is suppressed, complete graphoepitaxially oriented films could form by
              | coalescence of such grains (Fig. 2.4).
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              | 
              | 
              | 
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text          | Figure 2.2: a) Square-wave relief structure results in (100) textured film, with <100> in-
              | plane orientation of cubic crystals; b) Saw-tooth pattern is amenable to (111) planes of
              |    the diamond cubic crystal structure of group IV elements such as Si and Ge [69].
blank         | 
              | 
text          |        The process of preferential nucleation can take place in many regimes: from
              | vapour, liquid or solid phase, but it is most pronounced under conditions of low
              | supersaturation such as during vapour deposition, where most nuclei form on the
              | geometric relief patterns [70]. However, in this chapter, graphoepitaxy of Si and Ge
              | from liquid phase is investigated, where transient laser heating induces melting. In
              | addition, graphoepitaxy of solid phase crystallization (SPC) of amorphous thin films is
              | also explored.
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              | 
              | 
              | 
text          | Figure 2.3: Vapour deposited Ge crystallites preferentially nucleate on the corners of a
              | square-grating template etched in amorphous SiO2: a) XTEM; b) plan view SEM. Note:
              |          SiO2 grating was covered with a self-assembled monolayer (SAM) of
              |      octadecyltrichlorosilane (OTS) to facilitate Ge nucleation. Images obtained in
              |                        collaboration with T.I. Kamins et al. [87].
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              | 
              | 
              | 
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text          |    Figure 2.4: Sequence of growth for a cubic crystalline material on a square-wave
              | structure with perfect ‘decoration’ where all the oriented nucleation occurs at the steps,
              |              and random nucleation in between the steps is suppressed [70].
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              | 
title         | 2.2 Liquid phase graphoepitaxy (Prior art)
blank         | 
text          |        Early investigations of silicon graphoepitaxy have shown that surface relief
              | grating structures of 3-5 µm pitch in amorphous substrates can define the
              | crystallographic orientation of deposited silicon films [68]. The melting and
              | recrystallization of these thin films (500 nm thick) has been performed using strip-
              | heater ovens as well as by scanned continuous wave (cw) lasers. In both of these
              | methods, the substrate was temperature biased to a large fraction of the melting
              | temperature, allowing for a slow cooling rate of the molten silicon film. Such conditions
              | produced highly oriented single-crystal grains over 10 µm in size, with both in and out-
              | of-plane orientation determined by the underlying template [69].
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              | 
text          |        However, strip heaters and cw lasers are not suitable modes of heat delivery for
              | sequential 3DIC fabrication because the long anneal times would damage devices in the
              | lower layers, especially if substrate heating is involved. Therefore, our approach is to
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              | 
              | 
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text          |   Figure 2.5: a) Graphoepitaxy of 500nm thick Si films on fused silica grating (3.8μm
              |   pitch, 0.1 μm depth). After heating the substrate to 1000+ °C, the scanning IR lamp
              | melted the Si film, which then recrystallized into preferentially oriented Si (100) grains,
              |                with in-plane orientation also (100) along the grating [68].
blank         | 
              | 
text          | employ short pulses (15 µs) from a frequency doubled Nd:YAG laser as a way to melt
              | α-Si layer without much undue heating. In addition, we tried to improve on prior art by
              | using much finer grating structures (e.g. 95 nm half-pitch) as well as two-dimensional
              | templates (e.g. inverted pyramids) to better influence the orientation of the crystal film.
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              | 
title         | 2.3 Feasibility of transient heating for 3-D integration
blank         | 
text          |        Drawing on a one-dimensional thermal diffusion model [37], we selected spot-
              | size, laser power and pulse duration to ensure melting of the silicon layer while
              | minimizing the heating of the underlying substrate [88]. The transient thermal profile
              | for the laser-annealed wafer was obtained by solving the light absorption and heat
              | diffusion equations for the simplified 1-D structure shown in the inset of Fig. 2.6.
              | Temperature dependent values of thermal conductivity, specific heat and the refractive
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              | 
              | 
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text          | index coefficients of the different materials were used in the calculations. We accounted
              | for phase change by using the latent heat of fusion for the different materials. We also
              | assumed that molten α-Si solidifies into fine-grain polysilicon with a thermal
              | conductivity value twice that of α-Si. Random nucleation is not accounted for in the
              | simulation and radiative losses are assumed to be negligible. Full details of the thermal
              | simulation can be found in [62].
blank         | 
              | 
              | 
              | 
text          | Figure 2.6: One dimensional simulation results: thermal profile evolution due to a 15 µs
              |   laser pulse anneal demonstrating complete melting of 100 nm thick α-Si layer while
              |      maintaining sub-450 °C temperature in underlying layers (5 µm below α-Si).
blank         | 
              | 
text          |        The simulation results show that by using a 15 μs laser pulse with power density
              | of 120 kW/cm2, the deposited amorphous silicon film (100 nm thick) could be melted
              | completely, while keeping the maximum temperature excursion in the underlying SiO2
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              | 
              | 
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text          | layer (5 µm below α-Si) to less than 450 °C (Fig. 2.6). This demonstrates the feasibility
              | of using transient heating technique to melt and recrystallize upper layers of 3D
              | structures, without damaging circuits built in the lower layers.
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              | 
title         | 2.4 Laser annealing apparatus
blank         | 
text          |        The samples were subjected to a range of laser annealing conditions using an
              | acousto-optically modulated frequency doubled Nd:YAG laser (λ = 532 nm). The
              | diameter of the beam spot size was 15 μm (FWHM), while the pulse duration varied
              | from 15 μs to continuous wave. The sample was not scanned during exposure, and there
              | was no other substrate heating except from the incident radiation. The schematic of the
              | laser annealing apparatus is presented in Fig. 2.7, including the brightfield illumination
              | and in-situ imaging system [89].
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              | 
              | 
              | 
text          |  Figure 2.7: Laser annealing apparatus: Nd:YAG power laser at λ = 532 nm is acousto-
              |  optically modulated into pulses and guided onto the sample placed on X-Y stage. The
              |  Gaussian beam is focused through a Mitutoyo objective (NA = 0.90) creating a beam
              |                    spot of various FWHM diameters (10-32 µm) [89].
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              | 
              | 
              | 
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title         | 2.5 Graphoepitaxy using 1-D templates
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              | 
title         | 2.5.1 Design of nano-grating template
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              | 
text          |        The grating pattern was generated in thermally grown SiO2 using nanoimprint
              | lithography (NIL) [90]. The imprint was made in 200 nm thick thermoplastic resist with
              | a 4-inch silicon mold using an NX-2000 machine. The imprint tool was equipped with
              | the Air Cushion Press (ACPTM) ensuring uniformity over the entire 4-inch wafer. The
              | resulting pattern was transferred with double Cr shadow evaporation to achieve
              | different line widths. After lift-off, the gratings were etched into thermally grown SiO2
              | layer (1 μm thick) using CHF3/O2 reactive ion etching. Full details of the NIL procedure
              | have been previously described elsewhere [91]. We chose different line widths from 30
              | to 70 nm, while the pitch was kept at 190 nm. Trench depth was around 25 nm and the
              | grating profile can be seen in the atomic-force micrographs (Fig. 2.8a).
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              | 
              | 
              | 
text          |   Figure 2.8: a) AFM image and section analysis of the grating pattern etched in SiO2
              | using nanoimprint lithography (190 nm pitch, 70 nm linewidth); b) TEM cross-section
              | of the final structure showing nanoimprinted grating in thermal SiO2 (190 nm pitch, 30
              | nm linewidth) covered with LPCVD layer of α-Si (100 nm thick) followed by a capping
              |                              layer of LTO (170 nm thick).
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              | 
text          |        In experiments using silicon, an amorphous layer 100 nm thick was deposited at
              | 585 °C by low-pressure (400 mT) chemical vapour deposition (LPCVD) using silane
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              | 
              | 
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text          | (SiH4) chemistry. Finally, the structure was capped with 170 nm of low temperature
              | oxide (LTO) deposited at 400 °C. The resulting structure can be seen in the cross
              | sectional TEM image (Fig. 2.8b). A second set of samples with 500 nm thick α-Si layer
              | and 1.2 µm thick LTO cap was also fabricated.
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              | 
title         | 2.5.2 Results of pulsed laser (1-D) graphoepitaxy
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              | 
text          |        We used continuous-wave laser exposure at 1 to 2 MW/cm2 power densities in
              | order to ensure melting of the semiconductor layer. The effect of laser recrystallization
              | of a 500 nm thick α-Si film can be seen in (Fig. 2.9a). Three distinct regions are
              | observable following the exposure. First, near the center of the laser beam, large crystal
              | grains spanning the thickness of the film can be detected (Fig. 2.9b). Second, away from
              | the melted region, there is an area of solid-phase crystallized silicon with fine
              | polycrystalline structure (Fig. 2.9c). Finally, outside the annealed region is the original
              | deposited amorphous silicon layer (Fig. 2.9d). In addition, we found that thick capping
              | layers (at least 1 µm of LTO) were necessary to provide structural support during the
              | silicon melting process. Otherwise, the surface tension of liquid silicon on SiO2 caused
              | agglomeration, producing significant damage to the capping layer.
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              | 
              | 
              | 
text          | Figure 2.9: a) TEM cross-section of the melt zone for 500 nm thick Si film with 1.2 µm
              | LTO capping layer. Laser was in continuous-wave mode (non-scanning) with spot size
              | 15 µm FWHM; b) individual crystal grains visible near the center of the laser beam; c)
              | solid phase crystallization region; d) as deposited α-Si layer away from the laser beam.
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              | 
              | 
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text          |        Taking a closer look at the large crystal grains in the 100 nm thick cw laser
              | recrystallized Si film, it appears that individual grains are confined to the regions
              | between NIL patterned gratings with grain boundaries meeting regularly on top of the
              | patterned lines (Fig. 2.10). In addition, the lateral extent of each crystalline grain of the
              | thin Si film seems to be limited by the pitch of the SiO2 grating, in this case 190 nm.
              | Therefore the TEM micrographs suggest that nano-gratings in SiO2 substrates can
              | determine the size and boundary location of grains in recrystallized α-Si films.
              | However, convergent beam electron diffraction (CBED) patterns of each individual
              | grain indicate that there is no obvious preferential orientation of Si grains. Studies by
              | Givargizov et al. [72] suggest that the shape and radius of curvature of artificial patterns
              | is of critical importance in defining crystal orientation. For example, in the case of a
              | NIL patterned square grating, vertical walls with 90° sharp corners are desirable to
              | impart <100> in-plane orientation onto adjoining silicon crystal grains. Therefore, the
              | slightly rounded features of SiO2 grating evident in Fig. 2.9 and 2.10 may be
              | responsible for the apparent lack of preferential orientation.
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              | 
              | 
              | 
text          |      Figure 2.10: TEM cross-section of recrystallized Si film (100nm thick) on NIL
              | patterned grating in SiO2 (190 nm pitch, 30 nm linewidth). Individual grain boundaries
              |               emanating from the periodic NIL gratings are clearly visible.
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              | 
text          |        The TEM images of cw laser recrystallized 500 nm thick film (Fig. 2.9b) also
              | show large crystalline grains that seem to span the entire vertical thickness of the film.
              | However, these grains do not closely match the grating pitch in the lateral dimension
              | nor are they preferentially oriented. Imperfect grating geometry may be the culprit, but
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              | 
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text          | there is another possible cause: a concentration of small crystallites located around the
              | NIL patterned grating in SiO2. These crystallites also seem to cause line and plane
              | defects in large grains that are not evident in 100 nm thick recrystallized films. Cross-
              | sectional TEM image of as-deposited α-Si layer (Fig. 2.11) confirmed that these
              | crystallites form during deposition step of amorphous silicon at 585°C. They were too
              | small to determine the exact orientation by CBED, but the diffraction contrast suggests
              | they are randomly oriented.
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              | 
              | 
              | 
text          |  Figure 2.11: TEM cross-section of α-Si film (500 nm) deposited by LPCVD at 585 °C
              |    for 90 min over the patterned SiO2, showing small Si crystallites around the nano-
              |   grating. Due to their higher melting temperature than α-Si, these bits of crystal may
              |                           effectively ‘mask’ the SiO2 grating.
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              | 
text          |          During laser annealing of 500 nm thick film, this bottom-most part of silicon
              | layer probably did not melt completely (due to higher melt temperature of crystallites
              | compared to α-Si), effectively masking the NIL patterned grating below. Therefore,
              | there was no graphoepitaxial orientation of crystallized silicon grains in 500 nm thick
              | films.
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              | 
text          |          However, it must be noted that H.I. Smith et al. [92] identify these small
              | crystallites critical to the graphoepitaxial process. Their argument asserts that the last
              | surviving grains during laser irradiation are the ‘graphoepitaxially oriented’ ones, with
              | higher melt temperatures due to their energetically favourable orientation (see surface
              | energy argument above). Therefore, these surviving grains are ultimately responsible
              | for seeding full crystallization of the liquid silicon, producing graphoepitaxial films
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              | 
              | 
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text          | with preferential texture as well as in-plane orientation. The proposed mechanism could
              | explain the lack of preferential orientation in fully melted 100 nm thick Si films, since
              | no crystallites survive the full melting process, leading to randomly oriented nucleation
              | [93]. Conversely, in 500nm thick films, the laser power was insufficient to melt the
              | ‘weak’ crystallites away and select for the graphoepitaxial grains resulting in randomly
              | oriented grains as seen in Fig. 2.9.
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              | 
text          |        Further investigation into LPCVD deposited α-Si films showed that 30-50 nm
              | sized grains are present at the Si-SiO2 interface for films deposited at 585 °C, while
              | their occurrence is significantly suppressed with a lower deposition temperature of 525
              | °C (Fig. 2.12). Thus, the observed crystallites in Fig. 2.11 are indeed an artifact of the
              | deposition process at 585 °C and independent of 1D nano-grating in the SiO2.
              | Consequently, in order to avoid masking of the template by these randomly oriented
              | crystallites, lower temperature deposition of LPCVD α-Si films at 525 °C was pursued.
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              | 
              | 
              | 
text          |     Figure 2.12: HRTEM cross-section of the LPCVD deposited amorphous Si-SiO2
              | heterogeneous interface. Si film deposited at 585 °C shows small crystallites present at
              |         the interface, while at 525 °C their formation is significantly suppressed.
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              | 
title         | 2.5.3 Conclusions of initial 1-D template experiments
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              | 
text          |        Our initial experiments using transient heating techniques employed a square
              | nano-grating of 95 nm half-pitch, patterned by nanoimprint lithography (NIL) with the
              | intent of imparting better orientation control – thus the name nano-graphoepitaxy [91].
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              | 
              | 
              | 
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text          | In the investigations involving laser annealed 100 nm thick films, the regular grating
              | pattern seemed to determine the location of the crystal grain boundaries, thus
              | controlling the position and size of silicon crystals. However, no preferential crystal
              | texture or in-plane orientation was found. Similarly, in 500 nm thick films, large and
              | randomly oriented grains formed, with no apparent influence of the nano-grating.
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              | 
text          |        Two possible reasons for the lack of crystal orientation by graphoepitaxy have
              | been identified: template imperfection and incomplete melt of irradiated films. One-
              | dimensional nano-grating fabricated by NIL allows for smaller pitch templates, but
              | shallow trench depths and limitations of RIE process cause rounded corners and non-
              | vertical sidewalls, which ultimately compromise the geometry of the template that is
              | supposed to impart graphoepitaxial orientation. Moreover, high temperatures required
              | to melt Si also lead to plastic flow deformation of the SiO2 grating further degrading the
              | template, as seen in the solid-phase graphoepitaxy experiments.
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              | 
text          |        The second possible cause of randomly oriented grains in recrystallized Si films
              | is incomplete melt of the full thickness of the film. In particular, small, randomly
              | oriented crystallites formed at the SiO2 interface either during α-Si deposition process
              | (at 585 °C) or by solid phase epitaxy may effectively mask the nano-grating template.
              | During the laser pulse anneal, if these bottom-most crystallites are not melted, they then
              | nucleate the growth of randomly oriented grains, defeating graphoepitaxy.
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              | 
text          |        Overall, given that no preferential crystal texture or in-plane orientation was
              | found, the ability to form grapho-epitaxially oriented crystals with purely transient
              | annealing techniques was put into question. Consequently, a second set of experiments
              | using sharper two-dimensional patterns and thinner Si films was pursued to achieve
              | graphoepitaxy with pulsed laser heating.
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              | 
              | 
              | 
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title         | 2.6 Graphoepitaxy using 2-D templates
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text          |        To address the issues of template fidelity, we pursue a new approach that
              | employs sharper, two-dimensional templates defined by orientation dependent etching
              | of silicon. The intent of 2D template is to further constrain the degrees of freedom of
              | growing grains, and together with geometrically sharp features maximize the effect of
              | amorphous SiO2 relief pattern in determining the orientation of recrystallized films.
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              | 
text          |        LPCVD of α-Si is performed at lower temperature (525 °C), eliminating any
              | crystallites that may form at the SiO2 interface during deposition. Moreover, thinner
              | films (<100 nm) of silicon are deposited in order to maximize the surface energy
              | component of the free energy calculation, thus augmenting the probability of forming
              | template-oriented grains. Finally, these thin silicon films are still melted using pulsed
              | laser annealing. Whereas the new structure is no longer 3DIC compatible, the real intent
              | is to investigate if graphoepitaxy of thin silicon films is achievable using pulsed laser
              | annealing on shorter time scales.
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              | 
title         | 2.6.1 Design of inverted pyramid template
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              | 
text          |        To achieve sharper template geometry (radius of curvature at corners, rc, less
              | than 5 nm), orientation dependent etching of silicon was used to produce an array of
              | inverted pyramids with lattice defined sharp corners (Fig. 2.13b). Starting with a (100)
              | silicon wafer, 35 nm thick Si3N4 layer was deposited by LPCVD before spinning on 2%
              | 950K PMMA resist. An array of 500 nm squares was patterned on a 700 nm square grid
              | using a Raith 150 electron beam exposure tool. The pattern was transferred to the Si3N4
              | layer using reactive ion etching, and the exposed silicon was anisotropically etched in
              | 30% KOH solution at 80 °C for 2 minutes, resulting in a periodic array of inverted
              | pyramids (Fig. 2.13c). After removing the remaining silicon nitride hard mask in hot
              | phosphoric acid, the crystalline nature of silicon was effectively masked by growing a
              | 12 nm thin SiO2 layer via dry oxidation at 850 °C. The SiO2 layer was sufficiently thin
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              | 
              | 
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text          | not to obscure the geometry of the exposed (111) silicon planes, but thick enough to
              | prevent any homoepitaxy from the crystalline silicon substrate. Thus, an amorphous 2D
              | topographic template was formed. Subsequently, a 50 nm thick amorphous silicon layer
              | was deposited at 525 °C by LPCVD at 400 mT, followed by a thick 1.2 µm cap of low
              | temperature oxide (LTO) grown at 400 °C. The final fabricated structure can be seen in
              | the cross-sectional TEM image (Fig. 2.13a). Note the absence of any crystallites in α-Si
              | film deposited at 525 °C (slightly darker regions are due to sample preparation process).
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              | 
              | 
              | 
text          |   Figure 2.13: a) Cross-sectional TEM image of the fabricated sample illustrating the
              | sharp, lattice defined corners of template (rc < 5nm); b) corresponding schematic cross-
              |  section of the 500 nm inverted pyramid template sample c) Top view SEM of the 2D
              |             inverted pyramid array with the LTO cap removed for imaging.
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              | 
              | 
              | 
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text          |        The samples were subjected to a range of pulse lengths (1 µs to 1 ms) produced
              | by an acousto-optically modulated, frequency doubled Nd:YAG laser (λ = 532 nm) set
              | at 7.5W. The originally Gaussian beam intensity profile was reshaped using a refractive
              | beam shaper into a top-hat profile with 22 µm diameter. The sample was not scanned
              | during exposure and there was no substrate heating other than from the incident
              | radiation.
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              | 
title         | 2.6.2 Results of 2-D template experiments
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text          |        In order to ensure melting of the amorphous silicon layer, the final fabricated
              | structure was annealed using a single pulse of 100 µs duration with laser power density
              | at the sample of 1.3 MW/cm2. The cross-section of the annealed structure, prepared by
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              | 
              | 
              | 
text          |  Figure 2.14: a) Cross-sectional SEM image of the delaminated LTO cap after 100 µs
              |  pulse laser anneal; b) The cause of cap delamination can be seen in the top view SEM
              |     of the annealed area. Agglomerated silicon islands cluster around the middle of
              |              irradiated area due to de-wetting of molten Si film on SiO2 surface.
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              | 
              | 
              | 
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text          | focused ion beam, reveals that the LTO cap has delaminated from the substrate (Fig.
              | 2.14a) by agglomeration of the molten 50 nm thin film.
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              | 
text          |        After etching away the SiO2 cap, the top view SEM (Fig. 2.14b) clearly
              | demonstrates significant mass flow and accumulation of silicon material into 500 nm to
              | 2 µm sized islands that caused the LTO cap to lift. Liquid silicon de-wets SiO2 surfaces
              | with a contact angle of 87° [94], and the reduction in Gibbs free energy per unit volume
              | is inversely proportional to the film thickness, making thinner films more likely to
              | agglomerate. The failure of the LTO cap to prevent de-wetting could be explained by
              | material softening at such high temperatures (~1400°C) making LTO more akin to a
              | very viscous liquid than a stiff cap [95]. Reducing laser power or shortening the pulse
              | length did not melt the amorphous silicon film, but rather caused solid phase
              | crystallization (SPC).
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              | 
              | 
              | 
text          |    Figure 2.15: TEM cross-section of the 50 nm thick silicon film just outside of the
              |      melted region shows fine grain polycrystalline structure formed by solid phase
              |                                       crystallization.
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              | 
text          |        The resulting fine grain polycrystalline structure of SPC film can also be
              | identified in the non-agglomerated region at the edges of the laser annealed area (Fig.
              | 2.15). Thus, it appeared that the liquid silicon de-wetted the surface shortly after
              | melting, leaving a continuous solid phase crystallized film at the periphery of the melt
              | and large crystal islands in the middle.
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              | 
              | 
              | 
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text          |        Taking a closer look at the crystalline structure of one of these agglomerated
              | islands, it appears that large single crystal grains, 300-500 nm in size have formed (Fig.
              | 2.16). More importantly, a detailed analysis of convergent beam electron diffraction
              | (CBED) patterns indicates a high degree of both in-plane and out-of-plane grain
              | orientation, following the underlying template. In particular, the azimuthal (in-plane)
              | orientation of all three grains visible in Figure 2.16 is <110>, matching the template
              | orientation within the goniometer measurement error of ±0.5°.
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              | 
              | 
              | 
text          | Figure 2.16: TEM cross-section of the agglomerated silicon island after a 100 μs pulse
              |  laser anneal. Red arrows indicate out-of-plane orientation. In addition, all grains have
              |      in-plane orientation matching the 2D template, demonstrating a high degree of
              |                               graphoepitaxial orientation.
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              | 
text          |        A typical diamond shaped CBED pattern along <110> zone axis of the cross-
              | sectioned sample is shown in the inset of Fig. 2.17. The out-of-plane orientation is
              | mostly <100>, with a few grains at 54° tilt, which corresponds to the angle between
              | principal (100) and (111) planes. A high-resolution transmission electron micrograph
              | (Fig. 2.17) reveals excellent crystal lattice quality, where virtually defect free silicon
              | grains are terminated at twin grain boundaries emanating from the corners of the
              | template.
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              | 
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text          | Figure 2.17: HRTEM cross-section of a defect free recrystallized grain terminating at a
              | (111) twin grain boundary. Inset: microdiffraction (CBED) pattern affirms the excellent
              |                    crystal quality of the recrystallized silicon grain.
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              | 
text          |        The observed graphoepitaxial effect on crystal orientation is most likely due to
              | the two-dimensional nature of the inverted pyramid array as well as the high fidelity of
              | the amorphous template. Due to orientation dependent etching in KOH, the SiO2
              | template closely mimics the geometry of a diamond crystal lattice, characteristic of
              | group IV semiconductors. Unlike the one-dimensional square grating, the inverted
              | pyramid array constrains two in-plane degrees of freedom and consequently improves
              | orientation control by establishing a local energy minimum for a particular in-plane
              | grain orientation that matches the template. In earlier work, A. Giermann and C.V.
              | Thompson also noted successful graphoepitaxy by inverted pyramid templates, in their
              | case to achieve a periodic array of crystallographically oriented gold metal particles
              | [96]. Koide et al., also noted controlled orientation of strip-heater annealed thin
              | germanium films owing to a two-dimensional template [73]. In this work, the same
              | mechanism has been shown to function in transiently annealed thin silicon films.
              | Finally, although quite unlikely, the possibility of oriented grains seeding from the
              | underlying (100) Si substrate through cracks in 12 nm thick SiO2 cannot be fully ruled
              | out.
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              | 
              | 
              | 
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text          | Figure 2.18: TEM cross-section of the annealed structure. Atomically flat silicon (111)
              |   plane ‘walls’ of the pyramids have become wavy following the 100 µs pulsed laser
              |                      anneal indicating substrate melting took place.
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              | 
text          |        Due to the extremely thin SiO2 insulating layer and the high thermal
              | conductivity of the underlying crystalline silicon substrate, high laser power and long
              | pulse duration are required to melt the 50 nm amorphous silicon layer. With such
              | significant heat flows, melting the top silicon film inevitably causes the uppermost
              | region of the crystalline substrate to melt as well. TEM cross-sectional inspection of the
              | substrate geometry after laser annealing reveals some waviness to the normally flat
              | (111) silicon surfaces, suggesting mass redistribution in liquid phase (Fig. 2.18).
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              | 
text          |        One-dimensional thermal simulation [62] of the simplified layer structure
              | indicates that even for a shorter pulse of 10 µs duration, the laser power required to melt
              | 50 nm of amorphous silicon on top of 12 nm SiO2 also melts the underlying crystalline
              | silicon to a depth of 400 nm. While this is certainly not 3DIC compatible, it generates
              | significant substrate heating, which allows for large oriented crystals to form.
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              | 
              | 
              | 
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text          |          Earlier work by H.I. Smith et al. [92] demonstrated graphoepitaxial orientation
              | of partially melted Si films in which the last surviving grains that were not melted by a
              | strip-heater or scanned cw laser would serve as nucleation sites that would grow and
              | coalesce into oriented films. This technique of ‘survival of the fittest’ relies on the
              | elevated melting temperature of grains that have energetically favourable orientation
              | relative to the amorphous substrate. In contrast, in this experiment complete melt and
              | agglomeration occur, eliminating seeded grain growth from either SPC region or
              | unmelted grains. Such seedless condition would normally cause uncontrolled and
              | spontaneous crystallization to occur in an undercooled melt. However, due to the fact
              | that the melted top layer of the silicon substrate releases its latent heat as it solidifies, it
              | maintains the (much smaller) molten Si film close to the melting point. This in turn
              | limits the undercooling of the liquid melt and allows for near-equilibrium growth of
              | grains where energetic considerations become pronounced and graphoepitaxy takes
              | place.
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              | 
              | 
              | 
text          | Figure 2.19: a) TEM cross-section of the agglomerated silicon film after a 100 µs pulse
              |     laser anneal; b) the crystallized grain has in-plane orientation matching that of Si
              |  substrate, while the out-of-plane orientation is twinned along <111> plane, making it
              |    70.6° off from <100> Si substrate. The thin grain emanating from the corner of the
              |          template is graphoepitaxially oriented (matches the Si substrate exactly).
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              | 
              | 
              | 
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text          |        Another sample containing a 2D template where thin Si film has been melted
              | using pulsed laser anneal is presented in Fig. 2.19. All of the crystallized grains shown
              | have in-plane (azimuthal) orientation matching the Si substrate (±1°), suggesting strong
              | influence of the amorphous 2D template. However, the out-of-plane orientation is
              | graphoepitaxally aligned <100> only for the narrow sliver emanating from the left
              | corner, while the rest of the agglomerate is a <111> twin grain at 70.6° out-of-plane tilt
              | with respect to the substrate. Formation of twin boundaries such as these in silicon is
              | very common due to their low energy cost: γtwin ~ 34 mJ/m2, compared to a regular
              | grain boundary γgb ~ 273 mJ/m2 [97]. While we can only speculate on the nucleation
              | location and the direction of grain growth, the data does support the notion that crystal
              | grains with graphoepitaxial orientations with respect to 2D patterned amorphous SiO2
              | substrates are more likely to form than others.
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              | 
              | 
              | 
text          |  Figure 2.20: One-dimensional simulation results: thermal profile evolution due to a 10
              |   µs laser pulse anneal. Top curve illustrates slow cooling rates of 50 nm thick silicon
              |   film with 1000 °C substrate biasing, limiting the undercooling the film experiences
              |                 compared to the case of non-temperature biased sample.
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              | 
              | 
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text          |         Considering a 3DIC compatible structure with 8 μm thick insulating SiO2 layer,
              | the top silicon layer can be melted using a 10 μs pulse without raising the substrate
              | temperature above 450 °C (Fig. 2.20). In this case, the thin film crystallizes over about a
              | microsecond, denoted by a constant temperature region of solidification following the
              | laser pulse. Modeling of the same structure, but with the substrate temperature biased to
              | 1000 °C where lower laser power is required to melt the silicon film, reveals that
              | crystallization occurs over a much longer timescale of tens of microseconds. Thus, for
              | the experiment of graphoepitaxy on an inverted pyramid template, the inadvertent
              | melting of the underlying substrate significantly reduces vertical heat flow rates,
              | limiting undercooling and producing temperature profiles much like the case of 1000 °C
              | substrate temperature biasing. Such conditions suppress spontaneous random
              | nucleation, and allow for graphoepitaxially-oriented grains to grow (see Chapter 3).
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              | 
title         | 2.6.3 Conclusions of 2-D template graphoepitaxy
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              | 
text          |         Orientation dependent etching of Si (100) crystal made for lattice defined
              | inverted pyramid template, superior to that of RIE defined 1D nano-grating. The grown
              | thermal SiO2 layer minimally degraded the 2D geometry resulting in sharp features with
              | radius of curvature rc < 5 nm, compared to the rc ~23 nm in the square grating case.
              | Such accurate templates allowed for formation of graphoepitaxially oriented silicon
              | crystal grains.
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              | 
text          |         However, the more significant cause for successful graphoepitaxy was the
              | inadvertent melting of the substrate, and the resulting slow-cooling transient. With
              | limited undercooling, spontaneous random nucleation was suppressed, such that the
              | energetically favourable oriented grains had a chance to grow into the silicon melt.
              | Therefore, both sharp two dimensional template pattern and inadvertent substrate
              | melting facilitated the formation of large silicon crystals with controlled orientation
              | upon a 100 µs pulsed laser anneal.
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              | 
              | 
              | 
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title         | 2.7 Solid phase graphoepitaxy
blank         | 
text          |        Another potential avenue for achieving oriented semiconductor crystals on
              | amorphous substrates is by solid phase graphoepitaxy. T. Yonehara et al. [98,99]
              | demonstrated graphoepitaxy of thin Ge films on SiO2 by solid-state surface energy
              | driven grain growth. The mechanism is as follows: primary crystallization process
              | transforms an amorphous thin film into a mosaic of randomly oriented columnar grains,
              | with diameters similar to film thickness. Upon further annealing, secondary grains that
              | are graphoepitaxially oriented (i.e. the sum of the top and bottom surface energies is
              | minimum) grow by consuming neighbouring grains. Since minimum surface energy
              | generally corresponds to a specific crystallographic orientation, the resulting grains
              | should have a uniform texture, and due to the grating, also a uniform azimuthal
              | orientation. Consequently, these secondary grains grow, impinge and coalesce forming
              | large areas of oriented crystal material, as described by C.V. Thompson [71,100,101].
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              | 
text          |        Yonehara’s template was a 200 nm pitch square grating with 10 nm deep steps
              | in SiO2, while the thin (20 nm) films of Ge annealed at 900 °C for 16 hours produced
              | large (5 µm) secondary grains with <100> texture and <100> orientation parallel to the
              | grating axis. The solid-phase graphoepitaxy took place at a temperature quite close to
              | melting point of germanium (TM = 937 °C). However, the process temperature could be
              | lowered to 3DIC compatible levels, albeit at the expense of slower grain growth.
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              | 
title         | 2.7.1 Silicon solid-phase graphoepitaxy (1-D)
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              | 
text          |        To investigate solid phase graphoepitaxy of thin silicon films, the same 1D
              | nano-grating template described earlier was used. Amorphous silicon film (60 nm) was
              | deposited at 525 °C by LPCVD on top of the NIL grating etched into fused silica (SiO2)
              | substrate. Such thin films are required because the secondary grain growth rate
              | increases with decreasing film thickness, as expected in surface energy driven
              | mechanism [101]. In addition, a thick SiO2 cap (1.4 µm) was deposited to prevent
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              | 
              | 
meta          |                                                                                         39
text          | agglomeration, which in thin films (<100 nm) occurs far below melting temperature.
              | The nano-grating (NIL) samples were annealed in a conventional furnace at 600 °C and
              | 1100 °C, along with non-patterned control samples.
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              | 
text          |        While not strictly 3DIC compatible, the long anneals at 600 and 1100 °C were
              | designed to investigate whether solid-phase graphoepitaxy of silicon is at all possible,
              | and if so, can it be done at a low-temperature (such as 600 °C).
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              | 
text          |        The resulting crystallinity of annealed Si films was characterized by glancing
              | angle X-ray diffraction (XRD). After etching away the LTO cap, the samples were
              | exposed to λ = 0.975 Ǻ X-ray beam (150x150 µm in size) with 0.1° angle of incidence.
              | The significant diffuse signal from the bulk SiO2 substrate was subtracted, and the
              | diffraction peak intensity plotted in Fig. 2.21.
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              | 
              | 
              | 
text          | Figure 2.21: Glancing angle XRD spectra of thermally annealed 60 nm thick Si films on
              | NIL patterned and flat (control) SiO2 substrates: a) after 24 hours at 600 °C, b) after 24
              | hours at 1100 °C. Note, the errors in spectra at lower reciprocal space coordinates is due
              |               to imperfect subtraction of the SiO2 background X-ray peak.
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              | 
text          |        The diffraction data indicates that solid phase crystallization took place, with
              | <111>, <220>, <311> and <400> planes forming diffraction peaks typical of FCC
              | crystal lattice. However, there seems to be little effect of the nano-grating template
              | (NIL) on crystallographic orientation of Si films annealed at 600 °C. At 1100°C, the
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              | 
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text          | control sample data is inconclusive, but the nano-grating sample did not show
              | preferential orientation. Instead, the diffraction peak intensities are very close to that of
              | Si powder diffraction standard [102], suggesting random polycrystalline texture.
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              | 
text          |         Further characterization of NIL samples by cross-sectional TEM offers clues as
              | to why solid phase graphoepitaxy did not take place. The initial amorphous Si film (Fig.
              | 2.22a) starts crystallizing upon a 24 hour anneal at 600 °C. The relatively low
              | temperature of 600 °C reduces the rate of nucleation, allowing for the grains that do
              | nucleate to grow large (~200 nm) before impinging on another grain (Fig. 2.22b).
              | However, the grain grows slowly and is full of internal defects such as stacking faults,
              | twins and dislocations. In addition, microdiffraction (CBED) patterns showed no
              | preferential crystallographic orientation, suggesting that graphoepitaxial preference
              | does not take place during grain nucleation stage. Samples annealed at 1100 °C for 1-
              | hour (Fig. 2.22c) show smaller grains (~50 nm), but with fewer defects. Their
              | orientation is also random, while the SiO2 grating itself has become rounded. After 24
              | hours at 1100 °C (Fig. 2.22d), the NIL grating has completely lost its shape, resulting in
              | a smooth bump. In addition, secondary grain growth has increased the grain size to
              | more than 200 nm, while lattice defects are almost eliminated. However, the larger
              | grains still have no preferential orientation, confirming the XRD results.
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              | 
text          |         Therefore, the effect of artificial surface patterns altering crystallographic
              | texture reported in literature has not been observed in these thin Si films. A few things
              | could cause the lack of graphoepitaxial orientation. Firstly, the 1D nano-grating
              | degraded significantly at high temperatures due to softening of fused silica substrate.
              | The lack of geometrically defined template directly undermines the preferential growth
              | of oriented grains via surface energy anisotropy. Secondly, the anneal temperature of
              | 1100 °C is more than 300 °C below the melting point of silicon (TM=1412 °C). Given
              | that Yonehara et al. annealed Ge films only 37 °C below melting, the 1100 °C used for
              | Si may be insufficient to achieve significant secondary grain growth and thus
              | orientation effects in Si thin films.
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              | 
              | 
              | 
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text          | Figure 2.22: a) TEM cross-section of 60 nm α-Si film on NIL patterned nano-grating in
              | fused silica (SiO2) substrate. Solid phase crystallization takes place after: b) 24 hours at
              |                  600 °C; c) 1 hour at 1100 °C; d) 24 hours at 1100 °C.
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              | 
              | 
              | 
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text          |        In conclusion, solid phase graphoepitaxy of silicon seems difficult to achieve,
              | especially at low-temperatures. 3DIC incompatible thermal budget (1100°C+) is
              | required to achieve appreciable secondary grain growth, while such thermal excursions
              | also damage the template intended to orient the crystallizing films. Even with lower
              | melting point semiconductor materials such as germanium, 900°C+ temperatures
              | needed for high quality oriented crystals precludes this technique from monolithic 3DIC
              | applications.
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              | 
title         | 2.8 Graphoepitaxy by excimer laser annealing
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text          |        On the other extreme of thermal excursions are ultra short pulses of an excimer
              | laser anneal [103-107]. With absorption depths in α-Si being smaller than 100 nm and
              | pulse lengths below 100 ns, excimer laser anneal could effectively melt thin Si films
              | without any undue heating of the underlying structure, making them particularly
              | suitable to 3DIC applications [108]. In this section, graphoepitaxy of solidifying Si
              | films melted by excimer laser pulse anneal is investigated.
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              | 
text          |        Samples consist of 1D square wave nano-grating patterned by NIL in fused
              | silica substrates (SiO2), same as before. Amorphous silicon films (60 nm) are deposited
              | over the template by LPCVD at 525 °C, followed by a low temperature oxide (LTO)
              | cap (1.2 μm thick) to prevent agglomeration. Anneals were performed using a single 34
              | ns pulse of KrF excimer laser (λ = 248 nm). Beam spot was 5x2 mm rectangle of
              | Gaussian intensity profile, while the fluence was varied from 100 to 400 mJ/cm2.
              | Similar anneals of 50 nm thick α-Si on non-patterned fused silica by KrF excimer laser
              | achieved complete melt with 250 mJ/cm2 fluence [109].
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              | 
text          |        Recrystallized structure of the excimer annealed Si films was analysed using
              | cross-sectional TEM (Fig. 2.23). Because fluences greater than 200 mJ/cm2 caused
              | either agglomeration or ablation of the thin films, lower dosed samples were sectioned.
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              | 
              | 
              | 
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text          |  Figure 2.23: Cross-sectional TEM of excimer laser (KrF) annealed α-Si film on SiO2
              | nano-grating 1D template: a) after single 34 ns pulse at 192 mJ/cm2; b) dark field image
              |                         of recrystallized film after 136 mJ/cm2.
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              | 
text          |        Cross-sectional TEM images clearly show polycrystalline grains, 10-50 nm in
              | size throughout the Si film, many with discernable internal defects. Moreover, the
              | grains are randomly oriented with no influence of 1D nano-grating template. Such
              | microstructure could be expected from rapidly melted films, which consequently
              | solidify in equally rapid manner. In particular, experiments by M. Hatano et al. [110]
              | measured that solidification of KrF laser melted 50 nm thick Si films on fused silica
              | occurs within 60 ns of the laser pulse (278 mJ/cm2 fluence). Because the fused silica
              | bulk is at room temperature, the ensuing vertical cooling rates exceed 1010 °C/s.
              | Consequently, substantial undercooling takes place, triggering rapid spontaneous
              | nucleation resulting in fine grain polycrystalline film which M. Hatano et al. observed.
              | Thin Si films on patterned fused silica behaved similarly, with uncontrolled
              | spontaneous nucleation (both heterogeneous and homogeneous) seeding randomly
              | oriented grains that barely grew 10-50 nm before completely solidifying the film.
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              | 
              | 
              | 
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text          |        Achieving large grain growth in excimer laser melted Si films is therefore
              | unlikely. The uncontrolled spontaneous nucleation of rapidly cooling melt prevents any
              | appreciable grain growth. Moreover, the fast cooling Si system is far from equilibrium,
              | so the surface energy advantage of graphoepitaxially-oriented grains is not pronounced.
              | Therefore, the biggest advantage of short pulse excimer laser anneals, i.e. keeping the
              | lower layers cool and 3DIC compatible, directly causes large thermal gradients and fast
              | cooling rates that ultimately prohibit graphoepitaxy from taking place.
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              | 
title         | 2.9 Graphoepitaxy by scanned cw laser anneal
blank         | 
text          |        Scanning cw laser can anneal large areas quickly without excessive heating of
              | the substrate. Depending on the scanning speed and beam size, the dwell time, or
              | duration the laser irradiates any single point, can be made quite short and therefore
              | suitable for 3DIC applications. In the following section we explore the feasibility of
              | graphoepitaxy of thin germanium films via scanned laser anneal.
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              | 
              | 
              | 
text          | Figure 2.24: Rastered laser scan annealing of α-Ge film on top of SiO2 1-D grating. The
              | SEM image contrast delineates the zigzag shape of crystallized Ge grains. Note: 100nm
              |                 thick SiO2 cap has been removed for imaging purposes.
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              | 
              | 
              | 
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text          |        Samples containing 200 nm thick α-Ge film deposited on SiO2 square grating
              | (1D) were raster scanned at 1 cm/s using Nd:YAG laser with long scan axis along the
              | grating (Fig. 2.24). The recrystallized Ge formed zigzag shaped grains that grew
              | sequentially with each raster scan that melted a further section of the Ge film. The
              | largest of these grains can be 20 um long and up to 2-3 um wide. Experiments where the
              | laser beam was scanned perpendicular to the grating yielded very similar results.
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              | 
              | 
              | 
text          |  Figure 2.25: a) SEM image of α-Ge film on SiO2 grating after scanned laser anneal; b)
              |      resulting EBSD map of out-of-plane crystal orientation, with inverse pole plot
              |              (each grain colour corresponds to specific crystal orientation).
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              | 
text          |        Differing crystallographic orientations of grains produce a visible contrast in
              | secondary electrons emitted, as illustrated in the SEM of Fig. 2.25. A closer inspection
              | using electron backscatter diffraction (EBSD) [111] confirms that the recrystallized Ge
              | film consists of randomly oriented zigzag grains. Most likely, the first scan produced
              | randomly oriented crystallites; either by solid phase crystallization or from liquid (left
              | side of Fig. 2.25b). Consequently, these crystallites seeded grain growth into the Ge
              | melt created by subsequent laser scans, incrementally propagating the grains to the right
              | and forming the characteristic zigzag pattern. Therefore, the crystalline orientation is
              | determined by the random seeding of the first scan line rather than the square-grating
              | template, explaining the lack of graphoepitaxial orientation. In effect, the presence of
              | Ge crystallites allows epitaxial growth of existing grains with is energetically favoured
              | over the formation of a completely new Ge heterogeneous nucleation site on the SiO2
              | template [112].
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              | 
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text          |        Therefore, graphoepitaxy does not take place in films melted by scanning cw
              | laser, since the 1D template is rendered ineffective by the presence of randomly
              | oriented crystallites of the initial raster scan that seed all subsequent grain growth. One
              | possible avenue of selecting preferential crystal orientation in scanned laser anneals is
              | that of orientation filtering by crystal growth velocity competition [67]. Certain crystal
              | orientations have kinetically faster lateral growth rates, which allow them to expand at
              | the expense of slower growing grains. While this effect has been observed in the
              | scanned anneal of α-Ge film, the technique was not fully investigated.
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              | 
title         | 2.10 Summary of graphoepitaxy results
blank         | 
text          |        A summary of graphoepitaxy experiments, both from literature [93,68,73,98]
              | and from this work, is presented in Table 2.1. Annealing conditions, template structures,
              | as well as corresponding results are compared. It is interesting to note that while most
              | laser annealed films did not develop preferentially oriented grains, the one that did (2-D
              | template) had a significant degree of substrate heating. Such substrate thermal bias is
              | evident in all successful demonstrations of graphoepitaxy reported in literature (top half
              | of table). The implications of these findings are further discussed in the following
              | chapter.
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              | 
title         | 2.11 Conclusions
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text          |        We proposed a few methods of achieving single crystal regions of silicon over
              | amorphous SiO2 layers using nano-graphoepitaxy of deposited α-Si films and transient
              | laser annealing. Our one-dimensional numerical simulation showed that it is feasible to
              | use pulsed laser annealing to melt deposited layers of α-Si on the upper levels while
              | keeping within the thermal budget of the underlying circuits. In particular, for a 15 µs
              | pulse, 5 μm thick SiO2 insulating layer would limit temperature excursion at the lower
              | device level to 450 °C. The experiments using cw laser anneals indicated that patterned
              | gratings in SiO2 could determine the size and position of the grain boundaries in
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              | 
              | 
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text          | recrystallized α-Si films. However, graphoepitaxy did not occur, since the recrystallized
              | grains were randomly oriented and not influenced by the nano-grating (1-D) template.
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              | 
text          |        In addition, alternative transient heating approaches of excimer or scanned cw
              | lasers were employed to melt thin semiconductor films deposited on square-wave
              | grating template. While crystallizing grains from 30 nm to several micrometers in size,
              | neither method demonstrated graphoepitaxial orientation effect. On the other end of the
              | spectrum, solid phase graphoepitaxy required anneal temperatures far in excess of 3DIC
              | limits to grow high quality semiconductor grains on 1-D templated amorphous
              | substrate.
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              | 
text          |        Consequently, we applied a two-dimensional (2-D) template of inverted pyramid
              | structures to achieve graphoepitaxy of thin silicon films using pulsed laser annealing.
              | Experiments showed significant agglomeration of molten silicon on SiO2 surface, even
              | with 1.2 µm LTO cap present. Nonetheless, the resulting silicon islands contained
              | grains with a high degree of both in-plane and out-of-plane orientation matching that of
              | the underlying template. In addition, crystal grains up to 500 nm in diameter were
              | found to be virtually defect-free and limited by twin grain boundaries emanating from
              | template asperities. Closer examination of the thermal profiles during laser annealing
              | revealed significant heating of the substrate, which facilitated the growth of large and
              | preferentially oriented crystals by limiting undercooling. Thus, even though
              | graphoepitaxy employing nm-scale asperities was successfully demonstrated for two-
              | dimensional template using 100 µs pulsed laser annealing, film agglomeration and
              | undue heating of the substrate indicated that the result could not be exploited for
              | monolithic 3DIC applications in its present form.
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              | 
              | 
              | 
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text          |   *     Estimate. Silicon substrate below the SiO2 template melted. Exact temperature not measured independently.
              |   **    Red colour cells highlight 3DIC compatible processes and the corresponding lack of preferential crystal orientation.
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text          | Table 2.1:Summary of graphoepitaxy experiments from literature (top half) [93,68,73,98], and from this work (bottom half).
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              | 
              | 
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title         | Chapter 3 – Modeling and Simulation
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title         | 3.1 Introduction
blank         | 
text          |        The results of graphoepitaxy experiments that used transient laser annealing
              | showed very little graphoepitaxial orientation in recrystallized Si or Ge films (see Table
              | 2.1). Even with the amorphous templates placed to impart preferential crystal
              | orientation, most grains ended up randomly oriented and usually much smaller than a
              | micron in size. On the other hand, large and highly oriented films achieved by
              | graphoepitaxy have been reported in literature [93,68,73,98], albeit at much higher
              | temperatures which are incompatible with monolithic 3DIC requirements [35,36].
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              | 
text          |        In order to gain better understanding of the crystallization process, we have
              | developed a simulation algorithm that models the nucleation and grain growth
              | phenomena in laser melted semiconductor films. Furthermore, a test structure is
              | fabricated, annealed and examined to experimentally validate the results of the
              | simulation. Finally, general findings are used to explain the crystalline microstructure of
              | laser annealed graphoepitaxy samples.
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              | 
title         | 3.2 Classical crystallization theory
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text          |        The process of solidification of liquid semiconductor material into crystalline
              | grains is considered here as a first order phase change process consisting of nucleation
              | of individual grains and their subsequent growth. Therefore, to model these processes,
              | established classical crystallization theory [113-118] has been adopted.
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              | 
text          |        When a liquid is cooled down to a temperature lower than its melting point
              | (T<TM), it has a tendency to transform to solid phase. The free energy difference
              | between the undercooled liquid and the solid phase provides the driving force for this
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              | 
              | 
              | 
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text          | transition. Depending whether the spontaneous nucleation occurs in the liquid bulk or at
              | an interface with the solid container, it can be classified as either homogeneous or
              | heterogeneous nucleation, respectively (Fig. 3.1). The difference in total energy change
              | ΔGT corresponding to the formation of a nucleating particle is due to the extra
              | interfacial term of heterogeneous nucleation, which accounts for the energy required for
              | a creation of new nucleus interface of area Asw with the container wall.
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              | 
              | 
              | 
text          |  Figure 3.1: Nucleation mechanisms in liquid material in solid (SiO2) container. ΔGV is
              | the absolute value of the Gibbs free energy change per unit volume associated with the
              |  liquid-solid phase transformation, γls is the liquid-solid interface energy, while γsw and
              |                γlw are interface energy related to the SiO2 container wall.
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              | 
text          | The balance of interfacial energies determines the contact angle θ that the solid nucleus
              | makes with the wall: γ lw = γ sw + γ ls cos θ . Therefore, a generalized expression can be
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text          | developed for ΔGT of a nucleus or radius r:
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text          |               ⎛ 4                      ⎞
              |         ΔGT = ⎜ − πr 3 ΔGV + 4πr 2γ ls ⎟ S (θ ) , where
              |               ⎝ 3                      ⎠
              |                S (θ) = 1 for homogeneous nucleation, and
              |                           1
              |                S (θ ) =     (2 + cos θ )(1 − cos θ ) 2 for heterogeneous nucleation.
              |                           4
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text          | Consequently, since S(θ) ≤ 1, there is a reduction in nucleation barrier related to
              | heterogeneous nucleation (ΔG*Het), compared with the homogenous nucleation case
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              | 
              | 
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text          | (ΔG*Hom), as can be seen in Fig. 3.2. For example, in the case of germanium liquid on
              | SiO2 surface, θ = 72° [112], thus critical nuclei are more likely to spontaneously form at
              | the interface, rather than in bulk liquid.
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              | 
              | 
              | 
text          |  Figure 3.2: Even though the size of the critical nucleus (r*) is the same, the nucleation
              | energy barrier for heterogeneous integration (ΔG*Het) is lower than that of homogeneous
              |                             nucleation (ΔG*Het) by a factor S(θ).
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              | 
text          | Following the formalism of Becker-Döring theory of nucleation [119,120] and detailed
              | considerations of the atomic processes involved, Y. Liu et al. [112] arrived at these
              | useful expressions for homogeneous and heterogeneous nucleation rates [121, 122]:
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text          |                                                  1
              |                          NσA*ν o    ⎛ ΔG Hom
              |                                          *
              |                                                ⎞2   ⎛ ΔG Hom
              |                                                          *
              |                                                                  ⎞     ⎛ ΔG M'    ⎞
              |                I Hom   =            ⎜          ⎟ exp⎜ −          ⎟ exp⎜⎜ −        ⎟⎟
              |                            n*       ⎜ 3πkT     ⎟    ⎜   kT       ⎟
              |                                     ⎝          ⎠    ⎝            ⎠     ⎝ kT        ⎠
              |                                                      1
              |                        Aσ A ν         ⎛ ΔG       ⎞    ⎛ ΔG Het    ⎞     ⎛ ΔG M'   ⎞
              |                             2   *          *         2      *
              |               I Het   = w * ls o      ⎜    Het
              |                                                  ⎟ exp⎜ −         ⎟ exp⎜⎜ −       ⎟⎟
              |                                       ⎜ 3πkT     ⎟    ⎜   kT      ⎟
              |                           n           ⎝          ⎠    ⎝           ⎠     ⎝ kT       ⎠
blank         | 
text          | where N is the total number of atoms in the system, A* is the surface area of the
              | nucleating particle, σ is the area density of atomic attachment sites on the nucleus, νo is
              | the atomic vibration frequency, ΔG’M is the activation energy for a liquid atom to attach
              | onto the particle, n* is the number of atoms in the critical nucleus, Aw is area of interface
              | with the wall, while Als is the area of liquid-solid interface.
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              | 
              | 
              | 
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text          |        Once stable nuclei form, they will start growing with more atoms jumping
              | across the liquid-solid interface and forming new layers on the crystal solid. In this
              | dynamic process, the sticking rate is faster than the dissolving rate due to a net
              | difference in activation energies ΔGN [123], causing phase transition. Thus, if a is the
              | distance gained per layer of new atoms, the growth velocity can be expressed as [124]:
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text          |                                      ⎛ ΔGM"   ⎞⎡        ⎛ ΔG N   ⎞⎤
              |                         U = aν o exp⎜⎜ −      ⎟⎟⎢1 − exp⎜ −      ⎟⎥
              |                                      ⎝ kT      ⎠⎣       ⎝ kT     ⎠⎦
blank         | 
text          | where ΔG”M is equivalent to the liquid self-diffusion activation energy of the
              | crystallizing material. The full details of the derivation of crystal growth velocity can be
              | found in references [112, 123, 124].
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              | 
text          |        Consequently, after gathering relevant thermo-physical parameters [112-124],
              | the homogeneous and heterogeneous nucleation rates for undercooled germanium liquid
              | can be calculated as a function of temperature (Fig. 3.3). As expected, heterogeneous
              | nucleation on SiO2 surface occurs before homogeneous nucleation due to a reduction in
              | nucleation energy barrier.
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              | 
              | 
              | 
text          |       Figure 3.3: Homogeneous (red) and heterogeneous (blue) nucleation rates in
              |     undercooled Ge liquid stripe (40x1x0.1µm) surrounded by SiO2 as a function of
              |                         temperature: a) log scale; b) linear scale.
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              | 
text          | More importantly, it seems that spontaneous nucleation is highly unlikely to occur until
              | significant undercooling takes place (~240 °C), after which the rate rises sharply,
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              | 
              | 
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text          | causing an explosion in spontaneous nucleation at the heterogeneous interfaces. In
              | addition, the Ge crystal growth velocity as a function of undercooling has been
              | calculated, with typical values varying between 1.5 - 2.5 m/s [112].
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              | 
title         | 3.3 Test structure – model and fabrication
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text          |        In order to investigate crystallization phenomena in undercooled semiconductor
              | liquids, a representative model has been developed (Fig. 3.4). The 1-D structure consists
              | of a 100 nm thick layer of amorphous germanium on top of oxidized Si substrate,
              | capped with 100 nm of SiO2. Germanium was specifically chosen so that crystallization
              | due to spontaneous nucleation as well as seeded nucleation from attached Si (100) seed
              | could be examined and compared. In particular, lower melting temperature of Ge
              | permits the Si crystal seed to remain solid while α-Ge is melted via laser annealing.
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              | 
              | 
              | 
text          |  Figure 3.4: a) Simplified test structure for 1-D thermal diffusion modeling, as well as
              |   nucleation and grain growth model; b) cross-section of fabricated structure showing
              |    attached Si (100) seed and α-Ge thin stripe to be laser crystallized. (Not to scale).
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              | 
text          |        The test structure designed to validate the model was fabricated on oxidized Si
              | wafers with ~120 nm LPCVD α-Ge deposited at 300 °C, patterned into 1x40 µm stripes
              | and capped with ~100 nm of LTO. Some of the samples had 2x2 µm islands of Si (100)
              | seed transferred via hydrophilic fusion bonding (see Chapter 4). Extreme care needed to
              | be taken to ensure epitaxial contact between deposited Ge and the Si seed, by
              | preventing native oxide (SiO2) formation. These included reduced DI water rinse time,
              | spin-drying in N2 ambient and lowering the LPCVD chamber temperature (<200 °C)
              | prior to loading the samples. Laser annealing was accomplished using frequency
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              | 
              | 
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text          | doubled Nd:YAG laser (λ = 532 nm) with 5x5 mm spot size. In order to selectively melt
              | Ge, a single pulse of 40 ns (FWHM) duration and 180 mJ/cm2 dose was empirically
              | found to keep the Si (100) seed intact while fully melting the Ge stripe. In addition a set
              | of samples was rapid thermal annealed (RTA) at 960 °C for 1 second and passively
              | cooled in N2 (g) ambient.
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              | 
title         | 3.4 Algorithm
blank         | 
text          |        Our simulation algorithm first calculates the temperature evolution of molten Ge
              | in a simplified 1-D structure presented in Figure 3.4 using the one dimensional heat
              | diffusion model [37,62]. As the Ge liquid undercools from the initial 937 °C, the heat
              | diffuses through 200 nm of SiO2 into the underlying Si substrate, which acts as a heat
              | sink. Radiative and convective losses are comparatively negligible, and are therefore
              | ignored. Similarly, Si (100) seed only serves as an interface for seeded epitaxial growth
              | of germanium. To simplify the simulation, Ge undercooled liquid is considered
              | isothermal with no local thermal gradients. Therefore, the latent heat released during
              | phase transition is instantaneous and accounted for globally, slowing down the cooling
              | rate of the remaining Ge liquid.
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              | 
text          |        The crystallizing layer of liquid Ge is represented by a 2-D finite element mesh
              | with 1 nm spatial resolution. At each time step (1 ns long), homogenous and
              | heterogeneous nucleation rates, as well as crystal growth velocity, are calculated for the
              | prevailing temperature. Consequently, Monte Carlo method is used to determine
              | whether spontaneous nucleation takes place at each mesh element: heterogeneous for
              | perimeter elements at SiO2 interface, or homogeneous for bulk elements. Once a
              | nucleus appears, it increases in size isotropically, growing into the undercooled liquid at
              | calculated growth velocity until it impinges upon other grains or the SiO2 interface. In
              | the case of mesh points at the Si (100) seed interface, epitaxial growth of Ge (100)
              | crystal is assumed to be immediate even though there may be some delay involved due
              | to 4% lattice mismatch. The algorithm proceeds until all of the Ge liquid elements have
              | crystallized (became solid).
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              | 
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title         | 3.5 Results
blank         | 
text          |        Our simulation algorithm has been first used to model crystallization of
              | amorphous Ge melted using pulsed laser anneal and in absence of any crystal seed.
              | Upon laser melting, the liquid Ge (at 937 °C) creates a large vertical thermal gradient
              | with respect to the Si substrate, which is held at temperatures below 400 °C for 3DIC
              | compatibility. As the heat diffuses through the 200 nm thick SiO2 layer, the liquid
              | quickly undercools at an approximate rate of –300 °C/µs. Without a crystalline seed to
              | nucleate growth, Ge continues to undercool until at critical temperature spontaneous
              | random nucleation is triggered. Consequently, an avalanche of heterogeneous nuclei
              | appear at the SiO2 interface seeding many grains that quickly grow into the remaining
              | undercooled liquid. In turn, these expanding grains impinge upon each other, resulting
              | in fine grain polycrystalline Ge structure (Fig. 3.5).
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              | 
              | 
              | 
text          |  Figure 3.5: a) Single pulse (~40ns) laser anneal of 180 mJ/cm2 is used to melt 120 nm
              | thick α-Ge stripe; b) liquid Ge at 937 °C undercools as the heat diffuses to Si substrate;
              |  c) simulation result: spontaneous heterogeneous nucleation crystallizes the liquid into
              |                                 polycrystalline germanium.
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              | 
text          |        TEM cross-section of the laser annealed Ge stripe (Fig. 3.6) also shows
              | polycrystalline structure, agreeing with the simulation result. Indeed, solidification of
              | deeply undercooled Ge liquid seems to have been dominated by spontaneous
              | nucleation, resulting in multitude of randomly oriented grains less than 50 nm in size.
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              | 
              | 
              | 
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text          |   Figure 3.6: TEM cross-section of laser annealed Ge stripe indicating polycrystalline
              |        structure due to spontaneous nucleation in deeply undercooled Ge liquid.
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              | 
text          |        In the case of seeded crystallization [52-56], simulation showed that upon laser
              | melting, epitaxial growth of the Ge (100) grain from the solid Si (100) seed occurs
              | immediately. The oriented grain expands freely into the rapidly cooling liquid before it
              | is interrupted by a sudden onset of spontaneous nucleation (Fig. 3.7). Again, significant
              | heat dissipation to the underlying Si substrate quickly undercools Ge melt (ΔT >
              | ~200°C) resulting in conditions suitable for random nucleation, which ultimately
              | prevents seeded grain growth from proceeding for long distances.
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              | 
text          |        Experimental results show seeded Ge grain growth resulting in ~500 nm long
              | single crystal grains after a single 180 mJ/cm2 laser pulse. While there are a few twin
              | defects, the crystal is generally of high quality and matches the Si (100) seed orientation
              | exactly. Given that the seeded grain grew only 500 nm before impinging on
              | spontaneously nucleated grains, the crystallization must have taken place rather rapidly
              | (under 0.5 µs), indicating cooling rates on the order of –400 °C/µs. Overall, the TEM
              | investigations indicated close agreement with the simulation results.
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              | 
text          |        Finally, in the third scenario rapid thermal annealing (RTA) was used to heat the
              | whole wafer to 960 °C for 1 sec to ensure Ge fully melts while maintaining the Si (100)
              | seed intact. The bulk temperature of the passively cooled wafer was measured using a
              | pyrometer, and it fell at a rate of ~ 100 °C/s upon annealing, or 0.0001 °C/µs. Since the
              | thermal mass of the wafer is much larger than that of the Ge stripe, the cooling rate of
              | liquid Ge was equally slow, allowing for very long Ge (100) grains to crystallize (Fig.
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              | 
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text          | 3.8). In effect, slow cooling rates kept the Ge liquid close to melting temperature for
              | hundreds of microseconds, limiting the degree of undercooling. Therefore, spontaneous
              | nucleation was effectively suppressed allowing for interrupted epitaxial Ge growth for
              | hundreds of microns. High resolution TEM cross section of the RTA annealed test
              | structure demonstrates defect-free, high-quality Ge (100) crystallized grains on
              | amorphous SiO2 up to 40 µm away from the seed region (or full length of the Ge
              | stripe). Formation of such long seeded crystals is in agreement with rapid melt growth
              | results reported by Feng et al. [52].
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              | 
              | 
              | 
text          |  Figure 3.7: Laser annealed Ge stripe crystallization with a Si (100) seed: a) simulation
              |   result: seeded epitaxial growth gets interrupted by spontaneous nucleation; b) TEM
              | cross-section of the test structure annealed by a single 180 mJ/cm2 pulse agrees with the
              | simulation result; c) epitaxially grown Ge (100) grain with corresponding SAD pattern;
              |      d) fine grain poly-Ge region seeded by spontaneous heterogeneous nucleation.
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              | 
              | 
              | 
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text          | Figure 3.8: RTA anneal (960 °C, 1 sec) of Ge stripe crystallization with a Si (100) seed:
              |    a) both simulation and the test structure show unimpeded grain growth of seeded
              |  Ge(100), up to 40 µm long; b) HR XTEM demonstrating high-quality defect-free Ge
              |     (100) grain on SiO2 substrate with corresponding single crystal SAD pattern c).
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              | 
text          | Heating the substrate to 960 °C would certainly not be considered 3DIC compatible,
              | however, it does reveal that slowing the cooling rates by reducing the vertical thermal
              | gradient can effectively suppress random nucleation from occurring.
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              | 
title         | 3.6 Conclusion and implications for graphoepitaxy
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text          |        Transient annealing techniques, such as pulsed laser annealing are effective
              | methods to radiatively melt thin layers of semiconductors without unduly heating the
              | underlying layers of a 3DIC [88]. However, the resulting temperature difference
              | between the molten Ge (937°C), or Si (1412°C), and the substrate (<400°C) causes very
              | fast cooling rates, on the order of 300 °C/µs. This inherently large thermal gradient
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              | 
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text          | quickly undercools the liquid, triggering uncontrolled spontaneous nucleation that limits
              | both the size and quality of resulting grains.
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              | 
text          |        Assuming that graphoepitaxy is fundamentally a preferential nucleation process
              | [70], heterogeneous nuclei of preferential crystal orientation should be energetically
              | favoured. Therefore statistically, they should appear on the amorphous SiO2 template
              | before the randomly oriented spontaneous nuclei. However, H.I. Smith et al. [92] have
              | calculated that melting temperature of preferentially oriented Si grain to be less than a
              | degree (<1°C) higher than the average randomly oriented one. Such a notion would
              | suggest that preferential nucleation of graphoepitaxial grains in undercooled liquid
              | should also occur only a degree or so before general spontaneous nucleation begins.
              | Consequently, cooling rates would need to be sufficiently slow (<<1°C/µs) to allow for
              | appreciable growth of graphoepitaxial grains before being drowned out by random
              | heterogeneous nucleation.
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              | 
text          |        Successful demonstrations of Si or Ge graphoepitaxy [93,68,73,98] inevitably
              | use thermal biasing of the substrate or high power IR strip heaters to ensure reduced
              | cooling rates, which effectively suppress random nucleation. In the case of 3DIC
              | compatible scenarios where substrate temperature cannot exceed 400 °C, such biasing is
              | not possible, while greater thermal insulation (SiO2) would lead to excessively thick
              | inter-layer dielectrics. A possible approach to 3DIC compatible graphoepitaxy would be
              | to use a train of laser pulses with diminishing intensity. Once the semiconductor
              | material melts, the subsequent pulses would keep the liquid warm, effectively reducing
              | the cooling rate. Such a scenario could possibly yield preferentially oriented grains
              | without damaging the underlying layers of a monolithic 3DIC.
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              | 
text          |        Since graphoepitaxy has been found to be unsuitable for low-temperature
              | monolithic 3DIC fabrication, alternative approaches such as semiconductor crystal
              | island transfer are explored in the following chapters.
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              | 
              | 
              | 
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title         | Chapter 4 – Aluminum-Germanium Bonding
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title         | 4.1 Introduction
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text          |        In an effort to identify a low-temperature bonding technique that would satisfy
              | many of the requirements needed for successful monolithic 3D integration, we propose
              | aluminum-germanium (Al-Ge) eutectic bonding. Al-Ge has been effectively used to
              | package and hermetically seal fabricated MEMS devices, thanks to the eutectic liquid
              | alloy that forms at the bonding interface at 424 °C [125]. This transition to liquid phase
              | at the eutectic temperature is the key advantage of all eutectic bonding techniques,
              | including the more familiar gold-silicon eutectic bonding (Au-Si) at 363 °C [126].
              | Consequently, the Al-Ge eutectic alloys have been shown to generate strong and void-
              | free bonds, even on rough surfaces. Furthermore, Al-Ge could be particularly applicable
              | to 3D integration, given that the materials involved are CMOS process compatible
              | (unlike Au-Si), and could also provide a conductive path upon bonding. However, the
              | processes so far reported [127-129] are not suitable for 3DICs, having either too high a
              | bonding temperature or pressure or requiring excessively thick films (~4 µm).
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              | 
              | 
              | 
text          |  Figure 4.1: Aluminum-germanium binary alloy phase diagram. Even though pure Al
              | melts at 600°C, and pure Ge close to 940°C, the eutectic alloy of 30.3% Ge in Al melts
              |                   at a significantly lower temperature of 424 °C [125].
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              | 
              | 
              | 
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text          |        Therefore, experiments were performed to determine whether low-temperature
              | (435 °C), low-pressure (200 kPa) bonding using thin Al-Ge films (157 nm) could be
              | used for wafer scale integration. Fracture energy of the bond was measured, and the
              | interface microstructure examined by Auger electron spectroscopy (AES), focused-ion-
              | beam (FIB), and transmission electron microscopy (TEM). Ultimately, the new and
              | improved Al-Ge eutectic bonding technique was applied to attach silicon islands for
              | monolithic 3DIC integration.
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              | 
title         | 4.2 Experimental Details
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text          |        Al-Ge eutectic bonding was tested using 100 mm diameter n-type Si (100)
              | wafers that have been RCA cleaned and thermally oxidized to create typically 100 nm
              | of SiO2. This layer serves as a diffusion barrier during bonding. Blanket aluminum and
              | germanium films were deposited sequentially onto the wafers using Innotec ES26C E-
              | beam evaporator in a single pump down. The samples were cleaned in Piranha solution
              | (H2SO4:H2O2 = 4:1 at 120 °C) for 20 min, followed by deionised water (DI) rinse and
              | spin drying prior to being introduced into the chamber. The wafer temperature never
              | exceeded 40 °C during evaporation, while the deposition rate was ~5 Å/s for both
              | materials. Germanium was chosen as the capping layer because it is much easier to
              | chemically remove native germanium oxide (GeO2), which is soluble in water,
              | compared to native aluminum oxide (Al2O3). The thicknesses of the films deposited
              | were chosen to match the Al-Ge eutectic composition (70 at% Al and 30 at% Ge),
              | which should melt at the eutectic temperature of TE = 424 °C (Fig. 4.1) [125] and thus
              | form the bond. Taking into account the densities (ρ) and atomic weights (A) of Al and
              | Ge, the ratio of thicknesses could be calculated as:
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text          |                             t Ge at % Ge ρ Al AGe
              |                                 =                 = 0.59
              |                             t Al at % Al ρ Ge AAl
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text          |        Therefore, for a 100 nm thick Al film, 59 nm of Ge was deposited on top. The
              | surface roughness of as-deposited bilayer structure (157 nm thick) was 3.48 nm RMS
              | (root mean square), as measured by Veeco Dimension 3100 atomic force microscope
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              | 
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text          | (AFM). Figure 4.2a presents an AFM surface scan of a particularly thin bilayer stack
              | (47 nm), while the cross-sectional scanning electron micrograph gives a general idea of
              | the structure (b).
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              | 
              | 
              | 
text          |  Figure 4.2: a) AFM scan (5x5 µm) of as-deposited bilayer (30nm Al + 17nm Ge) with
              |   surface roughness of 1.63nm RMS; b) FIB cross-section of evaporated Al-Ge stack
              |      (300nm Al + 175nm Ge) on top of SiO2 diffusion barrier. Note: the Ge surface
              |                  roughness in (b) is due to Ga+ ion milling process (FIB).
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              | 
text          |         The bond tests were conducted with different bilayer thicknesses (from 48 nm to
              | 475 nm), bonding temperatures (400-550 °C) and configurations (one sided and two
              | sided). The one sided configuration had Al-Ge film deposited only on one of the two
              | mating wafers (the other wafer had bare SiO2), while the two-sided configuration had
              | Al-Ge on both. Immediately prior to bonding, both wafers to be bonded were dipped in
              | dilute hydrofluoric acid (2% HF) for 30 s to remove native germanium oxides, followed
              | by DI water rinse and spin dry. Megasonic DI water jet clean was also used to remove
              | any large particle contamination from the wafer surface.
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              | 
text          |         The bonding step was performed in EV501 Bonder (EV Group), typically at 435
              | °C for 30 min with a downward force of 3 kN (or ~350 kPa over 100 mm diameter area)
              | at a base vacuum of ~1 x 10-4 Torr. The applied pressure and uniformity were measured
              | independently using pressure sensitive paper (Pressurex®). The heating took place in
              | under an hour, while the cooling rate was approximately 3 °C/min, limited by the
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              | 
              | 
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text          | thermal mass of the chuck assembly. The bonding temperature of 435 °C was chosen to
              | insure eutectic melt (Fig. 4.1), while keeping it as low as possible to be suitable for
              | 3DIC applications.
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              | 
text          |        Structural strength of the bonded wafer pairs was initially examined
              | qualitatively using razor blade insertion test. An accurate measurement of the Al-Ge
              | bond strength was achieved utilizing a double cantilever beam thin-film adhesion
              | measurement technique [130] (see next section).
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              | 
              | 
              | 
text          |    Table 4.1: Summary of Al-Ge eutectic bonding conditions: all bonding tests were
              |                performed utilizing both one and two-sided configurations.
              |               *
              |                   For the 400 °C tests, bonding time was set to 120 minutes.
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              | 
text          |        The samples were inspected for voids with C-mode scanning acoustic
              | microscope (SAM) fitted with a 230 MHz transducer and a spatial resolution of 5-10
              | µm. In order to investigate the bond microstructure, Auger electron spectroscopy (AES)
              | was performed to collect chemical depth profiles and interface element maps. Phi
              | Scanning Auger Nanoprobe model 700 was operated at 10 kV with 10 nA of beam
              | current, while Ar+ ion sputtering at 3 keV with a current of 3 μA allowed for depth
              | profiling of Al, Ge, Si, O and C species. The last two elements were included to monitor
              | possible presence of contamination or oxidation that may have occurred during the
              | bonding process. Finally, cross-sectional analysis of the bonded area was achieved by
              | FIB and TEM.
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              | 
              | 
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text          | Figure 4.3: Wafer flat area of 4-inch wafer pair bonded at 450°C showing a small drop
              | of solidified Al-Ge alloy that has been squeezed out during the bonding step. Thus, Al-
              |               Ge bilayer alloy does indeed melt above eutectic temperature.
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              | 
title         | 4.3 Strength of Al-Ge eutectic bond
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text          |         To test structural integrity of the Al-Ge eutectic bond, razor blade insertion test
              | was performed on all of the bonded wafer pairs (see Table 4.1). They all remained
              | intact, i.e. there was no wafer-scale splitting. After applying significant force, small
              | pieces at the edge would chip off, cracking through the silicon bulk. Only the wafer
              | pairs bonded by 48 nm Al-Ge bilayer at 435 °C did show some weakness, having larger
              | pieces split off.
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              | 
text          |         Quantitative measurement of the bond strength was accomplished using double
              | cantilever beam (DCB) thin-film adhesion measurement technique [130]. DCB method
              | was chosen because it is accurate and yields repeatable measurements with low scatter.
              | In this technique, the adhesive failure of the bond at interface between two materials
              | can be modeled as a crack propagating along that interface, allowing one to apply
              | theories of fracture mechanics originally developed for bulk materials. Adhesion is
              | characterized by measuring the amount of energy required, per unit area, to propagate
              | the crack along an interface (Gc). This value is a quantity known in fracture mechanics
              | as the critical crack extension force.
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              | 
              | 
              | 
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text          | Figure 4.4: a) Double cantilever beam technique sample schematic showing the debond
              | length caused by tension forces applied at the end of the beams through metal tabs (b).
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              | 
text          |        In the double cantilever beam configuration, the ends of Al-Ge bonded beams
              | are pulled apart, forcing a crack to propagate down its length (Fig. 4.4). Loads are
              | applied to the sample through metal tabs epoxy glued to the beams. The force pulling
              | the beams apart (P) causes bending of the beams that stores elastic strain energy. This
              | energy is released as the crack extends along the interface, defining a debonding length
              | (a). Consequently, the crack extension force (Gc) generated during the DCB experiment
              | can be calculated from [130] using the following approximation:
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text          |                                    P 2a 2
              |                                   BhE
              |                                              (
              |                          GC = 12 ⋅ 2 3 1 + 0.64 ⋅ h ,
              |                                                    a
              |                                                      2
              |                                                            )
              | where E is the Young’s modulus of silicon beams. In addition, double cantilever
              | method is considered a pure mode I (tension) fracture strength measurement,
              | distinguishing it from mode II (shear) or mixed mode techniques [131]. This property is
              | significant, as it minimizes plastic deformation (Gp) component of the fracture energy
              | (Gc), and thus measures the chemical work of adhesion (Go) component. Therefore,
              | using DCB method would give the mode I value of Gc ≈ Go, which is a more
              | representative measure of bond toughness [132]. Finally, mode I measurements are best
              | for measuring cohesive failure (which occurs within the bulk of the bonding material,
              | such as the case of the AlGe samples), while mixed mode measurements are better at
              | measuring adhesion failure (between interfaces).
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              | 
              | 
              | 
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text          |  Figure 4.5: Measured bond strength of copper-copper bond under pure Mode I tension
              |  is about Gc = 2.5 J/m2 [134]. This value is much smaller compared to measured Al-Ge
              |                       bond fracture energy of Gc = 50 J/m2 [133].
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              | 
text          | For the case of Al-Ge eutectic bonding, the DCB measurement was performed on two-
              | sided, 318 nm thick bilayer Al-Ge samples, bonded at 435 °C for 30 minutes. The
              | fracture energy of the Al-Ge eutectic bond was found to be Gc = 50.5 ± 12.7 J/m2 when
              | experiencing mode I (tension) loading [133]. The fracture energy can be thought of as
              | the amount of energy needed to separate two Al-Ge surfaces per unit area. Compared to
              | pure mode I strength measurements for similar copper-copper bonds at 400 °C, which
              | measure around 2.5 J/m2 [134], Al-Ge eutectic bonds appear to be an order of
              | magnitude tougher (Fig. 4.5). One hypothesis is that the internal segregated dendritic
              | structure of Al-Ge bonds makes the bond stronger, with its non-uniform morphology.
              | Another likely possibility is that there is still a significant contribution from plastic
              | deformation within the Al-Ge layer, increasing the measured value of Gc above the pure
              | chemical work of adhesion.
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              | 
              | 
              | 
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title         | 4.4 Void formation in Al-Ge eutectic bonds
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text          |         Investigation of the interface of Al-Ge bonded 100 mm diameter wafers using
              | SAM revealed nearly void-free bonding (Fig. 4.6). The 5 mm void present in the center
              | of the image is due to a known weak pressure point, caused by the graphite backing
              | plate design. The non-uniformity in the applied pressure across the wafer pair was
              | confirmed using pressure sensitive paper to map the distribution (Fig. 4.7). Thus, it is
              | quite remarkable how tolerant the Al-Ge eutectic bonding mechanism is to the non-
              | uniformities in applied pressure, forming a solid and void-free bond over the whole
              | wafer (excluding the center).
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              | 
              | 
              | 
text          | Figure 4.6: Scanning acoustic microscope (SAM) image of 4-inch wafer pair bonded at
              |    435 °C with 2.2 kN applied force (200 kPa) for 30 min (condition A). The Al-Ge
              |  eutectic bonding achieves a nearly void-free bond, with a single defect (white) in the
              |  center due to a known pressure weak spot. Note: white areas are voids, black areas are
              |              solid bond, while the faint grey lines are due to Ge dendrites.
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              | 
text          |         The reason is that the liquid phase nature of the Al-Ge eutectic at 424 °C and
              | above ensures intimate contact between the mating wafer pairs by wetting and flowing
              | around surface roughness. Thus, unlike solid phase thermo-compressive bonding (e.g.
              | Cu-Cu, Ti-Ti), large applied pressure is not required to form a solid and bubble-free
              | bond.
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              | 
              | 
              | 
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text          |    Figure 4.7: Map of pressure distribution over a 4-inch wafer placed under 3.3 kN
              |  downward force (350 kPa) applied by the bonder. Measurement was performed using
              |                            Pressurex® pressure sensitive paper.
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              | 
text          | However, it should be noted that at sub-eutectic (400 °C) bond temperatures where no
              | melt occurs, Al-Ge bond quality strongly depends on applied pressure. Because no melt
              | occurs below eutectic temperature (TE) physical contact is required for a bond to form.
              | Thus, with larger applied pressures the wafers are forced into contact.
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              | 
title         | 4.5 Bond morphology of Al-Ge eutectic bond
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text          |        Microstructure of the Al-Ge bond was revealed by grinding the bulk of the top
              | silicon wafer, followed by a potassium hydroxide (KOH) solution etch (30% conc.,
              | 70°C) that stopped at the SiO2 layer located at the interface. Plan view of the exposed
              | Al-Ge bonding layer (Fig. 4.8) through the remaining SiO2 shows dendritic segregation
              | of the eutectic alloy upon solidification.
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              | 
              | 
              | 
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text          | Figure 4.8: Plan-view optical (a) and SEM (b) images showing the microstructure of the
              |  Al-Ge eutectic bond formed at 450 °C (condition A). The top wafer has been ground
              | and etched away to reveal Al-Ge layer segregated into germanium dendrites (light grey)
              |                         within an aluminum matrix (dark grey).
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              | 
text          |        A closer analysis using AES identified Ge dendrites (light grey), several microns
              | long and about a micron wide, embedded in an Al matrix (dark grey), as illustrated in
              | Figure 4.9. The geometric structure is typical of Al-Ge system [135], in which
              | solidification takes place at the eutectic temperature where the two distinct liquidus
              | curves meet. At this temperature both Al and Ge solid phases must deposit on the
              | respective grain nuclei until all of the liquid is converted into solid. The simultaneous
              | deposition results in a distinct microstructure unique to the alloy, and is usually
              | observed in slowly cooled (i.e. not quenched) samples. This mesh structure and the
              | resulting large surface area between the Ge dendrites and Al matrix could be the cause
              | of its strong mechanical bond [135].
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              | 
              | 
              | 
text          | Figure 4.9: AES elemental map of Al-Ge eutectic bond formed at 450°C. As the bond is
              |       cooled, the eutectic alloy segregates into solid Ge dendrites in an Al matrix.
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              | 
              | 
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text          |        The Auger depth profile of the Al-Ge bond was obtained by Ar+ ion sputtering
              | of the bonded and backside thinned sample above (Fig. 4.10). The sputtering rate was
              | about 50 nm/min calibrated on SiO2 substrate (approx. 12 nm/min on Al-Ge). Both
              | wafers originally had 300 nm of Al and 175 nm Ge evaporated prior to bonding at 450
              | °C, yet the depth profile delineates six alternating layers of germanium and aluminum.
              | As expected, the original bonding interface cannot be identified due to the eutectic melt,
              | and the Al and Ge phases are nearly pure due to low solid solubility of each in the other
              | [125]. The level of atomic oxygen throughout the Al-Ge bond is less than 5 at%, while
              | it is strongly present (~55 at%) in the 100 nm thick SiO2 layer grown on the bulk silicon
              | wafer. As well, carbon concentration is quite low, suggesting that sources of
              | contamination were limited.
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              | 
              | 
              | 
text          |     Figure 4.10: Auger depth profile of Al-Ge eutectic bond formed at 450 °C, after
              | backside grinding and etching. The dendritic phase separation occurs vertically as well,
              |   forming six alternating layers of Al and Ge upon solidification of eutectic melt. The
              |                         initial bonding interface is indiscernible.
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              | 
              | 
              | 
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text          |        In addition, SiO2 appears to be an effective diffusion barrier that prevents fast
              | diffusing silicon atoms [136] from entering Al-Ge eutectic system from the bulk. Such a
              | barrier is required because the presence of elemental silicon creates Al-Si-Ge tertiary
              | alloy whose melting temperature is higher than 424 °C [125]. Consequently, the tertiary
              | non-eutectic composition would prevent melting during bonding, thus degrading the
              | quality of the bond. It should be noted that a conductive material, such as thin titanium
              | nitride (TiN), could be used as a Si diffusion barrier [137]. Silicon diffusivity in fine-
              | grain TiN at 600 °C is about 1 x 10-20 m2/s [138], making it an excellent diffusion
              | barrier. Consequently, Al-Ge bond layer could be utilized as a conductive path going
              | through TiN barrier for backside contacts or other such applications.
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              | 
              | 
              | 
text          |   Figure 4.11: Cross-section TEM of Al-Ge eutectic bond formed at 435 °C in 1 hour.
              |   The void-free bonding layer consists of laterally segregated Al and Ge domains that
              |  span the thickness of the film (~100nm), as indicated by the local EDS spectra shown.
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              | 
text          |        Cross-section TEM investigation of Al-Ge eutectic bond formed at 435 °C for
              | one hour clearly depicts lateral segregation of Al and Ge phases. By focusing the TEM
              | electron beam spot (40 nm) within the Al-Ge bond layer, energy dispersive X-ray
              | spectroscopy (EDS) spectrum was collected and chemical composition analysed. The
              | light coloured domain in Figure 4.11 consisted of 95% aluminum, while the dark region
              | contained 91% germanium, again confirming the high degree of elemental segregation
              | that occurred upon solidification of the eutectic alloy.
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              | 
              | 
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text          |        However, unlike the alternating layers of Al and Ge in Auger depth profile of
              | Figure 4.10, the Al and Ge domains here span the full thickness of the film (~100 nm).
              | Given that both SiO2 mating wafers originally had 450 nm thick Al-Ge bilayers each, it
              | is surprising to find such a thin bond as a result. Significant mass flow of liquid Al-Ge
              | alloy must have occurred under applied bonding pressure. Nevertheless, the final bond
              | is void free and forms a solid connection between the SiO2 surfaces (Fig. 4.12).
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              | 
              | 
              | 
text          |  Figure 4.12: TEM cross-section of Al-Ge eutectic bond layer: a) Al forms long (up to
              | 10 μm) grains while Ge is polycrystalline; b) HRTEM of Al crystal lattice fringes with a
              |                            single stacking fault defect shown.
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              | 
title         | 4.6 Attaching silicon islands by Al-Ge eutectic bonding
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text          |        To achieve monolithically integrated 3DIC, a region of high quality crystalline
              | semiconductor material is required to fabricate upper level devices in situ, on top of
              | existing circuitry. With this motivation, low-temperature Al-Ge eutectic bonding of
              | patterned silicon islands onto amorphous SiO2 substrates at 435 °C has been
              | demonstrated.
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              | 
text          |        The donor wafer consisted of an array of Si islands, 20 µm in size, with 40 µm
              | pitch, that were to be transferred onto the acceptor wafer. In order to avoid laborsome
              | backside grinding and etching, the attached crystalline Si islands could be split from the
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              | 
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text          | bulk donor wafer via Smart-Cut® [139] or by selectively etching a buried layer. In this
              | experiment, the donor wafer was a SOI-like structure with 4 μm of LPCVD SiO2
              | capped with 500 nm of LPCVD polysilicon. The polysilicon layer was patterned into 20
              | µm islands using standard photolithography and dry etched using HBr/Cl2 plasma.
              | Next, the exposed SiO2 was wet etched in 49% HF solution for 2 minutes; creating
              | polysilicon islands on SiO2 pedestals (Fig. 4.13). Finally, by depositing a thin diffusion
              | barrier of 50 nm SiNx (PECVD) the donor wafer was complete.
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              | 
              | 
              | 
text          | Figure 4.13: Schematic (not to scale) showing: a) one-sided Al-Ge eutectic bonding of
              |  20 µm polysilicon islands; b) razor blade spitting of bonded wafers via SiO2 pedestal
              |      fracture. Note: Si3N4 diffusion barrier on polysilicon islands is marked in red.
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              | 
text          |        The acceptor wafer had 80 nm of thermally grown SiO2 that was covered with
              | Al-Ge bilayer stack (100 nm Al and 57 nm Ge). The wafers were bonded at 435 °C for
              | 30 minutes, while 2.2 kN down-force (200 kPa) was applied over the 4-inch diameter
              | wafer pair. To complete the transfer process, donor wafer bulk was cleaved away by
              | inserting a razor blade between the wafers. The fracture occurred in the SiO2 pedestals,
              | rather than the apparently stronger Al-Ge layer. Special care needed to be taken to
              | ensure that liquid Al-Ge around the islands did not bond directly to the donor wafer
              | bulk. This included patterning AlGe bilayer into pads prior to bonding to limit the
              | amount of excess material, or ensuring the pedestals were sufficiently tall (>3 µm).
              | Finally, the remnants of the pedestals were wet etched in 6:1 buffered oxide etch
              | (BOE), while the excess Al-Ge around the islands was etched in phosphoric, acetic,
              | nitric acid (PAN) at 40 °C. The resulting array of transferred silicon islands on the SiO2
              | acceptor wafer is shown in Figure 4.14.
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              | 
              | 
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text          |  Figure 4.14: SEM of an array of polysilicon islands attached to a SiO2 substrate using
              |  Al-Ge eutectic bonding at 435 °C. The excess Al-Ge in between the islands has been
              |              etched away in phosphoric, acetic, nitric acid solution (PAN).
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              | 
text          |        Attachment of islands was quite successful, with the transfer yield estimated to
              | be greater than 90%. The acceptor wafer had a few defective islands at the edge related
              | to the razor splitting method. However, these problems could be eliminated with the use
              | of more sophisticated separation methods, such as hydrogen induced splitting (see next
              | section). Cross-sectional analysis of the Al-Ge interface confirmed seamless bonding
              | between the islands and the acceptor wafer (Fig. 4.15). The area examined by the FEI
              | Strata 235DB dual-beam FIB/SEM indicated that no microcavity defects or other voids
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              | 
              | 
              | 
text          |      Figure 4.15: Cross-sectional SEM of the Al-Ge bonding interface between the
              |    polysilicon island and the oxidized Si substrate, showing seamless and void-free
              |          attachment. A full 20 µm cross section examined contained no voids.
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              | 
              | 
              | 
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text          | were present. Moreover, the thin (157 nm) one-sided Al-Ge eutectic bond had
              | segregated into Al and Ge columnar phases, spanning the full thickness of the film. This
              | morphology is similar to the thicker Al-Ge bond structure revealed by X-TEM analysis
              | in the previous section.
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              | 
text          |        However, the most remarkable property of eutectic Al-Ge bonding is the ability
              | to form strong and void-free bond with very rough surfaces. Unlike direct (fusion)
              | bonding, which requires optically smooth wafers to allow short range attractive van der
              | Waals forces to hold the wafer pair together, Al-Ge liquid wets the bonding surfaces
              | and flows around any asperities, significantly relaxing the surface smoothness
              | requirement. This is especially true when the mating wafers are placed under
              | compressive applied pressure. Consequently, upon solidification, a solid and void-free
              | connection is made, as can be seen in Figure 4.16. Incidentally, the liquid nature of the
              | eutectic bond also ensures a hermetic seal, an advantage that has been exploited for
              | MEMS packaging applications [127].
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              | 
              | 
              | 
text          |  Figure 4.16: Rough (4.3 nm RMS over 5x5 µm area) polysilicon island (with 100 nm
              |  LPCVD SiO2 diffusion barrier) is successfully bonded onto oxidized Si substrate via
              |                        Al-Ge eutectic bonding (435 °C, 200 kPa).
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              | 
title         | 4.7 SmartCut® release method
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text          |        A more elegant approach to remove the bulk donor wafer is by hydrogen ion
              | splitting, or SmartCut® [82]. Laborsome backside grinding and etching is avoided by
              | implanting a large dose of H+ ions (6 x 1016 cm-2) into the donor wafer prior to bonding.
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              | 
              | 
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text          | These hydrogen species agglomerate via Ostwald ripening and start forming micro-
              | cracks upon moderate heating [140]. At a critical point the internal pressure of formed
              | H2   (g)   causes a large-scale crack, which propagates along major crystal plane (100),
              | effectively exfoliating a thin device layer. The range of the H+ implant determines the
              | thickness of the layer, since the peak of the hydrogen distribution occurs there. In the
              | case of Si (100), an off axis 7° tilt hydrogen implant at 75 keV energy would yield a
              | 640 nm thick layer, as calculated by the SRIM simulation [141].
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              | 
              | 
              | 
text          | Figure 4.17: Bright field X-TEM images of GeOI preparation: a) H+ implant damage in
              |  bulk Ge; b) hydrogen blisters appear upon annealing; c) fusion bonded and exfoliated
              |                                           Ge film [83].
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              | 
text          |            The use of hydrogen splitting is quite flexible, since it can be utilized to transfer
              | full wafer films as well as islands. In addition, theoretically any crystalline material
              | could undergo hydrogen induced cracking along weak crystalline planes, i.e. ones with
              | lower aerial bond density, as long as sufficient H+ dose is implanted. For example, Ge
              | thin layers have been fusion bonded and exfoliated to make GeOI wafers from bulk Ge
              | [142]. Finally, room temperature cleaving of hydrogen-implanted wafers by razor
              | insertion has been demonstrated [143] with minimal anneals reaching only 250 °C.
              | Thus, SmartCut® offers a versatile and low-temperature method of transferring thin
              | crystal films, ideal for 3DIC applications.
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              | 
              | 
              | 
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title         | 4.8 Semiconductor islands using SmartCut® donor wafer release
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text          |        A complete process of attaching silicon crystal islands on SiO2 acceptor wafer
              | via Al-Ge eutectic bonding and hydrogen splitting has been carried out and is presented
              | in Figure 4.18. Additionally, Ge crystal islands have also been transferred from
              | epitaxially grown Ge on silicon substrate (see Appendix B).
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              | 
              | 
              | 
text          | Figure 4.18: Al-Ge bonding of Si islands for monolithic 3DICs: a) thermally oxidized Si
              |   (100) donor wafer is implanted with H+ ions (6x1016 cm-2, 75 keV, Rp= 630 nm) for
              |  eventual SmartCut®; b) donor islands are patterned; c) 157 nm thick Al-Ge bilayer is
              |  evaporated onto an oxidized Si acceptor wafer and patterned into pads; d) donor and
              |  acceptor wafers to be bonded are placed face-to-face; e) Al-Ge eutectic bonding takes
              | place at 435 °C and 200 kPa pressure for 30 minutes; f) donor wafer is split away using
              |  SmartCut® process; g) the splitting process leaves surface roughness that is removed
              |   with CMP (h); i) resulting in single crystalline Si (100) islands on top of amorphous
              |                                   SiO2 acceptor wafer.
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              | 
              | 
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text          | The Al-Ge bilayer on the acceptor wafer was patterned into pads prior to bonding. This
              | step was necessary in order to prevent agglomeration of excess Al-Ge eutectic liquid
              | between the islands, which in turn could cause unwanted bonding to the donor bulk,
              | disrupting the SmartCut® release process.
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              | 
              | 
              | 
text          |  Figure 4.19: a) SEM of Si islands on the donor wafer implanted with H+ and ready to
              | bond; b) IR camera image of the Al-Ge bonded 4-inch wafers (with Si islands visible).
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              | 
text          |        The donor wafer was patterned and dry etched to create arrays of islands (3μm
              | to 2000μm in size) ready for bonding (Fig. 4.19a). The etch depth was larger than the
              | H+ implant depth (640nm) in order to successfully release the islands during SmartCut.
              | Infra red image of the bonded 4-inch wafer pair (Fig. 4.19b) shows the regular array of
              | islands (contrast is made by Al-Ge bonding layer which absorbs in the IR spectrum).
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              | 
text          |        The donor wafer was removed by annealing the Al-Ge bonded pair at 400 °C for
              | 12 hours. The molecular hydrogen pockets thus coalesced and the internal pressure split
              | the wafers. However, it is critical to set the H+ implant dose low enough, such that
              | SmartCut splitting does not occur prematurely during the Al-Ge bonding step at 435 °C.
              | The reason is that hydrogen splitting requires rigid surfaces for cooperative thin film
              | exfoliation [144,145]. If the splitting occurs while Al-Ge eutectic melt is present,
              | irregular and localized transfer occurs, since the liquid Al-Ge bond does not anchor the
              | islands well to withstand the mechanical forces involved. A possible alternative is to use
              | razor cleaving instead of thermal treatment to induce splitting [83].
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              | 
              | 
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text          |     Figure 4.20: a) SEM image of 10 µm Si crystal island bonded to SiO2 via Al-Ge
              | eutectic bonding at 435 °C; b) optical image of 50 µm Ge (100) island on SiO2 with Al-
              |   Ge bond pad visible (bright area). CMP step is needed to remove surface roughness.
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              | 
text          |        The resulting Si and Ge crystal islands bonded to SiO2 via Al-Ge eutectic
              | bonding are presented in Figure 4.20. Most of the transferred islands are intact, with
              | only island edge defects due to the smaller size of the Al-Ge bonding pad. The final step
              | before making the islands ready for device fabrication is a CMP polish to remove the
              | remaining surface roughness and damage from the hydrogen splitting process (see
              | Appendix A). Depending on the application, the polish step can also be used to adjust
              | the ultimate thickness of the crystalline island.
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              | 
title         | 4.9 Sub-eutectic Al-Ge bonding
blank         | 
text          |        In the interest of having a fully low-temperature 3DIC process with all
              | constituent steps at 400 °C or below, the feasibility of sub-eutectic AlGe bonding at 400
              | °C has been investigated. Because the bonding takes place below eutectic temperature
              | (424 °C), no melt occurs within the Al-Ge bilayer such that atomic diffusion takes place
              | in solid phase. In this regard, the mechanism of sub-eutectic Al-Ge bonding should be
              | similar to the solid phase thermo-compressive techniques such as Cu-Cu bonding.
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              | 
text          |        Surprisingly, initial 4-inch oxidized Si wafers bonded via sub-eutectic Al-Ge
              | bonding held well, and passed the razor test, testifying to its structural strength.
              | Moreover, AES analysis of cleaved pieces revealed that the interfacial crack propagated
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              | 
              | 
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text          | through the SiO2 layer, and not the bond itself. The mating Si wafers had 800nm
              | thermally grown SiO2 covered with 475 nm Al-Ge bilayer (condition A). Bonding took
              | place at 400 °C for 2 hours, and 350 kPa pressure in EV501 bonder at 10-4 Torr
              | pressure. Samples were dipped in 2% HF solution for 30 seconds to remove any native
              | germanium oxides that could provide a chemical barrier to bonding. The resulting SEM
              | cross section of a successful bond is presented in Figure 4.21.
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              | 
              | 
              | 
text          |  Figure 4.21: Sub-eutectic Al-Ge bond at 400 °C. The mating wafers had 475 nm thick
              |       Al-Ge bilayer each, and were bonded for 2 hours at 350 kPa down-pressure.
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              | 
text          |        As expected, the cross-sectional image shows the presence of the original
              | bonding interface, with a sprinkling of sub-micron voids between the surfaces.
              | However, the initial bilayer structure has completely disappeared, having been replaced
              | by distinct columnar grains. Remarkably, even without liquid eutectic condition, solid
              | phase diffusion of Al and Ge atoms has laterally segregated the alloy into its separate
              | phases. The bright regions in the SEM have been confirmed to have high Ge content,
              | while the dark ones consist of majority Al material. Such profound reorganization could
              | explain the surprising strength of the sub-eutectic Al-Ge bond, since highly mobile
              | surface atoms could also cross onto the mating wafer forming a solid physical bond.
              | Therefore, the contact area between the mating surfaces ultimately limits the strength
              | and quality of sub-eutectic (solid phase) Al-Ge attachment.
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              | 
              | 
              | 
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text          | Figure 4.22: Silicon (100) island attached to SiO2 wafer via sub-eutectic Al-Ge bond at
              |           400 °C. Donor wafer has been successfully removed via SmartCut®.
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              | 
text          |        Finally, sub-eutectic Al-Ge bonding appears suitable for attachment of crystal Si
              | islands for 3DIC. Figure 4.22 depicts a large Si (100) island bonded to an Al-Ge pad.
              | Even though the bond temperature of 400 °C ensured no melt, the attachment was
              | strong enough to withstand hydrogen ion splitting of the donor wafer. In addition, due
              | to the lower temperature, there was significantly less agglomeration of Al-Ge alloy
              | within the bonding pads. Therefore, sub-eutectic Al-Ge bonding forms a viable method
              | for 3DIC integration, even without harnessing the benefits of a liquid phase eutectic.
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              | 
title         | 4.10 Conclusions
blank         | 
text          |        Aluminum-germanium eutectic bonding has been successfully demonstrated at
              | 435 °C using a bilayer film as thin as 157 nm, making it a viable method for 3DIC
              | integration. The liquid phase of the eutectic material offers versatility, ensuring
              | excellent uniformity and defect-free interface, even when bonding rough surfaces.
              | Dendritic microstructure of the formed Al-Ge eutectic bond produces formidable
              | strength (50 J/m2), creating a solid bond that gives high transfer yields when combined
              | with SmartCut® release process. Moreover, sub-eutectic Al-Ge bonds formed at 400 °C
              | proved nearly as successful in attaching semiconductor islands onto amorphous
              | substrates. Finally, the conductive nature of Al-Ge layer, as well as its compatibility
              | with standard CMOS processing techniques, makes Al-Ge eutectic bonding particularly
              | suitable for monolithic 3DICs.
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              | 
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title         | Chapter 5 – Copper bonding
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              | 
title         | 5.1 Introduction
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text          |        As the IC interconnect dimensions keep shrinking, the use of copper metal is
              | regaining popularity. Compared to aluminum, copper is electro-migration resistant, has
              | higher electrical conductivity as well as higher thermal conductivity, promising better
              | electrical performance, reduced Joule heating and efficient heat transfer [146,147].
              | These advantageous properties of copper make it equally attractive for vertical
              | interconnects of 3DICs. Using copper-copper bonds to attach different layers of a 3DIC
              | would not only provide a strong mechanical attachment, but also serve as a conductive
              | path as well as a built-in heat channel. Consequently, Cu-Cu bonding is positioned as
              | one of the best candidates for achieving 3DIC integration.
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              | 
text          |        Two main integration approaches that use copper-based bonding are die-to-
              | wafer integration [23-27,148] and full wafer stacking for 3DICs [28-33]. Both of them
              | rely on solid-phase surface diffusion of copper atoms to form the bond, under thermo-
              | compressive conditions. In addition, Ziptronix Inc. has recently developed an aligned
              | dual-bonding approach that combines the positive aspects of Cu bonding with low-
              | temperature fusion bonding process [25]. In this hybrid method, the structural
              | attachment is arguably achieved by SiO2-SiO2 bond, while the adjacent Cu-Cu bonds
              | mainly serve for electrical contact. Regardless of the detailed mechanism, with
              | successful bonds reported at temperatures as low as 300 °C [149], the pure Cu-Cu
              | bonding approach is certainly compatible with back-end-of-line (BEOL) processing
              | conditions, and therefore suitable for both wafer stacking and monolithic 3DIC
              | techniques.
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              | 
              | 
              | 
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title         | 5.2 Mechanism
blank         | 
text          |        The fundamental mechanism of thermo-compressive metal bonding is that of
              | interfacial atomic diffusion [150-152]. The metal atoms, in this case copper, move
              | along the solid metal surface and upon contact with the metal layer of the mating wafer,
              | form a bond. Collective movement of surface copper atoms allows for microscopic
              | plastic deformation, smoothing the surface asperities, and so creating a larger area of
              | contact between the bonding wafers. It is important to note that the Cu bonding process
              | takes place in solid phase, far away from the Cu melting temperature of TM = 1084 °C.
              | The thermal bias increases the metal atom diffusivity (and mobility), while the
              | compressive pressure mechanically forces the wafers into intimate contact. Such
              | thermo-compressive conditions aid in increasing the effective area of contact for
              | bonding to occur. Finally, after sufficient bonding time at elevated temperature and
              | pressure, the atomic reorganization at the interface allows the copper layers to fuse,
              | forming a strong structural bond as well as a conductive and thermal channel.
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              | 
text          |        Since successful bonding is dependent of atomic diffusion across the Cu-Cu
              | interface, the condition of the surface is paramount. Any dust or other particle
              | contamination can severely limit the contact area, and thus cause unwanted interfacial
              | voids. In addition, any real metal surfaces are never perfectly flat but microscopically
              | rough, hence the true contact area between wafers can be much smaller than the
              | nominal area [153]. Finally, native oxide formation on the metal surface could further
              | hinder the bonding process by presenting a barrier to atomic interface diffusion.
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              | 
text          |        Therefore, to accomplish a copper-copper thermo-compressive bond, one would
              | ideally need a particle free, low roughness and oxide free copper surface. Otherwise,
              | any impediment to surface atomic diffusion would require higher temperature, higher
              | pressure or longer bond time to compensate.
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              | 
              | 
              | 
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title         | 5.3 Surface preparation and characterization
blank         | 
text          |        The surface roughness of as-deposited 300 nm thick copper films was around
              | 1.6 nm RMS, which is higher than reported in literature (1.1 nm RMS) [154]. Copper
              | films were put down on top of blank 4” Si (100) wafers using Innotec ES26C E-beam
              | evaporator, with a 30 nm thin tantalum (Ta) diffusion barrier underneath. The rate of
              | evaporation has no appreciable effect on surface roughness, as exemplified by AFM
              | scans in Figure 5.1.
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              | 
              | 
              | 
text          | Figure 5.1: 5x5 µm AFM scan of 300 nm thick Cu film evaporated at: a) 0.3 nm/s rate,
              |     b) 0.9 nm/s rate. Root-mean-square (RMS) surface roughness is not affected by
              |                                     deposition rate.
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              | 
text          |        Even though smoother films could be deposited using ion-sputtering techniques
              | (down to 0.7 nm RMS), these were deemed sufficiently smooth for Cu-Cu bonding.
              | Application of contact theory to metal-metal bonding of silicon wafers [155], did
              | indicate that the true contact area decreases with increasing surface roughness, limiting
              | yield. However, it also found that 2.0 nm RMS rough Cu films could successfully bond
              | at even 300 °C and 130 kPa pressure. Further experiments by Chen et al. [156]
              | confirmed that surface roughness is not an issue with Cu-Cu bonding above 350 °C.
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              | 
text          |        Finally, to remove copper native oxides from the surface prior to bonding, the
              | wafers were dipped in 3:1 (by volume) H2O:HCl for 30 seconds followed by a DI rinse.
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              | 
              | 
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text          | Subsequently, wafers should be immediately loaded into the bonding chamber and
              | pumped to vacuum (~10-3 torr) to prevent any re-oxidation. The chemical reactions are
              | believed to be as follows [149]:
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              | 
text          | Cu2O (s) + 8 Cl- + 2 H+ (aq) → 2 CuCl42- (aq) + H2O (l) + 2e-
              | CuO (s) + 4 Cl- + 2 H+ (aq) → CuCl42- (aq) + H2O (l)
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              | 
text          |        The effect of dilute hydrochloric acid dip on surface roughness is shown in
              | Figure 5.2. Increased copper film roughness is due to the fact that dilute HCl also etches
              | Cu. There may be alternative treatments such as glacial acetic acid solution at 35 °C
              | [157] that not only removes native oxide, but also significantly decrease reoxidation
              | rate. Finally, in-situ forming gas anneal (95% N2, 5% H2 by vol.) at 150 °C for 15
              | minutes [158] could reduce the copper oxides in the bonding chamber via the following
              | exothermic reactions:
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              | 
text          | CuO (s) + H2 (g) → Cu (s) + H2O (g) (ΔH = -87.1 kJ/mol at 650 K)
              | Cu2O (s) + H2 (g) → 2 Cu (s) + H2O (g) (ΔH = -91.0 kJ/mol at 673 K)
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              | 
text          |        For the copper bonding experiments for monolithic 3DIC applications described
              | below, only a 30 sec 1:1 HCl:H2O dip was used, with the rationale that the increased
              | surface roughness was not a limiting factor in Cu-Cu bonding at 400 °C.
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              | 
              | 
              | 
text          |  Figure 5.2: Copper metal surface roughening by dilute HCl solution: a) as deposited;
              |                 b) 30 sec, and c) 60 sec. AFM scans are of 5x5 µm area.
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              | 
              | 
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title         | 5.4 Cu-Cu bonding procedure
blank         | 
text          |         For the purposes of achieving monolithic 3DIC by attachment of Si or Ge
              | crystal islands, we adapted the process developed for full wafer stacking. Therefore, all
              | of the Cu-Cu bonding experiments described below involve full wafer bonding of either
              | 4” Si (100), or a 4” epitaxially grown Ge (100) wafer. The general procedure is
              | illustrated in Figure 5.3.
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              | 
              | 
              | 
text          |  Figure 5.3: Diagram of Cu-Cu bonding of Si for monolithic 3DICs: a) Si (100) donor
              | wafer is implanted with H+ ions for eventual SmartCut; b) 300 nm thick Cu layer (with
              |   30 nm Ta diffusion barrier) is evaporated on both donor and an oxidized Si acceptor
              |   wafers; c) donor and acceptor wafers to be bonded are placed face-to-face; d) Cu-Cu
              |  bonding takes place at 400 °C and 400 kPa pressure for 30 minutes; e) donor wafer is
              |  split away using SmartCut process; f) resulting single crystalline Si (100) layer on top
              |                              of amorphous SiO2 acceptor wafer.
blank         | 
              | 
text          |         The 4” Si (100) donor wafer was first blanket implanted with H+ ions (7 x 1016
              | cm-2, 90 keV) with a range of approx. 600 nm, which will determine the thickness of the
              | Si layer transferred during the SmartCut process. Acceptor wafer is an oxidized 4” Si
              | wafer. Both bonding wafers were cleaned in Piranha solution (H2O2:H2SO4 = 1:4) for
              | 20 minutes, rinsed in DI water and dried prior to e-beam evaporation of 30 nm tantalum
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              | 
              | 
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text          | (Ta) diffusion barrier followed by 300 nm of copper (Cu). Right before the bonding
              | step, the wafers were dipped in H2O:HCl (1:1) for 30 seconds, rinsed, dried and
              | immediately loaded into the EV501 bonder. Wafers were bonded at 400 °C for 60
              | minutes, with 3.3 kN of downward force over 4” diameter area (420 kPa) and base
              | pressure of ~1 x 10-4 Torr. Subsequently, hydrogen ion splitting (SmartCut®) removed
              | the donor wafer after a 2 hour anneal at 425 °C in N2    (g)   for the H+ dose implanted.
              | Copper-copper bonding was also used to bond epitaxially grown Ge (100) wafers, with
              | minor modifications in the cleaning steps.
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              | 
title         | 5.5 Copper bond strength tests
blank         | 
text          |        In the preliminary experiment, full 4” Si (100) wafers were bonded using Cu-Cu
              | bonding for 30 minutes at 350 °C, 400 °C and 450°C and a further 30-minute N2           (g)
blank         | 
text          | anneal at the respective bonding temperature. All of copper bonded pairs were
              | structurally strong enough to pass the razor test (i.e. did not split along bonding
              | interface). Therefore, wafer saw dicing test [149] in which bonded wafers were cut into
              | 5x5 mm square dies was performed. By monitoring the failure (debonding) percentage
              | of the bonded pieces due to dicing stress, the bond strength was qualitatively estimated
              | (Figure 5.4).
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              | 
              | 
              | 
text          |   Figure 5.4: Dicing test results for Cu-Cu bonded 4” Si wafers at 350 °C (Sample 2).
              |        Two brown squares are two 5x5 mm square dies debonded during sawing.
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              | 
              | 
              | 
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text          |        The results of the wafer saw dicing test of Cu-Cu bonded wafers are
              | summarized in Table 5.1. Overall, the vast majority of the dies in all three samples
              | survived the dicing process, giving qualitative evidence of a structurally strong bond.
              | More accurate, quantitative measurements using four-point bend tests reported the
              | copper bond toughness to be 2.5 J/m2 in pure tension loading and 17 J/m2 under mixed-
              | mode loading conditions [134,159]. Therefore, it would be safe to conclude that Cu-Cu
              | bonding at 400 °C forms a sufficiently strong bond for 3DIC applications, including the
              | stresses of wafer splitting process (SmartCut®).
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              | 
              | 
              | 
text          |     Table 5.1: Wafer saw dicing test results for Cu-Cu bonded Si wafers at various
              |     conditions. K&S 775 wafer dicing saw was used to cut 5 mm x 5mm dies with a
              |               resinoid blade spinning at 20k rpm and feed rate of 1 mm/s.
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              | 
title         | 5.6 Copper bonding for monolithic 3DIC applications
blank         | 
text          |        Transfer of crystalline Si material for upper layers of 3D integrated devices via
              | copper bonding was successful. The microstructure morphology of the copper bonded
              | film was investigated by imaging the cross-section of the resulting film stack. Sample
              | sectioning was performed using a focused ion beam (FEI Strata 235DB dual-beam
              | FIB/SEM). Thus, the final vertical structure of the acceptor wafer is clearly visible in
              | Figure 5.5.
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              | 
              | 
              | 
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text          | Figure 5.5: Cross-sectional SEM of the acceptor wafer illustrating successful transfer of
              |    ~600 nm thick Si crystalline film on top of amorphous substrate (SiO2) via Cu-Cu
              |   bonding at 400°C. Note: the top of the Si transferred layer exhibits Ga+ ion damage
              |         incurred during sample preparation (FIB), and not the SmartCut process.
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              | 
text          |        The copper films on the mating wafers appeared to have fused together to form a
              | homogenous copper bond. The bonding layer, as the SEM reveals, is a mosaic of copper
              | grains with differing crystal orientations (and therefore differing contrast due to
              | orientation dependent emission of secondary electrons). Individual grains grew larger
              | during the 400 °C bonding process and subsequent anneal, making the original bonding
              | interface hard to distinguish. Ar+ ion polished cross section of copper bonded
              | germanium (100) crystal film gives a clearer picture of the copper grain growth across
              | the original divide (Figure 5.6).
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              | 
text          |        Self-diffusivity of Cu at 400 °C is 8.5 x 10-17 cm2/s [160], enabling significant
              | movement of atoms across the interface to ultimately form a seamless thermo-
              | compressive bond. K. N. Chen et al. [149] have also reported such evidently large grain
              | extrusions under the same bonding conditions. In addition, there are very few voids
              | present (~1 per 25 µm2), usually located in the middle of the copper bond and not larger
              | than 200nm.
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              | 
              | 
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text          | Figure 5.6: Cross-sectional SEM of germanium crystalline film bonded onto SiO2 wafer
              |  via 400 °C Cu-Cu bond. Copper grains are clearly visible, while the two bright stripes
              |    lining the copper bond are 40 nm thick tantalum (Ta) diffusion barriers. Note: this
              | sample was prepared using JEOL SM Ion polisher (Ar+), and the Ge surface roughness
              |                            is due to SmartCut splitting process.
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              | 
text          |        Finally, tantalum (Ta) thin films 40 nm thick were utilized as copper diffusion
              | barriers in order to prevent deleterious effects of Cu impurities in crystalline silicon and
              | germanium. The very slow diffusion rate of Cu atoms in Ta of 2 x 10-15 cm2/s at 400 °C
              | [161] ensure effective isolation up to 550 °C process temperatures [162]. For
              | comparison purposes, the diffusivity of Cu in Si at 400 °C is much larger, 7 x 10-6 cm2/s
              | [163]. If any reasonable device characteristics are to be expected from upper layer
              | crystalline devices of a 3DIC, special care needs to be taken to prevent possible trap
              | states caused by out diffusing copper atoms.
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              | 
              | 
              | 
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text          | Figure 5.7: Cross-sectional SEM illustrating the morphology of the Cu-Cu bond (at 400
              | °C) used to attach Ge (100) crystalline film. There are very few interfacial voids and the
              |        large copper grains have completely erased the original bonding interface.
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              | 
text          |        The procedure outlined earlier called for a full 4-inch diameter silicon film to be
              | attached onto an oxidized acceptor Si wafer. Figure 5.8 includes photographs of donor
              | and acceptor wafers post-transfer, illustrating that while most of the Si (100) crystalline
              | film has been transferred onto the SiO2 acceptor wafer (pink coloured area in Fig. 5.8b),
              | there exist a few non-bonded areas (copper in colour).
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              | 
              | 
              | 
text          |    Figure 5.8: Copper bonded post-transfer images of: a) 4-inch Si donor wafer after
              |   splitting; b) 4-inch oxidized Si acceptor wafer with bonded crystalline Si (100) film
              |    (appears pink). Note that the non-bonded areas still have reddish Cu film visible.
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              | 
text          |        Given that both wafers are quite smooth (Si prime with Cu film of 1.6 nm RMS
              | roughness), the non-bonded areas are probably caused by uneven pressure applied
              | across the wafer through the top bonding plate (and graphite liner). The non-bonded
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              | 
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text          | areas roughly match the distribution of the low-pressure areas, which have been
              | previously mapped using pressure sensitive paper (see Chapter 4). Consequently, these
              | findings highlight the crucial importance of applied pressure to ensure full contact
              | between the mating wafers, and thus a successful thermo-compressive bond. Because
              | the Cu-Cu bonding mechanism relies on solid-phase diffusion of Cu atoms it is far more
              | susceptible to low applied pressure or surface roughness limitations than liquid-phase
              | based techniques, such as AlGe eutectic bonding. Figure 5.9 illustrates an extreme
              | example where a rough surface epi-Ge (100) wafer (RMS = 3.2 nm) combined with
              | uneven applied pressure by the bonder result in dramatic loss of close contact between
              | the wafers, ultimately limiting the transfer of Ge crystal film.
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              | 
              | 
              | 
text          |  Figure 5.9: Cu-Cu thermo-compressive bonding of rough epi-Ge (3.2 nm RMS) to an
              |  oxidized Si prime wafer at 400 °C: a) Scanning acoustic microscope (SAM) image of
              |  the bonded pair showing interfacial voids in white and bonded areas in black; b) raw
              |  image of the pressure sensitive paper indicating uneven pressure distribution applied
              |  over the 4-inch wafer; c) resulting acceptor wafer after SmartCut splitting, exhibiting
              |                 incomplete transfer of Ge crystal film (light grey colour).
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              | 
text          |        It is important to mention that bonding an array of islands, rather than a full
              | wafer is expected to be much easier in the case of Cu-Cu and other thermo-compressive
              | techniques. The reduced footprint area would substantially increase the effective
              | bonding pressure, resulting in closer contact between copper layers and therefore a
              | better bond.
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              | 
              | 
              | 
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title         | 5.7 Conclusions and future of copper based bonding
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text          |        Thermo-compressive Cu-Cu bonding is an attractive method for attachment of
              | crystalline Si and Ge islands for upper layers of a 3DIC. With uniform pressure
              | application, and reasonably smooth surfaces (< 2 nm RMS), successful transfer of Si
              | and Ge islands is achievable at 400°C or below. The resulting bonds tend to be
              | homogenous, void-free and mechanically strong, and in addition also serve as effective
              | electrical and heat channels.
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              | 
text          |        However, copper is not considered a CMOS friendly material due to deep level
              | trap formation in Si and Ge crystal lattices, and therefore must be isolated by diffusion
              | barriers similar to those in back-end copper metal interconnects. At the same time, one
              | must concede that the crystal islands for active layers of a 3DIC would be bonded
              | directly on top of such back-end metalization layers, which are frequently made of
              | copper. Consequently, the dangers of contamination from Cu-Cu bonds are no greater
              | than that of copper interconnects isolated by a thin tantalum barrier.
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              | 
text          |        As discussed in Chapter 1, the very presence of copper in back-end metal layers
              | provides a convenient base for Cu-Cu bonding of aligned vertical interconnects.
              | Accordingly, most of the effort in optimizing copper bonding techniques has been
              | focused on wafer stacking (or chip-to-wafer) applications, including optimization of
              | through silicon vias (TSV) that would vertically connect device layers through Si bulk.
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              | 
              | 
              | 
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title         | Chapter 6 – Titanium Bonding
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title         | 6.1 Introduction
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text          |        A more recently developed attachment technique is that of titanium-based wafer
              | bonding [164]. It is similar to the copper-copper bonding approach in that it uses a
              | metallic intermediate, in this case titanium (Ti), to attach either full or patterned wafers
              | together. Similarly, the metal layer, which is used for mechanical attachment also
              | provides direct electrical and thermal interconnections. However, unlike Cu-Cu
              | technique, which requires metal on both mating surfaces, one could also achieve direct
              | Ti-Si and Ti-SiO2 bonding using the titanium-based approach, provided that surfaces
              | are sufficiently smooth. Finally, titanium-based wafer bonding is possible at low
              | temperatures (~400°C) [165], complying with back-end-of-line (BEOL) conditions
              | required for successful monolithic 3DIC fabrication.
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              | 
title         | 6.2    Advantages of titanium-based bonding
blank         | 
text          |        Titanium is a reactive transition metal, which has a strong affinity with Si, O, N
              | and C. This property allows it to form intimate connection with silicon-based materials,
              | exemplified by excellent adhesion properties with SiO2. In addition, titanium is an
              | effective gas scavenger, with the ability to dissolve up to 33 atom % of oxygen in a
              | solid solution at elevated temperatures [165]. Coupled with similar ability to absorb
              | nitrogen, titanium metallic layer could effectively reduce or eliminate interfacial gas
              | bubbles that may have formed or become trapped during the bonding procedure.
              | Finally, titanium has been widely used in Ti/TiN liners for Al metalization, making it
              | well characterized BEOL processing, CMOS-compatible material. Put together, these
              | exceedingly desirable properties make low-temperature titanium-based bonding quite
              | attractive for 3DICs.
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              | 
              | 
              | 
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title         | 6.3     Mechanism
blank         | 
text          |         The mechanism of bonding two surfaces with Ti metal on each is that of
              | interfacial atomic diffusion, just like the case of Cu-Cu bonding. In these thermo-
              | compressive techniques, heat and pressure are applied to aid metal atom migration
              | along and across the interface, thus forming a permanent bond between the two
              | surfaces. The self-diffusivity of Ti at 400 °C is 1.8 x 10-17 cm2/s [164] which is
              | reasonable compared to that of Cu at the same temperature (8.5 x 10-17 cm2/s [160]). A
              | quick estimate of Ti diffusion length during a typical bonding process of 2 hours at 400
              | °C would be (Dt)1/2 = 3.6 nm, which is in agreement with observed grain extrusion
              | across the interface (Fig. 6.1).
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              | 
              | 
              | 
text          |   Figure 6.1: HRTEM image of Ti/Ti bonded wafers, showing titanium grain growth
              |                             across the original interface [164].
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              | 
text          |         As with other techniques requiring interfacial diffusion of atoms, the surface
              | condition is critical to the success of the bond. Any particles, hydrocarbon
              | contaminations, surface oxidation or gas adsorption/entrapment could limit the kinetics
              | of the interfacial diffusion reaction, adversely affecting the strength of the bond. An
              | instructive example is that of Shimatsu et al. [166], where immediately after Ti
              | deposition in an ultrahigh vacuum (UHV) chamber, successful Ti/Ti bonding was
              | performed in situ at room temperature and small bonding pressure (~2 kPa). Therefore,
              | if one substantially limits Ti surface degradation due to oxidation or contamination,
              | strong Ti-Ti bonds could be achieved at much lower temperatures than 400 °C.
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              | 
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text          |         The mechanism of Ti-Si bond formation, on the other hand is substantially
              | different. Solid-state amorphization at the Ti/Si interface plays a key role, where fast
              | diffusing Si atoms mix into Ti metal creating an amorphous titanium silicide at low
              | temperatures. Both the rate of Si diffusion in Ti (3.0 x 10-15 cm2/s at 400°C [160]), and
              | the necessary chemical driving force of negative heat of mixing (-39 kJ/g-atom [167])
              | ensure solid-state amorphization takes place, and the Ti-Si bond forms. Finally, the
              | mechanism of Ti-SiO2 bonding is that of reduction reaction at the interface, and is
              | explained in detail by Yu et al. [164].
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              | 
title         | 6.4     Ti-Ti bonding process
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text          |         To investigate whether Ti bonding is a feasible process for achieving 3DICs via
              | island attachment method, patterned donor wafers were bonded to bulk 4” acceptor
              | wafers using Ti-Ti bonding at 400°C. Similarly to the Cu-Cu process described earlier,
              | the donor wafer was subsequently split using SmartCut® technique, leaving behind an
              | array of crystal semiconductor islands. The schematic of the Ti/Ti bonding process is
              | illustrated in Figure 6.2.
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              | 
              | 
              | 
text          | Figure 6.2: Diagram of Ti/Ti bonding of Si islands and subsequent removal of the bulk
              | donor wafer using SmartCut®, leaving behind an array of Si (100) crystal islands on top
              |                                           of SiO2.
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              | 
              | 
              | 
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text          |        The 4” wafers to be bonded were first cleaned in Piranha solution (H2O2:H2SO4
              | = 1:4) for 20 minutes, rinsed in DI water and dried prior to e-beam evaporation (or Ar
              | sputtering) of 40nm Ti layer on each mating surface. A 1x1 µm AFM scan showing the
              | resulting surface roughness of Ti layer deposited onto Si islands can be seen in Figure
              | 6.3. Right before the bonding step, the wafers were treated in HCl:H2O (1:1) for 30 sec,
              | rinsed, dried and immediately loaded into the EV501 bonder. The purpose of the
              | cleaning steps is to remove organic contaminants and the remaining native oxide in
              | order to improve the surface reaction kinetics. The mating wafer pair was bonded at 400
              | °C for 2 hours, with 3.3 kN of downward force over 4” diameter area (420 kPa) and
              | base pressure of ~1 x 10-4 Torr. However, due to the reduced contact area of patterned
              | islands, the effective applied pressure is closer to 1 MPa. After bonding, the donor
              | wafer was removed by hydrogen ion splitting (SmartCut®), which occurred after an
              | eight hour anneal at 400 °C in N2(g) for the H+ dose implanted (7 x 1016 cm-2, 90 keV).
              | Titanium based bonding was also performed on wafers with epitaxially grown Ge
              | islands.
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              | 
              | 
              | 
text          | Figure 6.3: AFM (1x1 µm) surface roughness scans of 40 nm deposited Ti on Si prime
              | substrate, indicating a smoother film was achieved by evaporation (0.69 nm RMS). The
              |  e-beam evaporation deposition rate was 0.15 nm/s, while that of Ar ion sputtering Ti
              |                              deposition rate was 0.4 nm/s.
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              | 
              | 
              | 
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title         | 6.5    Titanium bonding results
blank         | 
text          |        Titanium-based island bonding technique produced impressive results. In the
              | case of Si islands, there was near perfect transfer yield over the whole 4-inch wafer.
              | Everything, from the smallest 3 µm sized islands to the largest 2000 µm islands
              | attached successfully to the acceptor wafer, as illustrated in Figure 6.4.
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              | 
              | 
              | 
text          |  Figure 6.4: Optical image of Si crystal islands (light areas) attached to SiO2 acceptor
              |                    wafer after Ti/Ti bonding and donor wafer splitting.
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              | 
text          |        There were no optically visible defects or voids present within the islands,
              | indicating low particle or organic contamination at the interface and uniform bonding
              | conditions across the wafer. This is partially due to the donor wafer being a perfectly
              | smooth Si prime wafer (<0.2 nm rms) and the relatively smooth nature of evaporated Ti
              | (0.69 nm rms) as illustrated on Figure 6.3. Together, smooth mating surfaces ensured
              | large effective contact area for thermo-compressive Ti-Ti bond to form by surface atom
              | diffusion. In light of such defect-free bonding, detailed scan of the bonding interface via
              | scanning acoustic microscopy has not been performed, while Ti metallic layer
              | absorption prohibited imaging of the interface using IR illumination.
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              | 
text          |        It should be noted that void-free 8-inch wafer Ti-Ti bonding has been previously
              | reported by Yu et al. [164]. However, the patterned island configuration exhibited here
              | can only improve upon their result, by providing avenues for interfacial out-gassing,
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              | 
              | 
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text          | mitigating particle contamination and increasing the effective applied pressure. Figure
              | 6.5 shows a photograph of the 4-inch acceptor wafer with a full array of Si islands
              | attached (green colour). The brown coloured region is most likely exposed Ti film that
              | has inadvertently been oxidized during the splitting process.
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              | 
              | 
              | 
text          |   Figure 6.5: Photo of 4-inch acceptor wafer with Si islands attached (green) via Ti-Ti
              | bonding. The brown-coloured edges are exposed Ti surface that has been inadvertently
              |                                         oxidized.
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              | 
text          |        While no quantitative measurement of the strength of the Ti-Ti bond has been
              | performed, a simple razor-splitting test on bulk Si wafers indicated high structural
              | integrity, with only small chips breaking off. Given that the fracture propagated through
              | Si wafer bulk, rather than the bonding interface, one could assume that the Ti-Ti bond
              | fracture energy is larger than ~2 J/m2 (value for Si). In any case, the Ti bond was strong
              | enough to hold Si islands attached to the acceptor wafer throughout the splitting
              | process, as shown in Figure 6.6.
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              | 
              | 
              | 
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text          |    Figure 6.6: SEM image of Ti/Ti bonded Si island on the SiO2 acceptor wafer. The
              |   resulting height of the island is 630 nm, while the surface roughness is the result of
              |                              hydrogen ion induced splitting.
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              | 
text          |        In the second set of experiments, Ti-Ti bonding was used to transfer epitaxially
              | grown germanium islands onto amorphous SiO2 substrate, effectively producing
              | Germanium-On-Insulator (GOI) structure. The procedure is the same as before, except
              | that the donor wafer is epitaxially grown Ge (100) crystal (see Appendix B), rather than
              | prime Si wafer. Optical images of Ti-Ti bonded germanium islands indicate incomplete
              | transfer (Fig. 6.7), where an irregular patchwork of Ge crystal layer attached to the SiO2
              | substrate.
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              | 
              | 
              | 
text          |   Figure 6.7: Ti-bonded epi-Ge (100) islands on SiO2 substrates, showing incomplete
              |   transfer. Rounded dark areas are transferred Ge crystals, while the bright area is the
              |  non-bonded Ti layer. The intended square shape of large Ge islands can be discerned.
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              | 
              | 
              | 
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text          |        The cause of incomplete transfer is surface roughness, which significantly limits
              | the area of contact for Ti-Ti bond to form. The titanium layer itself is not the cause,
              | since it is relatively smooth (0.69nm rms) and was successfully used to attach Si islands
              | (<0.2nm rms). However, the epitaxially grown germanium layer from which the donor
              | islands are patterned has significant surface roughness (>2 nm rms), which is inherent to
              | the growth method (Fig. 6.8). As described in Appendix B, lattice mismatched Ge
              | crystal is forced to relax on top of (100) Si using multiple hydrogen annealing steps,
              | which repair most of the crystal defects, but are unable to completely smoothen the
              | germanium surface. Similarly to the Ge-SiO2 fusion bonding approach, a
              | straightforward touch polish CMP step (Appendix A) could flatten the rough Ge layer
              | to prime wafer specifications (<0.2nm rms), allowing for successful Ti-Ti bonding of
              | epitaxial germanium.
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              | 
              | 
              | 
text          |  Figure 6.8: AFM (20x20 µm) scan of epi-Ge layer (1 µm thick), after multiple 800°C
              |   hydrogen anneals. The resulting roughness is 2.03nm root mean square (rms) with Z
              |     range being 12.1 nm. Note: diagonal line visible is a crystal defect (boundary).
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              | 
text          |        Therefore, the one limitation of Ti-Ti bonding is a surface roughness
              | requirement for successful bond to form. Since Ti metal layer is malleable and
              | conforms to a certain degree under pressure and elevated temperature, it can
              | accommodate some roughness, but nowhere near the eutectic Al-Ge bonding method. It
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              | 
              | 
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text          | would be instructive to determine the roughest surface that could be successfully
              | bonded via Ti-Ti technique. However, it would be a strong function of bonding
              | temperature, time, pressure and film thickness, all of which affect surface diffusion of
              | Ti atoms.
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              | 
title         | 6.6    Conclusions
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text          |        Titanium-based bonding offers a viable option for attachment of crystalline Si
              | and Ge islands for fabricating upper active layers of a monolithic 3DIC. Ti-Ti bonds are
              | strong, thin, CMOS compatible, and also offer a conductive path for backside contacts.
              | Experiments using Ti bonding to attach (100) Si islands onto SiO2 substrate
              | demonstrated high yield and uniformity with no void formation, while epi-Ge bond tests
              | indicated that smooth (<1 nm rms) surfaces are required for successful Ge island
              | attachment.
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              | 
              | 
              | 
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title         | Chapter 7 – Fusion Bonding
blank         | 
              | 
title         | 7.1 Introduction
blank         | 
text          |        The adhesion of flat, polished surfaces goes back to 1936, when Lord Rayleigh
              | showed the presence of interaction energy between two glass plates [168].
              | Consequently, bonding of semiconductor wafers to glass was demonstrated, albeit with
              | large applied electric field at 500 °C [169]. This process is generally known as anodic
              | bonding. However, the true form of semiconductor wafer bonding is a process of
              | joining two mirror-polished wafers at room temperature without any special ‘glue’ or
              | external forces. Therefore, this rather elegant method of fusing wafers together has
              | found wide applications from fabrication of silicon-on-insulator (SOI) substrates [77],
              | to production of 3D micro-electromechanical systems (MEMS) [78]. In addition, it has
              | recently been used to produce first germanium-on-insulator (GeOI) substrates [83], as
              | well as early Ge-based monolithic 3DICs discussed in Chapter 1 [86].
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              | 
text          |        In the case of monolithic 3DIC application, fusion bonding offers a viable and
              | clean method to attach crystalline semiconductor islands at low temperature. This ‘glue-
              | free’ approach would provide a new canvas of crystalline material in which upper layer
              | active devices could be fabricated. Given that the acceptor wafer surface would be
              | either patterned or flat dielectric layer (ILD) covering underlying circuits, most of the
              | research effort has been focused on SiO2-SiO2, Si-SiO2 and Ge-SiO2 as bonding
              | techniques for island attachment. The design simplicity, material compatibility, as well
              | as room-temperature processing are great advantages of fusion bonding. However, the
              | stringency of the surface smoothness requirement for successful attachment and the
              | resulting bond strength must be fully investigated to determine how suitable the method
              | is for monolithic 3DIC applications.
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              | 
              | 
              | 
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title         | 7.2    Mechanism of hydrophilic bonding
blank         | 
text          |        When two smooth surfaces are brought close to each other, they can fuse and
              | become quite difficult to separate. Different forces acting at the interface cause the
              | adhesion, while their relative strength is dependent on the separation distance. For short
              | distances between both surfaces (d ~ 1 nm) the dominant forces are hydrogen bonding
              | and van der Waals forces (due to instantaneous atomic dipole moments) [170]. Since
              | these forces act over very short ranges, it is crucial to start with very smooth wafers (of
              | low surface roughness) in order to achieve large-area contact and thus a strong bond.
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              | 
              | 
              | 
text          |   Figure 7.1: Mechanism of hydrophilic fusion bonding: a) interfacial monolayers of
              | water (H2O) bridge the wafers by hydrogen bonding to surface silanol groups (Si–OH);
              |  b) water molecules rearrange, accommodating surface roughness; c) at points of close
              |   contact, direct hydrogen bonding between OH groups occurs; d) the silanol groups
              |  polymerize forming much stronger siloxane bonds (reversible reaction up to 425 °C).
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              | 
text          |        Depending on the surface chemistry, two varieties of fusion bonding are
              | possible: hydrophobic and hydrophilic. Because the goal of monolithic 3DIC is to
              | attach crystalline islands onto amorphous dielectric surfaces such as SiO2, which is
              | hydrophilic, the choice was made to pursue hydrophilic fusion bonding. The details of
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              | 
              | 
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text          | the bonding mechanism between Si surfaces are illustrated in Figure 7.1. Other material
              | pairings, such as Si-SiO2, SiO2-SiO2 and even Ge-SiO2, are variants of this mechanism.
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              | 
text          |        Once hydrophilic bonding at room temperature fuses the wafers, the bond
              | strength is quite weak: around 180 mJ/m2 [79]. Thermal annealing is required to
              | strengthen the bond. Up to 110 °C the surfaces are held together by hydrogen bonding
              | between multiple layers of water molecules (up to 1 nm thick), bridging the gap and
              | accommodating surface roughness. The only reaction occurring is a slow fracture effect
              | where Si–O–Si bonds (either native or thermal SiO2) are broken by adsorbed water
              | molecules to increase the number of –OH groups present.
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              | 
text          | In the second phase up to 150 °C, the silanol groups connected by hydrogen bonding
              | polymerize across the interface to form much stronger covalent siloxane bonds (Si–O–
              | Si). The chemical reaction is reversible up to 425 °C [171], and expressed as:
blank         | 
text          |                                                               Kf       [ Si − O − Si ][ H 2 O]
              |    Si(1)–OH + HO–Si(2) → Si(1)–O–Si(2) + H2O,      K (T ) =        =
              |                                                               Kr            [ Si − OH ] 2
blank         | 
text          | where Si(1) and Si(2) refer to silicon atoms on wafers (1) and (2) respectively. After a
              | sufficiently long anneal time, equilibrium of water concentrations between the interface
              | and the surrounding ambient develops. Consequently, by effectively removing the H2O
              | product of the forward reaction, one can increase the concentration of siloxane bonds.
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              | 
text          |        Since water desorption above 150 °C is irreversible, long anneal completes the
              | outgassing and almost all of the silanol groups are converted to siloxane bonds in the
              | contacted areas. Therefore, for temperatures below 800 °C, the contact area ultimately
              | limits the maximum bond strength achievable (~ 1.2 J/m2). In addition, inert gasses such
              | as nitrogen, N2 (g), can remain trapped in nanocavities formed by the surface roughness,
              | preventing further siloxane bonds between the wafers. Bonding in vacuum would
              | ameliorate such an issue.
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              | 
              | 
              | 
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text          |        Finally, annealing hydrophilic bonded wafers above 800 °C starts viscous oxide
              | flow. Either native or thermal SiO2 can then deform to fill micro cavities, ensuring full
              | contact area between the surfaces, and thus maximum theoretical bond strength (about
              | 2.5 J/m2 [79]).
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              | 
text          |        For completeness, hydrophilic room-temperature bonding could also be
              | achieved via hydrogen bonding of nitrogen (–NH2) groups, thus broadening the material
              | choices to include surfaces such as silicon nitride (Si3N4) [172] and metal nitrides (TiN,
              | TaN). Finally, successful SiO2/sapphire (Al2O3) hydrophilic bonding has also been
              | reported at 150 °C [79].
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              | 
title         | 7.3    Low-temperature hydrophilic bonding
blank         | 
text          |        Normally, fusion-bonded wafers are annealed at high temperatures (up to 1100
              | °C) to reach high bonding energy and void-free interface. However, the mechanism
              | described in the previous section suggests that hydrophilic bonding of SiO2-SiO2, Ge-
              | SiO2 and Si-SiO2 could be achieved at temperatures as low as 150 °C given sufficiently
              | long anneals. Therefore, in the case of monolithic 3DIC applications (< 400°C),
              | hydrophilic fusion bonding of perfectly flat surfaces could theoretically form strong
              | bonds (~ 1.6 J/m2 for Si-SiO2 and ~ 1 J/m2 for SiO2-SiO2) [79]. However, in practice,
              | only the silanol groups in close proximity are converted into siloxane bonds, making
              | surface roughness the critical factor limiting bond strength (by way of limiting effective
              | contact area). Viscous oxide flow at temperatures above 800°C is not an option for
              | 3DIC applications. Hence, to get stronger bonds one can either minimize surface
              | roughness, or increase the density of bonds in the areas that are in contact.
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              | 
title         | 7.3.1 Surface activation for low-temperature fusion bonding
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              | 
text          |        Producing optically flat surfaces for successful fusion bonding may be very
              | costly or impractical to implement. Instead, a reactive bonding surface that would
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              | 
              | 
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text          | produce strong attachment could be used to alleviate the surface smoothness
              | requirements.
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              | 
text          |        Bonding surfaces could be activated by plasma treatment [173] or by wet
              | chemical means. Oxygen (and nitrogen) plasma treatment prior to bonding has been
              | reported to lead to high bonding energy at moderate temperatures [174]. The effect is
              | likely due to surface charging, increased roughness and SiO2 porosity, all of which
              | augment the number of available bonding sites [175]. However, plasma treatment may
              | potentially be unsuitable for activating fully processed wafers due to the antenna effect
              | [176]. In addition, significant particle contamination took place during plasma
              | processing at SNF, causing large interfacial voids to appear. Unable to resolve the
              | particle issue, wet chemical processing was pursued instead.
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              | 
text          | Both native SiO2 and thermal SiO2 can be activated by wet chemical means. The basic
              | reaction is the breaking of surface siloxane bonds by water to form two silanol groups:
blank         | 
text          |                          Si–O–Si + H2O (l) → Si–OH + HO–Si
blank         | 
text          | This reaction is only valid if the siloxane bonds are strained, as in the native oxide,
              | where the 130° Si-O-Si bond angle deviates from the equilibrium value of 144°, making
              | it much more reactive. Fully hydrolysed silica surface has 4.6 OH groups/nm2.
              | Compared to the native oxide, the less-strained thermal-oxide siloxane bonds have only
              | 0.06 OH groups/nm2 (Fig. 7.2), and would require very long times (60h+) in boiling
              | H2O to become fully hydrolysed [79].
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              | 
              | 
              | 
text          |     Figure 7.2: SiO2 surface schematic showing a single silanol (Si–OH) bond. Wet
              | chemical activation could increase the density of silanol bonds by breaking the covalent
              |                           Si–O–Si bonds of the silica matrix.
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              | 
              | 
              | 
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text          |        Consequently, it is crucial to use a solution containing H+ or OH- groups to
              | activate the surface by increasing the density of the silanol groups. Since density of
              | silanol (–OH) groups is directly correlated to the bond strength [177], surface activation
              | should yield stronger bonds compared to control. The contact angle of water could be
              | used to determine the degree of activation, since water molecules readily form hydrogen
              | bonds with surface silanol groups. Thus, a highly activated surface would be wetting (or
              | hydrophilic), producing low contact angles. Figure 7.3 presents water contact angles on
              | Si surfaces subjected to standard semiconductor processing chemical solutions.
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              | 
              | 
              | 
text          |   Figure 7.3: Water contact angle as a function of different silicon surface treatments.
              |   The degree of activation (hydrophilic surface) is greatest when the contact angle is
              |  smallest. Note: RCA-1 treatment is NH4OH:H2O2:H2O (1:1:5) at 80 °C, while RCA-2
              |              treatment is composed of HCl:H2O2:H2O (1:1:6) at 80°C [79].
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              | 
text          |        In the case of highly effective RCA-1 solution having NH4OH, the surface
              | reaction breaks the siloxane bond, leaving behind silanol and amine groups. The
              | electron-rich amine group (–NH2) is a good acceptor for hydrogen bonds, and can also
              | polymerize to form siloxane bonds spanning the interface.
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              | 
              | 
              | 
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text          |        Si–O–Si + NH4OH → Si–NH2 + HO–Si + H2O,              (activating SiO2 surface)
              |        Si–NH2 + HO–Si → Si–O–Si + NH3,            (polymerization across the interface)
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              | 
text          |        Polymerization could be accelerated in high pH environment. Therefore, as
              | ammonia (NH3) is produced at the interface, it would raise the pH and possibly increase
              | the polymerization rate. Moreover, unlike water, ammonia has a lower tendency to
              | break siloxane bonds, making the fusion bond more stable [178]. The final strength of
              | low-temperature SiO2-SiO2 bonds after RCA-1 surface activation and 200 °C anneal has
              | been reported to be 850 mJ/m2 compared to 400 mJ/m2 without activation [80,179].
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              | 
text          |        Activation of germanium surface is achieved by dilute (29%) NH4OH solution.
              | Highly reactive H2O2 component is omitted since it etches germanium by successive
              | chemical oxidation. The high surface energy reported for Ge-SiO2 system (800 mJ/m2)
              | [179] is attributed to hydrophilic surface as a result of NH4OH treatment, even though
              | the exact mechanism is not yet understood.
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              | 
title         | 7.3.2 Achieving surface smoothness required for fusion bonding
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              | 
text          |        To successfully fusion bond two surfaces, they need to be smooth enough to
              | ensure effective contact area is large enough for adhesion to occur. In the case of
              | hydrophilic wafer bonding at room temperature, empirical results have shown that
              | surfaces need to be smoother than 0.5 nm root-mean-square (RMS) over 5x5 µm area
              | [79,180].
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              | 
text          |        Commercially available prime Si wafers receive a final mirror polish that
              | produces very flat surface of only 0.15 nm RMS [181]. Wet thermal oxidation of such
              | wafers (at 950 °C or less) roughens the surface only marginally to about 0.25 nm RMS,
              | regardless of the SiO2 thickness. This is probably due to growth occurring at the buried
              | Si/SiO2 interface. Therefore both prime Si and thermally grown SiO2 should readily
              | bond by fusion bonding at room temperature.
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              | 
              | 
              | 
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text          |        However, since monolithic 3DIC applications presume attachment to top
              | dielectric surface of fully processed CMOS wafers, the roughness of these deposited
              | layers must be investigated. Figure 7.4 collates tapping AFM scans of various deposited
              | SiO2 dielectric layers.
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              | 
              | 
              | 
text          |    Figure 7.4: Tapping-mode AFM scans (5x5 µm) demonstrating surface roughness
              |   (RMS) of various SiO2 films (200nm thick). Note: vertical scale has a range of 5 nm
              |                            except for TEOS sample (30 nm).
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              | 
text          |        Compared to thermal SiO2, all of the materials investigated appear too rough
              | (>0.5 nm RMS) to achieve successful fusion bonding as deposited. For example, TEOS
              | (tetraethyl orthosilicate) 200nm thick film deposited at 681 °C, had an astonishing 12.6
              | nm RMS roughness. Only low-frequency PECVD (plasma enhanced chemical vapour
              | deposition) SiO2 film deposited at 350 °C seemed smooth enough to bond (0.403 nm
              | RMS), and has been shown to do so experimentally [142]. However, as with plasma
              | activation, the PECVD SiO2 film deposited at SNF suffered from micro particle
              | contamination, which induced large interfacial voids upon hydrophilic fusion bonding
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              | 
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text          | to a Si wafer (Fig. 7.5). Rinsing wafers in DI wafer or dipping them in activation bath
              | proved ineffective in removing the particle contamination.
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              | 
              | 
              | 
text          |   Figure 7.5: Infrared (IR) image of hydrophilic fusion bonded 4” wafer pair, after 36
              |   hour anneal at 400 °C. a) Si bonded to thermal SiO2 is almost void-free, while b) Si
              | bonded to PECVD SiO2 shows many particle induced voids (appear as Newton’s rings).
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              | 
text          |        In order to meet fusion bonding roughness requirement, chemical-mechanical
              | polishing (CMP) was utilized to smoothen the surface of deposited SiO2. In under a
              | minute of polishing, colloidal silica based slurry (UltraSol S-10) reduced the surface
              | roughness of deposited oxides below the 0.5 nm RMS requirement. For example, the
              | evolution of RMS surface roughness of low-temperature oxide (300 °C) as a function of
              | polish time is depicted in Figure 7.6. The dramatic effects of polish CMP are evident in
              | the corresponding AFM scans shown in Figure 7.7.
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              | 
              | 
              | 
text          |  Figure 7.6: AFM scans (5x5 µm) depicting surface roughness of as deposited LPCVD
              |   SiO2 (LTO) and the smoothening effect of CMP treatment for 60 and 180 seconds.
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              | 
              | 
              | 
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text          |  Figure 7.7: RMS surface roughness of low temperature oxide (LTO) deposited at 300
              | °C as a function of CMP polish time. Within 1 minute, the roughness is reduced below
              |              the requirement for successful fusion bonding (0.5 nm RMS).
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              | 
text          | Full details of the CMP process are presented in Appendix A. Therefore, by performing
              | touch polish CMP, any deposited dielectric (including final inter-layer dielectric
              | covering fully processed CMOS devices) can be brought within roughness requirements
              | for successful hydrophilic fusion bonding.
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              | 
title         | 7.4    Fusion bonding procedure
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text          |        Hydrophilic fusion bonding has been investigated in following configurations:
              | Si-SiO2, SiO2-SiO2 and Ge-SiO2. Moreover, in addition to full 4-inch wafer bonding,
              | fusion bonding of patterned islands was performed.
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              | 
              | 
              | 
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text          |        The wafers to be bonded were first checked to ensure surfaces were smooth
              | enough to bond (< 0.5 nm RMS). If not, appropriate polishing and post-CMP cleaning
              | steps were taken to remove roughness (see Appendix A). Subsequently, mating surfaces
              | were activated in NH4OH:H2O2:H2O (1:1:5) at 80 °C for 10 minutes, followed by DI
              | water rinse and spin dry. In the case of germanium activation, the activation solution did
              | not contain H2O2 (since it etches Ge). The wafers were manually bonded in a Teflon jig
              | by roughly aligning the flats and pressing them together face-to-face. At this point, infra
              | red (IR) camera was sometimes used to determine if any voids were present at the
              | interface. The bonded pair was subsequently annealed to strengthen the bond at various
              | temperatures and durations (typically 200 °C for 48 hours followed by 400 °C for 12
              | hours). Finally, donor wafers that had H+ implanted (7 x 1016 cm-2, 90 keV) were
              | removed by hydrogen ion splitting (SmartCut®). Section 4.7 offers more details of the
              | hydrogen exfoliation process.
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              | 
title         | 7.5    Fusion bonding results
blank         | 
text          |        All smooth wafer pairs that were fused using chemically activated hydrophilic
              | bonding process described above bonded well. They attached to each other immediately
              | upon pressing them together, and remained intact after various thermal anneals. To
              | determine the quality of the fusion bond, the mating interface was imaged using IR
              | camera while the bond strength was measured by crack opening method [182].
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              | 
text          | During hydrophilic fusion bonding, interfacial voids may form and limit the area of
              | successful attachment. Such voids are caused by either micro-particle contamination or
              | outgassing during thermal annealing. This is of serious concern since a 1 µm-sized
              | particle could produce a void approximately 5 mm in diameter [79]. Careful handling
              | while bonding and a cleanroom environment (class 1000 or better) can minimize the
              | occurrence of micro-particle induced voids. Thus, void-free interfaces can be achieved
              | as exhibited in IR images of wafer pairs immediately after bonding - Figure 7.8 (no
              | anneal).
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              | 
              | 
              | 
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text          | Figure 7.8: IR camera images of interfacial voids present between Si-Si, Si-SiO2 and Si
              |  islands-SiO2 wafer pairs, after various thermal anneals. Si-SiO2 pairs had significantly
              | fewer thermally induced voids than the Si-Si pair, while the island wafers produced no
              |                                        voids at all.
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              | 
text          |        The second cause of voids is thermal annealing. The thermally induced voids are
              | actually caused by accumulation of gas molecules (e.g. H2, H2O or NH3) trapped at the
              | interface. Gas is generated as either desorbed hydrocarbons or as by-products of the
              | interfacial polymerization reaction, which forms the hydrophilic fusion bond (see
              | Section 7.2). In the case of NH4OH-activated Si, SiO2, or Ge surfaces practiced in this
              | chapter, the bulky tetrahedral NH3 gas molecules diffuse out very slowly along the
              | interface, especially at low temperatures. Thus, they can become trapped, limiting the
              | contact area and preventing the formation of more siloxane bonds. Since they cannot
              | diffuse into Si, they cause many voids at Si-Si interface at 225 °C and 450 °C (Fig. 7.8).
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              | 
              | 
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text          | Similar observations by Mitani et al. [183] found that these bubble defects mainly form
              | after annealing below 900 °C. Alternatively, very high temperature anneals (>1000 °C)
              | can eliminate Si-Si voids by speeding up the out-diffusion process (not pictured).
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              | 
text          |        In the case of Si-SiO2 bonding, ammonia (NH3) can diffuse into the silicon
              | dioxide layer, thus suppressing thermal void formation at low-temperatures (Fig. 7.1).
              | This is especially the case for porous PECVD SiO2 [179], where the volumetric fraction
              | of void space, or porosity, could be as high as 41% [184]. Consequently, SiO2-SiO2
              | hydrophilic bonding having two oxide surfaces is even less prone to thermally induced
              | voids, as depicted in Figure 7.9a, where only a couple of voids are visible in the SiO2-
              | SiO2 bonded Si (100) crystal layer.
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              | 
              | 
              | 
text          |    Figure 7.9: Post-SmartCut SiO2 acceptor 4” wafers with: a) transferred crystalline
              |  silicon film (pink colour) ~600 nm thick, after SiO2-SiO2 hydrophilic fusion bonding
              |  and 48 hour anneal at 200°C; b) an array of Si-SiO2 fusion bonded Si (100) islands on
              |   top of thermal SiO2 (blue colour). Post-bonding anneal was at 400 °C for 22 hours.
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              | 
text          |        Bonding of islands seems to be the best scenario of all, since no particle or
              | thermally induced voids can be discerned in the IR images (Fig. 7.8). Corroborating
              | evidence can be seen in the array of Si (100) islands that were successfully transferred
              | onto amorphous SiO2 acceptor wafer via activated Si-SiO2 hydrophilic bonding and 400
              | °C anneal (Fig. 7.9b). Attached Si islands vary in size from 3 µm to 2000 µm, and their
              | thickness is approximately 630 nm (determined by the H+ ion implant range). Closer
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              | 
              | 
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text          | examination by SEM and optical microscope (Fig. 7.10) reveals regularly spaced arrays
              | of intact islands with almost no defects. Only a few of the largest islands (>1000 µm)
              | showed small voids (~20 µm in diameter) upon SmartCut® splitting.
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              | 
              | 
              | 
text          |    Figure 7.10: SEM of 3 µm sized Si (100) islands fusion bonded onto SiO2. Optical
              |  images on the right illustrate successfully attached arrays of square islands with sizes
              |     from 3 µm to 200+ µm. The thickness of Si islands after SmartCut is ~ 630nm.
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              | 
text          |          Such high transfer yields could be attributed to the use of islands in fusion
              | bonding. Because any one island is not larger than 2000 µm, the interfacial gas
              | molecules have less than 1000 µm to diffuse to the channels left between the islands.
              | Comparing to the full 4-inch wafer bonding case, gaseous by-products need to travel up
              | to 50,000 µm (50 mm) along the interface to escape into ambient (a factor of 50
              | longer). Therefore, bonding islands significantly reduces the diffusion length and thus
              | time needed to outgas during low-temperature anneals. Together with the use of
              | ‘porous’ PECVD SiO2 [179,184] (not implemented here), island structures could
              | effectively suppress the occurrence of thermally induced voids upon annealing (Fig.
              | 7.11).
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              | 
              | 
              | 
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text          | Figure 7.11: Optical images of Ge (100) layer fusion bonded to SiO2. By patterning Ge
              |       into 300x300 µm islands (b), the number of thermally induced voids is reduced
              | compared to the full wafer transfer (a). The channel width between the islands is 10 µm.
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              | 
title         | 7.6     CMP polishing of fusion attached islands
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text          |         To make the attached semiconductor islands ready for upper layer device
              | fabrication, a final processing step required is to remove the hydrogen induced splitting
              | damage. The violent process of cooperative thin film exfoliation takes place upon
              | thermal anneal, where the hydrogen microcavities coalesce and crack the crystal
              | structure along the (100) plane leaving a rough surface. In addition to surface roughness
              | (Fig. 7.12a), the splitting process damages the top 30-40 nm of the crystal islands.
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              | 
              | 
              | 
text          |  Figure 7.12: AFM scan (5x5 µm) of Si island surface after hydrogen-induced splitting
              |   (SmartCut®). The rough and damaged surface becomes smooth after 30 sec of CMP.
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              | 
              | 
              | 
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text          | However, a short chemical mechanical polish (CMP) of the semiconductor islands can
              | smoothen the surface to under 0.5 nm RMS while also removing the damaged topmost
              | layer. Figure 7.12b demonstrates a smooth Si (100) crystal island after 30 sec CMP
              | using UltraSol S-10 slurry. The CMP step also removed about 100 nm of the island,
              | leaving behind defect-free Si crystal lattice. The details of the CMP process are in
              | Appendix A.
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              | 
              | 
              | 
text          |   Figure 7.13: a) 4-inch SiO2 wafer with an array of Ge (100) islands attached via Ge-
              |  SiO2 fusion bonding and 400 °C anneal. The donor wafer was removed via SmartCut,
              | while the islands were polished by CMP, leaving behind device-ready Ge (100) islands
              |                                         on SiO2.
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              | 
text          |        The final CMP step was also applied to Ge (100) islands that were fusion
              | bonded to SiO2 wafers. It is evident that the Ge-SiO2 hydrophilic bonds, annealed at 400
              | °C are strong enough to withstand both SmartCut and CMP processes. The high transfer
              | yield and structural integrity of the attached GeOI islands can be observed in Fig. 7.13.
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              | 
title         | 7.7    Strength tests
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text          |        The strength of the hydrophilic fusion bond was tested using crack-opening
              | method [182]. In this technique, a razor blade is inserted between two bonded wafers,
              | causing delamination at the interface (Fig. 7.14a). The crack propagates until a balance
              | is reached between the elastic and bonding energies. Then, by measuring the length of
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              | 
              | 
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text          | the delamination (L), an approximation of the bonding energy (γ) can be calculated
              | through the following expression [185]:
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text          |                                           3Et w3 t b2
              |                                       γ =               ,
              |                                            32 L4
              | where E is the Young’s modulus of silicon wafers, while tw and tb are thicknesses of
              | wafers and the razor blade respectively. The value of silicon Young’s modulus along
              | <110> crystal orientation was used, E110 = 169 GPa [186], because the blade was
              | inserted in <110> direction, parallel to the Si (100) wafer flat.
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              | 
              | 
              | 
text          |    Figure 7.14: a) Crack opening method of bonding-energy measurement consists of
              |   inserting a blade between bonded wafers, and measuring the length (L) of resulting
              | delamination; b) IR image of fusion bonded Si-SiO2 wafers with a razor blade inserted.
              |                 The darker shade area of delamination is clearly visible.
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              | 
text          |        Bond strength is equivalent to the value of bonding energy, since it can be
              | thought of as the amount of work required (in Joules) to separate the bonded wafers, per
              | unit area (m2). Therefore, the measured strength of NH4OH-activated Si-SiO2
              | hydrophilic bond after 36 hour anneal at 400 °C was γSi-SiO2 = 660 ± 160 mJ/m2. This is
              | about a third of the bulk silicon fracture energy of 2.1 J/m2 [187]. The measured value
              | for bonding of Si islands onto SiO2 under same conditions was 1.1 ± 0.2 J/m2, once
              | scaled for the effective contact area. The stronger bonds of islands are most likely due
              | to efficient removal of interface by-products, allowing for larger microscopic contact
              | area. Consequently, during post-processing, bonded islands consistently fared better
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              | 
              | 
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text          | than full-wafer bonded films. Finally, Ge-SiO2 fusion bond was stronger, measuring
              | 1.3 ± 0.3 J/m2, after 24-hour anneal at 200 °C, followed by 12-hour anneal at 400 °C.
              | Comparatively, bulk Ge (100) fracture energy is 1.84 J/m2 [187]. It is important to note
              | that surface energy values obtained have large measurement errors due to the fourth
              | power term of delamination length (L4) and the limited resolution of the IR camera set-
              | up where the length is read. In addition, Martini et al. [188] have questioned the
              | quantitative reliability of the crack-opening method because it is influenced by air
              | humidity and other ambient conditions. Nevertheless, the technique offers a
              | straightforward method to determine relative strengths of bonds and compare them to
              | bulk values.
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              | 
text          |         Therefore, low-temperature (400 °C or less) hydrophilic fusion bonding to SiO2
              | produces reasonably strong bonds, between 30%-70% of the bulk Si/Ge strength. It also
              | appears that the island configuration improves the strength of the attachment. Overall,
              | while much weaker than Cu-Cu or AlGe bonding techniques, fusion bonding provides
              | strong-enough connection to successfully complete further processing steps (such as
              | CMP).
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              | 
title         | 7.8     Fusion island bonding – design considerations
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text          |         For fusion bonding of patterned wafers, one important design consideration is
              | the island layout. Depending on the height of the island features (2h) and the spacing
              | between islands (2R), there could be an unwanted collapse of the ceiling where the
              | donor and acceptor wafers touch in places that should be open gaps. This scenario
              | occurs due to local elastic deformations of both mating wafers and has been modeled by
              | Q.-T. Tong and H. Gösele [79].
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              | 
              | 
              | 
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text          | Figure 7.15: Local elastic deformation of mating wafers could yield to ‘ceiling collapse’
              |                         causing undesired fusion bond in certain areas.
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              | 
text          |        In order for gaps between islands not to close during fusion bonding, the
              | minimum island height (2h) required is dependent on Young’s modulus (E) of both
              | wafers, thickness of the wafers (tw), and the average surface energy of the two materials
              | (γ). In addition, modified Young’s modulus can be calculated as E’ = E/(1-ν2), where ν
              | is Poisson ratio (0.28 for Si) [186]. Therefore, in the case of two identical silicon
              | wafers, the condition is:
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              | 
text          |                    R2
              |         h>                    , when R >> h and R >> 2tw,
              |                  2 '
              |                    E tw / γ
              |                  3
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text          |              7     Rγ
              |         h>            , when R >> h, R <2tw.
              |              2     E'
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              | 
text          | For example, considering island arrays separated by 2R = 5 mm of empty space, the
              | minimum island height of h > 870 nm is required so that tw = 0.525 mm thick silicon
              | wafer pair (E ~169 GPa) does not close the open-space gaps.
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              | 
text          |        Thus, as a design layout rule, as long as island features are less than 2R = 0.5
              | mm apart, the possibility of unintended bonding in the gap areas is significantly
              | reduced, since the island height needed is only h > 30 nm (assuming γ ~ 200 mJ/m2
              | before annealing).
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              | 
              | 
              | 
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title         | 7.9    Conclusions
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text          |        Fusion bonding does provide an elegant method to attach single-crystal silicon
              | and germanium islands onto amorphous substrates without requiring intermediate
              | materials to achieve bonding. However, this process simplicity is counterbalanced by
              | stringent surface smoothness requirement that could be satisfied by CMP, or alleviated
              | by chemical surface activation. The resulting hydrophilic Si-SiO2, SiO2-SiO2 and Ge-
              | SiO2 bonds are weaker than thermo-compressive bonds, such as Cu-Cu or AlGe eutectic
              | bonds. However, with chemical surface activation and 3DIC compatible annealing,
              | fusion bonding is strong enough to endure further processing, including SmartCut® and
              | CMP. Finally, the use of island structures has been found to significantly reduce the
              | occurrence of thermally induced voids, while also increasing the bond strength.
              | Therefore, due to aforementioned reasons, hydrophilic fusion bonding offers an
              | attractive method to achieve low-temperature 3DICs via crystal island attachment.
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              | 
              | 
              | 
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title         | Chapter 8 – Conclusion
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              | 
text          |        Three-dimensional (3D) integration of semiconductor devices offers the
              | advantages of denser circuits, lower power consumption and greater speed over
              | conventional (2D) integrated-circuit technology in which all transistors are fabricated in
              | one plane. In order to reap these benefits, it is critical to have high vertical interconnect
              | density between layers, a requirement that is best met by monolithic integration.
              | However, because monolithic 3DIC approach involves sequential fabrication of circuits
              | over pre-existing layers, stringent temperature limits are imposed on upper layer
              | processing steps in order to maintain the underlying device integrity.
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              | 
title         | 8.1 Summary of results
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text          |        This thesis addressed the fundamental challenge of obtaining single-crystal,
              | device-quality semiconductor islands for fabrication of upper layer circuits of a
              | monolithic 3DIC. We have shown that seedless laser crystallization of silicon could
              | form high quality, oriented crystals on amorphous templates by graphoepitaxy, but at
              | process temperatures incompatible with 3DIC applications. A more straightforward
              | approach of attaching high-quality crystalline islands for upper-layer devices was
              | successfully demonstrated using a variety of low-temperature bonding methods in
              | combination with SmartCut® and CMP.
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              | 
text          |        Feasibility of using transient laser annealing for monolithic 3DIC fabrication
              | was evaluated using one-dimensional thermal diffusion model. We found that single 15
              | µs pulse could melt and recrystallize thin α-Si layers on top of 5 µm of thermally
              | insulating SiO2, while maintaining the underlying circuit layers below 450 °C. Thus,
              | we constructed experimental apparatus consisting of 10W cw Nd:YAG laser operating
              | at 532 nm wavelength, acousto-optic modulator allowing for µs pulse lengths, as well as
              | illumination and imaging systems.
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              | 
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text          |        Graphoepitaxy via transient laser annealing of both silicon and germanium was
              | explored as a method to achieve oriented high-quality crystal islands on amorphous
              | substrates. In an effort to impart superior orientation control, novel nano-grating
              | templates of 190 nm pitch were fashioned in amorphous SiO2 using nanoimprint
              | lithography (NIL). However, results of experiments using pulsed cw, scanned cw as
              | well as excimer laser anneals produced randomly oriented grains 30 nm to several
              | microns in size, with no preferential crystal orientation. Two-dimensional (2D) relief
              | pattern of inverted pyramids, on the other hand, demonstrated high degree of in-plane
              | <001> as well as out-of-plane <100> Si crystal orientation matching the underlying
              | template exactly. Moreover, we found grains up to 500 nm in size to be virtually defect-
              | free. However, closer examination of the thermal profiles during laser annealing
              | revealed significant heating of the substrate, which facilitated the growth of large and
              | preferentially oriented crystals by limiting undercooling, but at the same time made the
              | process 3DIC incompatible.
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              | 
text          |        To gain better understanding of the crystallization process, we developed a
              | simulation algorithm that models the homogeneous and heterogeneous nucleation and
              | grain-growth phenomena in laser-melted semiconductor films. We found that inherently
              | large thermal gradients develop between laser-melted semiconductor liquid (>937°C)
              | and the underlying substrate (<400°C), causing very fast cooling rates, on the order of
              | 300 °C/µs. Consequently, the quickly undercooled liquid triggers uncontrolled
              | spontaneous nucleation that limits both the size and quality of resulting grains. The
              | validity of the simulation was supported with the experimental results of rapid melt
              | growth (RMG) of Ge from attached Si (100) seeds. Ultimately, it became clear that
              | successful graphoepitaxy requires significant substrate heating that is unacceptable for
              | 3DIC applications.
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              | 
text          |        Alternatively, we pursued a more direct approach of attaching high-quality
              | crystal islands directly on top of fabricated circuits for upper-layer device fabrication. A
              | variety of low-temperature (≤400 °C) bonding methods were investigated and optimized
              | for monolithic 3DIC application: fusion bonding (SiO2-SiO2, Si-SiO2, Ge-SiO2),
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              | 
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text          | *    Surface roughness requirement has not been explicitly determined. The quoted values for Cu-Cu, Ti-Ti and Al-Ge bonding
              |      indicate the largest measured surface roughness of samples that bonded successfully (AFM, 5x5 µm area).
              | **   Bond strength not measured quantitatively, but known to be strong (razor blade test cracks Si bulk rather than the bond).
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              | 
text          |                 Table 8.1: Summary of low-temperature bonding techniques for monolithic 3D integration.
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              | 
              | 
              | 
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text          | thermo-compressive bonding (Cu-Cu, Ti-Ti), as well as AlGe eutectic bonding. Results
              | of these experiments are summarized in Table 8.1. In particular, we deemed AlGe
              | eutectic bond to be especially attractive with superior strength (~50 J/m2), low void
              | formation, relaxed surface roughness requirement, hermetic seal, conductive path, use
              | of thin films and CMOS friendly materials.
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              | 
text          |        Finally, a full 3DIC-compatible process to transfer bulk-quality crystalline Si
              | and Ge islands onto SiO2 substrates was developed. After bonding, the process relies on
              | hydrogen ion-induced exfoliation (SmartCut®) to remove the bulk of the donor wafer,
              | while the splitting damage is polished away with touch-CMP technique. Finally, planar
              | topography was achieved by CMP planarization of inter-island dielectric. A clean, flat
              | canvas not only allows easier fabrication of upper-layer devices, it also ensures vertical
              | extendibility of sequential island transfer process for multi-layer monolithic 3DIC.
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              | 
title         | 8.2 Monolithic 3-D integration of FPGA
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text          |        For applications involving heavy communication between memory and logic,
              | such as field-programmable gate array (FPGA), monolithic 3D integration is poised to
              | provide the ultimate bandwidth, resulting in significant performance gains.
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              | 
              | 
              | 
text          | Figure 8.1: Area reduction of an FPGA circuit in a 3-layer implementation (LB – logic
              |   block; CB – connection block; SB – switch block); a) 2D layout; b) 3D layout, with
              |    memory split out of SBs onto a separate 3rd layer. The vertical integration of three
              |                  distinct blocks substantially reduces circuit area [189].
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              | 
              | 
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text          |        The FPGA is an inherently interconnect-limited technology with three distinct
              | and easily separable functions – logic blocks, connection blocks and switching blocks
              | (Fig. 8.1). Splitting the three functions vertically, heterogeneous integration would
              | create a 3D-FPGA. Re-implementation of a baseline 2-dimensional Xilinx Virtex II
              | FPGA (65nm technology) as a 3D circuit was calculated to offer numerous advantages:
              | 3.2X reduction in area, 1.7X reduction in average critical delay, as well as 1.7X
              | reduction in total dynamic power consumption [189]. Moreover, these advantages
              | improve with smaller technology nodes. Thus, in order to experimentally demonstrate
              | these benefits, we are currently implementing a fully low-temperature monolithic 3D-
              | FPGA process using high performance Ge MOSFET 2nd layer switching devices in
              | conjunction with resistance-change memory (RCM) cells as the 3rd layer (Fig. 8.2). In
              | particular, Ge (100) crystal islands are attached using chemically activated Ge-SiO2
              | fusion bonding.
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              | 
              | 
              | 
text          | Figure 8.2: Three-dimensional FPGA implementation pursued by Stanford University.
              |  Switching devices in the 2nd layer are Ge MOSFETs, while the third layer consists of
              |                        resistance-change memory (RCM) cells.
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              | 
              | 
              | 
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title         | 8.3 Final thoughts
blank         | 
text          |        Realization of fully functional monolithic 3DIC circuits such as 3D-FPGA is
              | certainly a promising path towards demonstrating the wide-reaching gains of vertical
              | integration. However, there are many other areas that merit further research.
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              | 
text          |        In the case of laser crystallization and graphoepitaxy, even if only small (30-50
              | nm) sized islands are achievable, they can still be used for device fabrication. Given that
              | new generations of devices have very small (<32nm) critical dimensions, one could
              | conceivably fabricate one device per grain, provided that the channel region is defect
              | free. For example, a method that could pre-determine the location of grain boundaries
              | (such as surface nano-asperities in Chapter 2) would open the door for possible high
              | performance devices in laser-induced microcrystalline islands.
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              | 
text          |        Furthermore, in the area of bonding, the full potential of sub-eutectic AlGe
              | bonding capabilities could be investigated further. In particular, the technique seems to
              | maintain many of its advantages well below eutectic temperature, as it becomes more
              | thermo-compressive in nature. Given the high mobility of inter-diffusing Al and Ge
              | atoms in solid phase, sub-eutectic AlGe bonding may become the preferred low-
              | temperature attachment technique. Overall, one cannot be unimpressed by the sheer
              | versatility of the different low-temperature bonding methods. The plethora of material
              | choices, thicknesses, adhesion strengths, sealing properties, electrical connections, as
              | well as temperature requirements provides a well-stocked bonding toolbox that could
              | effectively solve many heterogeneous integration challenges. The ability to place and
              | attach islands of any material onto almost any surface at low-temperature brings the
              | science of bonding out of the packaging realm and into the forefront of heterogeneous
              | microstructure engineering.
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              | 
              | 
              | 
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title         | Appendix A - CMP process and cleaning
blank         | 
              | 
text          |        The use of chemical mechanical polishing (CMP) is indispensable in the context
              | of 3DICs. Just as multiple steps of planarization of inter-layer dielectrics (ILDs) are
              | required to achieve the multiple levels of back-end metal interconnects, it is also
              | essential to planarize upper active layers for a viable 3DIC.
blank         | 
              | 
text          |        In the scope of this work, CMP has been mainly utilized for two purposes:
              | firstly, for smoothening surfaces to make them suitable for fusion bonding (Chapter 7),
              | and secondly, for polishing of SmartCut® induced surface damage (Chapter 4).
              | However, CMP usefulness extends to planarization of laser-crystallized semiconductor
              | islands [79] in order to make them suitable for device fabrication.
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              | 
text          |        Comprehensive review of CMP technology can be found in M. R. Oliver’s book
              | “Chemical-Mechanical Planarization of Semiconductor Materials” published by
              | Springer in 2004 [190]. In this appendix, experimental procedure and parameters used
              | for 3DIC applications are reported.
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              | 
title         | A.1 Experimental procedure
blank         | 
text          |        All polishing was performed on G&P Technologies POLI-400L research 4-inch
              | wafer CMP tool. It is a single table, two head system, one for polishing and the other for
              | conditioning. The table rotational speed was set at 50 rpm, while the head was rotating
              | at 30 rpm. Polishing pressure applied was 200/300 psi (wafer/ring). Polishing time
              | varied with application.
blank         | 
              | 
text          |        Slurry used for most experiments was Ultra-SolTM S10 colloidal silica slurry,
              | with pH of 10 and mean particle size around 70 nm. The S10 formulation was originally
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              | 
              | 
              | 
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text          | designed specifically for polysilicon polishing applications. In addition, a neutral
              | version Ultra-Sol 3EX with pH of 7.3 was also tested for SiO2 polishing.
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              | 
text          | The pad used for polishing was R&H IC1000 stacked K-groove type. It is quite hard,
              | has low compressibility, low slurry capacity, and is commonly used for shallow trench
              | isolation (STI). Such hard and incompressible pads were chosen because they are best
              | for uniform polishing of raised structures over the whole wafer [190]. Also they
              | perform well for standard full wafer roughness removal polishing.
blank         | 
              | 
text          | The standard CMP procedure for all types of polishing was as follows:
blank         | 
text          |    1. Condition the pad (10 minutes, DI water)
              |    2. Cyclical dummy polish/conditioning (3x)
              |            a. Dummy polish (1 minute, slurry)
              |            b. Conditioning the pad (1 minute, slurry)
              |    3. Hand brush cleaning of the pad (1 minute, DI water)
              |    4. Pad saturation (slurry)
              |    5. Actual polish of real wafer (slurry)
              |    6. Submerge wafer in DI water bath immediately after polishing
              |    7. Scrub both surfaces of the wafer with PVA sponge (1 min, DI water)
              |    8. Blow dry the cleaned wafer with N2 gun
              |    9. Post CMP decontamination
blank         | 
text          | Note: the polishing dummy should preferably be of the same material as the real wafer
              | to be polished. Hand brush is used to remove any unwanted particles from the polishing
              | pad that could cause unwanted scratching to occur.
blank         | 
              | 
title         | A.2 Results of CMP experiments
blank         | 
text          |        Polishing rates for crystalline silicon islands (~50% fill ratio) at the above-
              | described polishing conditions is 280 nm/min (Fig. A.1). Semiconductor crystal
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              | 
              | 
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text          | polishing is most likely to be used for removal of the SmartCut® H+ ion induced
              | splitting damage. The goal is to remove the top damaged layer (~50 nm), as well as to
              | make it sufficiently smooth for subsequent upper layer device fabrication.
blank         | 
              | 
              | 
              | 
text          |     Figure A.1: Time progression of CMP polish of Si (100) islands (50% fill ratio)
              |             using Ultra-Sol S10 slurry with table/head speed of 60/30 rpm,
              |                            and polishing pressure of 200 psi.
blank         | 
              | 
text          |        In order to determine post-CMP surface condition, AFM scans were performed
              | to measure the resulting roughness, and develop proper cleaning procedures. Figure A.2
              | illustrates the critical cleaning step, which uses wet polyvinyl alcohol (PVA) sponge to
              | remove the slurry residue immediately after polishing. PVA does not cause any
              | mechanical scratching of the surface, while its cellular network structure continually
              | flushes DI water and collects surface residue of colloidal silica. The final surface
              | roughness of polished Si (100) islands was about 0.416 nm RMS. While this is much
              | rougher than the commercially available Si wafers (0.142 nm RMS), it is smooth
              | enough for upper layer 3DIC application.
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              | 
              | 
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text          | Figure A.2: CMP of Si (100) islands leaves speckled slurry residue (a), which can be
              | removed by wet PVA sponge scrub (b), bringing the surface roughness to 0.416 nm
              |          RMS. Reference Si prime wafer (c). All AFM scans are 5x5 µm.
blank         | 
              | 
              | 
              | 
text          |   Figure A.3: Time progression of CMP polish of LPCVD deposited SiO2 (LTO)
              |           using Ultra-Sol 3EX slurry with table/head speed of 60/30 rpm,
              |                          and polishing pressure of 200 psi.
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              | 
              | 
              | 
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text          |        Similarly, CMP removal rate of bulk low-temperature SiO2 (LTO), using Ultra-
              | Sol S-10 slurry was 67 nm/min (not shown), while the use of Ultra-Sol 3EX slurry
              | increased the bulk removal rate to 75 nm/min (Fig. A.3).
blank         | 
              | 
text          |        More importantly, the surface roughness of the deposited SiO2 falls below 0.3
              | nm RMS within first 60 seconds of polishing (see Chapter 7). Therefore, CMP can be
              | successfully used to prepare planar surfaces that could successfully undergo fusion
              | bonding because the surface roughness becomes less than 0.5 nm RMS.
blank         | 
              | 
text          |        Finally, chemical mechanical polishing of germanium was studied. Little has
              | been reported in literature on Ge polishing, and most CMP processes mentioned involve
              | colloidal silica (~200nm in size) and KOH chemical ingredient [191]. Therefore, the
              | standard CMP procedure using Ultra-Sol S10 slurry was pursued and characterized. The
              | removal rate of epitaxially grown Ge (100) was around 30 nm/min. The rate could be
              | significantly increased with small amounts of hydrogen peroxide (H2O2) dissolved into
              | the slurry (Fig. A.4a) [192]. However, to achieve smooth surfaces, the peroxide free
              | S10 slurry formulation was sufficient. Figure A.4b depicts an extremely smooth
              | epitaxial Ge (100) surface that is suitable for hydrophilic fusion bonding (Ge-SiO2).
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              | 
              | 
              | 
text          | Figure A.4: a) Germanium removal rate vs. H2O2 concentration in slurry [192]; b) AFM
              |   scan (1x1μm) of epi-Ge (100) surface after 60 sec CMP using S10 slurry (no H2O2).
              |                            The RMS roughness is 0.158 nm.
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              | 
              | 
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title         | A.3 Attached island isolation (STI variant) process development
blank         | 
text          |        Attaching crystalline semiconductor islands for upper layer 3DICs creates a
              | bumpy topography on the wafer. In order to successfully integrate multiple layers,
              | planarization of each layer is crucial. Thus, a process much like the shallow trench
              | isolation (STI) is utilized to fill the channels between the islands with a dielectric and
              | planarize the final surface.
blank         | 
              | 
text          |        Initially, conformal LPCVD low temperature silicon dioxide was deposited
              | directly over the attached crystal islands. The excess SiO2 was polished away by CMP
              | using Ultra-Sol S10 slurry (Fig. A.5a). However, because the slurry is formulated for
              | polysilicon polishing, with approximate selectivity between Si:SiO2 of 3:1, it
              | preferentially removed Si islands causing severe dishing (Fig. A.5b).
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              | 
              | 
              | 
text          |   Figure A.5: a) LPCVD deposited conformal SiO2 fills the gaps between the attached
              |  crystal islands, and the excess is polished off by CMP; b) poor selectivity between Si
              |                          and SiO2 causes severe dishing to occur.
blank         | 
              | 
text          |        In order to prevent dishing, an extra layer of silicon nitride (SiN) is introduced
              | underneath the SiO2 as a polish stop. As a test, 40 nm of low-stress LPCVD SiNx was
              | deposited at 870 °C, even though low temperature alternatives, such as PECVD SiN
              | could be deposited at 350 °C or below [193]. In the case of Ultra-Sol S10 slurry used,
              | the ratio of removal rates between SiO2 and SiNx was measured to be 4:1. Therefore,
              | with the polish stop in place, the CMP of deposited dielectric SiO2 halted upon reaching
              | the silicon nitride layer. The resulting planarization of the dissimilar materials is
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              | 
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text          | depicted in Fig. A.6, where the thin SiN layer is highlighted in red colour. Some SiO2
              | dishing still occurred, however it was rather small (<100 nm over a 10 µm wide trench).
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              | 
              | 
              | 
text          | Figure A.6: a) CMP of deposited SiO2 dielectric isolation stops once the buried silicon
              | nitride (SiN) layer is reached; b) cross-sectional SEM of the resulting planarity between
              |                             the Si island and the SiO2 filling.
blank         | 
              | 
text          |        The final step in the process would be to chemically remove the SiNx polish stop
              | layer in hot phosphoric acid (H3PO4), making islands both planar, electrically isolated,
              | and ready for device fabrication. Therefore, thanks to attached island isolation process
              | (STI variant), multiple layers of planarised islands isolated by dielectric filling could be
              | integrated as a part of a 3DIC.
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              | 
title         | A.4 Post CMP decontamination
blank         | 
text          |        Removing potential contaminants after CMP processing is necessary to ensure
              | proper operation of semiconductor devices. Since most industrial slurries used for
              | polishing silicon contain KOH solution, including Ultra-Sol S10, it is critical to
              | properly remove any traces of highly mobile K+ ions, as well as metallic contaminants
              | and remaining surface particles.
blank         | 
              | 
text          |        Standard decontamination procedures for silicon wafers involve dipping them in
              | RCA-2 bath of HCl:H2O2:H2O (1:1:5) at 70 °C for 20 minutes. However, this method is
              | not suitable for Ge layers due to high etching rates in H2O2 containing solutions. Thus, a
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              | 
              | 
              | 
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text          | low-consumption, and non-roughening method needs to be developed for Ge post-CMP
              | clean.
blank         | 
              | 
text          |          C. Deguet et al. [194] have developed a proprietary Ge cleaning process that is
              | low-consumption that leaves surface with metallic contamination levels below 5x1010
              | at/cm2, with good particle-removal efficiency and no deterioration in surface roughness.
              | In our case, we pursued a more straightforward approach of cyclical dips in HCl:H2O
              | (1:1) at 60 °C for 1 minute, followed by multiple DI water rinses. While it does not
              | attack Ge and has minimal impact on surface roughness, the cleaning efficacy of this
              | process has not been specifically characterized.
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              | 
              | 
              | 
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title         | Appendix B - Epitaxial Germanium Growth Process
blank         | 
              | 
              | 
text          |        Germanium, as noted before, has superior semiconductor properties to silicon,
              | which make it an attractive choice for upper layer active devices of a 3DIC. However,
              | to harness the advantage of high mobility electrons and holes, defect free germanium
              | crystal material is required. Traditionally, Czochralski grown Ge bulk wafers, such as
              | those supplied by Umicore®, provide perfect Ge crystal lattice ideal for device
              | fabrication. However, due to their prohibitive cost, Ge bulk wafers have been replaced
              | with relaxed epitaxial germanium layers grown on Si (100) substrates. The 4% lattice
              | constant mismatch between Si and Ge must be absorbed either through a SiGe buffer
              | layer [195], or by relaxing the epitaxial layer through multiple hydrogen anneals [196].
              | Following the MHAH method by Nayfeh et al. [197], a thick (~1.5 µm) epitaxial Ge
              | layer is fabricated on Si substrate with final defect density of less than 106 /cm2 and
              | surface roughness under 1.6 nm RMS. This technique has been used in this work.
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              | 
text          |        Another significant advantage of using epi-Ge layer on Si bulk wafer is that the
              | thick Si wafer dominates the thermal expansion coefficient. Because the acceptor wafer
              | is also made of silicon, the coefficients are matched, simplifying the bonding process.
              | Specifically, there is less chance of bond failure or structural defects arising during
              | annealing due to stresses caused by material mismatch, as is the case when bonding
              | bulk Ge to bulk Si wafers.
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              | 
text          |        Full description of the relaxed epi-Ge growth process to create donor crystalline
              | material for GeOI substrates can be found in [194]. In this appendix, experimental
              | procedure and parameters used for epitaxial Ge material growth using MHAH method
              | for 3DIC islands are reported.
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              | 
              | 
              | 
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title         | B.1 Experimental procedure of epi-Ge growth
blank         | 
text          |        Germanium deposition was performed in an Applied Materials Centura
              | Epitaxial System, starting with a diffusion cleaned Si (100) 4-inch wafer. The basic
              | procedure involves growing multiple Ge layers that are successively annealed at high
              | temperatures (825 °C) in order to relax the layer, thus confining the misfit dislocations
              | near the heterogeneous interface, leaving a high-quality Ge surface at the top (Fig. B.1).
              | In addition, hydrogen anneals enhance atomic surface diffusion of Ge-H groups,
              | resulting in smoother films.
blank         | 
              | 
              | 
              | 
text          |    Figure B.1: a) A 155 nm thick epi-Ge layer grown at 400 °C shows defects at the
              | heterogeneous interface, while b) illustrates that successive Ge layer growth (at 400 °C)
              | with hydrogen anneals (at 825 °C) produce a high-quality crystal near the surface [196].
blank         | 
              | 
text          | The standard 3-layer recipe which epitaxially grew ~1μm Ge layer was as follows:
blank         | 
              | 
text          |    1. Diffusion clean Si (100) 4-inch wafer with a final 2% HF dip.
              |    2. Bake the wafer in H2 atmosphere at 1100 °C for 5 min to remove native oxide.
              |    3. Ge growth at 425 °C, 30 Torr, for 3 minutes yielding ~ 200 nm.
              |            Gas flows: 25 sccm (100% Ge), 5 slm (H2).
              |    4. Hydrogen anneal at 825 °C, 50 Torr for 30 minutes.
              |    5. Ge growth at 600 °C, 30 Torr, for 3 minutes yielding ~ 350 nm.
              |            Gas flows: 25 sccm (100% Ge), 5 slm (H2).
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              | 
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text          |    6. Hydrogen anneal at 800 °C, 50 Torr for 5 minutes.
              |    7. Repeat steps 5 and 6 for the 3rd layer of Ge.
              |    8. Deposit LPCVD SiO2 capping layer (~20 nm).
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              | 
title         | B.2 Characterizing epi-Ge surface quality
blank         | 
text          |        Typical epi-Ge film grown is show in Fig. B.2. The cross-section indicates Ge
              | film thickness of 914 nm, while the 20x20 µm AFM scan measures surface roughness
              | of 2.03 nm RMS. The top portion of the epitaxial Ge layer that has low defect density
              | (106 cm-2) could be transferred onto an acceptor wafer (via bonding and SmartCut®),
              | thus paving the way toward building Ge devices on upper layers of monolithic 3DICs.
blank         | 
              | 
              | 
              | 
text          |   Figure B.2: Cross-sectional SEM of grown epi-Ge (100) layer that is 914 nm thick.
              |  The corresponding 20x20 µm AFM scan, indicating 2.03 nm RMS surface roughness.
              |   Note: relief of the epi-Ge layer in the SEM is due to cleaving process and not due to
              |                                     crystal defects.
blank         | 
              | 
text          |        It is important to note that a longer, 5 layer epi-Ge recipe could grow thicker
              | films with smoother surfaces, due to the compounding affect of multiple hydrogen
              | anneals. However, the ultimate Ge surface smoothness achieved via MHAH method is
              | about 1.5 nm RMS, as shown in Fig. B.3.
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              | 
              | 
              | 
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text          |   Figure B.3: AFM scan (20x20 µm) of 5 layer epi-Ge showing characteristic “cross-
              |   hatch” pattern along the <110> direction with a spatial wavelength of the order of a
              |  micron, superimposed on mounds the size of several microns, with maximum peak to
              |          valley height of ~ 11 nm. The thickness of the epi-Ge film is 2.2 µm.
blank         | 
              | 
text          |        As grown epitaxial Ge surfaces are therefore too rough for successful low
              | temperature hydrophilic fusion bonding (Ge-SiO2). Consequently, attempts to smoothen
              | the surface would require either higher hydrogen anneal temperature or an extra polish
              | (CMP) step – see Appendix A.
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              | 
              | 
              | 
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