From 489700e61ca4d8fdc1306a5775645df364097570 Mon Sep 17 00:00:00 2001
From: "Korbel, Max" <max.korbel@intel.com>
Date: Mon, 11 Aug 2025 16:54:04 -0700
Subject: [PATCH] Fix register increment amount and larger registers args

---
 lib/src/memory/csr/csr_block.dart     | 6 +-----
 lib/src/memory/csr/csr_container.dart | 5 +++++
 lib/src/memory/csr/csr_top.dart       | 9 +++------
 3 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/lib/src/memory/csr/csr_block.dart b/lib/src/memory/csr/csr_block.dart
index 3f36c4259..43551c126 100644
--- a/lib/src/memory/csr/csr_block.dart
+++ b/lib/src/memory/csr/csr_block.dart
@@ -24,10 +24,6 @@ class CsrBlock extends CsrContainer {
   /// CSRs in this block.
   final List<Csr> csrs;
 
-  /// What increment value to use when deriving logical addresses
-  /// for registers that are wider than the frontdoor data width.
-  final int logicalRegisterIncrement;
-
   /// Direct access ports for reading and writing individual registers.
   ///
   /// There is a public copy that is exported out of the module
@@ -51,7 +47,7 @@ class CsrBlock extends CsrContainer {
     required super.frontWrite,
     required super.frontRead,
     super.allowLargerRegisters,
-    this.logicalRegisterIncrement = 1,
+    super.logicalRegisterIncrement,
     super.reserveName,
     super.reserveDefinitionName,
     String? definitionName,
diff --git a/lib/src/memory/csr/csr_container.dart b/lib/src/memory/csr/csr_container.dart
index d5f51d35e..ccd8c5bac 100644
--- a/lib/src/memory/csr/csr_container.dart
+++ b/lib/src/memory/csr/csr_container.dart
@@ -54,6 +54,10 @@ abstract class CsrContainer extends Module {
   /// to any register that exceeds the data width of the frontdoor.
   final bool allowLargerRegisters;
 
+  /// What increment value to use when deriving logical addresses
+  /// for registers that are wider than the frontdoor data width.
+  final int logicalRegisterIncrement;
+
   /// Constructs a base container.
   CsrContainer(
       {required Logic clk,
@@ -62,6 +66,7 @@ abstract class CsrContainer extends Module {
       required DataPortInterface? frontRead,
       required this.config,
       this.allowLargerRegisters = false,
+      this.logicalRegisterIncrement = 1,
       super.reserveName,
       super.reserveDefinitionName,
       String? definitionName})
diff --git a/lib/src/memory/csr/csr_top.dart b/lib/src/memory/csr/csr_top.dart
index 587af2f71..4c6af5d02 100644
--- a/lib/src/memory/csr/csr_top.dart
+++ b/lib/src/memory/csr/csr_top.dart
@@ -18,10 +18,6 @@ import 'package:rohd_hcl/src/memory/csr/csr_container.dart';
 /// MSBs of the incoming address and registers within the given block
 /// are addressable using the remaining LSBs of the incoming address.
 class CsrTop extends CsrContainer {
-  /// What increment value to use when deriving logical addresses
-  /// for registers that are wider than the frontdoor data width.
-  final int logicalRegisterIncrement;
-
   /// Configuration for the CSR Top module.
   @override
   CsrTopConfig get config => super.config as CsrTopConfig;
@@ -91,7 +87,7 @@ class CsrTop extends CsrContainer {
       required super.frontWrite,
       required super.frontRead,
       super.allowLargerRegisters,
-      this.logicalRegisterIncrement = 1,
+      super.logicalRegisterIncrement,
       super.reserveName,
       super.reserveDefinitionName,
       String? definitionName})
@@ -125,7 +121,8 @@ class CsrTop extends CsrContainer {
           reset: reset,
           frontWrite: blockFdWrite,
           frontRead: blockFdRead,
-          allowLargerRegisters: allowLargerRegisters));
+          allowLargerRegisters: allowLargerRegisters,
+          logicalRegisterIncrement: logicalRegisterIncrement));
     }
 
     for (var i = 0; i < blocks.length; i++) {